KR0120716B1 - And-or-not combination trigger circuit in bus information processing unit - Google Patents

Abstract

The AND-OR-NOT combination trigger circuit in a bus information processing unit provides the bus information processing unit with a combination trigger circuit which includes AND logic, OR logic, and NOT logic in each trigger condition, so as to effectively perform data detection. The AND-OR-NOT combination trigger circuit includes a reference cell consisting of a predetermined number of logic devices to satisfy a desired detecting trigger condition by AND-OR-NOT combination and a common cell consisting of a predetermined number of logic devices to satisfy a desired detecting trigger condition.

Description

A AND-OR-NOT combination trigger circuit in Bus Information Processing Unit

1 is a diagram showing a hierarchical combination trigger condition of the present invention.

2 shows an instruction register map supporting the combination trigger condition of the present invention.

3 shows a combination circuit that supports the combination trigger condition of the present invention.

4 is a view showing the overall concept of a combination circuit supporting the combination trigger condition of the present invention according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AND-OR-NOT combination trigger circuit in a bus information processor. Specifically, the present invention relates to a combination of AND logic, OR logic, or nat logic of each trigger item. The present invention relates to an end-or-natt combination trigger circuit in a bus information processor that supports combination trigger logic so that a user can retrieve bus data with various trigger conditions.

Conventionally, in using a trigger condition using many signals driven on a system bus as a trigger item, there are many limitations in using a trigger condition by providing only an AND logic condition in a conventional method.

In fact, when a trigger condition is specified for signals driven on a bus, a large number of logical combinations exist, and when implemented in hardware, there is a problem of enormous cost and time.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a combination trigger circuit such as an ANDLOGIC, an ORLOGIC and a natlogic in a bus information processor.

In order to achieve the above object, the present invention will be described in detail based on the accompanying drawings.

First, FIG. 1 is a logic trigger condition composed of a three level hierarchy provided by the bus information processor in order to support most combination trigger conditions that are meaningful at a minimum cost.

Basically, AND logic trigger condition is used when you want to search the situation when two or more random signals are driven at the same time. OR logic trigger condition is one or more of several signals presented as trigger condition. It is used to search the situation when the signal is driven.

The NOT logic trigger condition is used to search for a situation in which one trigger line excludes a trigger condition presented for each bit.

Looking at the logic trigger condition of step 1, the address arbitration bus group (ARG) partially provides the AND logic trigger condition and the oralogic trigger condition.

The Address Bus Group (AG) partially provides the ANDLOGIC trigger condition and the natlogic trigger condition.

The Address Status Bus Group (AkG) also partially provides an ANDlogic trigger condition and an OR logic trigger condition.

The Data Arbitration Bus Group (DRG) provides only the logic logic condition.

The Data Bus Group (DG) provides partial and logical trigger conditions and natlogic trigger conditions.

The Data Status Bus Group (DkG) provides both an ANDLOGIC trigger condition and an ORLOGIGIG trigger condition.

The logic trigger condition for each bus group of the data transfer bus is supported not only in the bus clock trigger condition but also in the transaction trigger condition.

The data transfer bus group (DTB), which is a two-stage logic trigger condition, is composed of each of the subdivided bus groups (ARG, AG, AkG, DRG, DG, and DkG) and provides only an logic logic condition.

The data transmission bus group (DTB) has a hierarchical structure, which constitutes a combination trigger condition for subgroups of the data transmission bus.

The Interrupt Bus Group (IBG), a one-stage logic trigger condition, provides both an ANDLOGIC trigger condition and a natlogic trigger condition. The UT (Utility Bus Group) provides an ANDLOGIC trigger condition and an oLogic trigger. Partially provides the condition.

The two-level logic trigger condition, the data bus group (DTB), the one-level logic trigger condition, the interrupt bus group (IBG), and the utility bus group (UG) are again grouped as an AND logic trigger condition to form a higher hierarchy of the three-level logic trigger condition. To form.

This constitutes a combination trigger condition for each group of system buses.

Next, FIG. 2 shows a bit-by-bit map of an instruction register for hardwarely supporting the combination trigger condition.

The lower 8 bits of the 32-bit instruction register are used to support the combination trigger condition.

Bits 7 through 4 are used to support the Not Logic trigger condition, which is stored as Logic 1 if the user wants to use the Not Logic trigger. Bit 3 to Bit 0 are used to support AND logic trigger condition and OR logic trigger condition.If user wants to use ORLogic trigger, save as Logic 1 and use as ANDLogic trigger. If it is stored as logic 0.

3 is a circuit diagram generalizing a method for supporting the combination trigger condition of the present invention with data of the command register, mask register of the function control section of the bus information processor, data of the data register, and bus data provided from the bus matching section. One embodiment is shown.

For example, a combination trigger condition can be made into eight combinations as follows using signals A and B as trigger items.

A and B, (Nat A) and B, A and (Nat B), (Nat A) and (Nat B), A ora B, (Nat A) Ora B, A ora (Nat B), and (Nat A) A) There are oats (knot B).

Each of the above trigger conditions A and B has one of logic 1, logic 0, and logic x (don't care), and the data in the mask register (mask A, mask B) is the trigger condition A and B Stores data 0 when is logic 1 or logic 0, and stores data 1 when logic x.

Data in the data registers (data A, data B) stores data 1 when trigger conditions A and B are logic 1, data 0 when logic 0, and any value when logic x.

In addition, the value of natlogic (nat A, nat B) stores data 0 in the command register of FIG. 2 when using ANDLOGIC and data 1 when in ORLOGIC.

In the combination trigger condition of the present invention, when x (don't care) and B is used, x (don't care) is implemented as satisfying the trigger condition, and x (don't care) ora B is trigger condition. In this case, x (don't care) is implemented as not satisfying the trigger condition, and when (knot x) and B or (knot x) ora B is the trigger condition, knot x (don care) is reversed from the above. It is characterized by the implementation.

As an example according to the above features, the following eight combinations may exist when configuring a trigger condition using an address and a transfer type.

Addr and TT, (knot Addr) and TT, Addr and (knot TT), (knot Addr) and (knot TT)

Addr ora TT, (knot Addr) ora TT, Addr ora (knot TT), (knot Addr) ora (knot TT)

3 is a circuit supporting the eight combinations using two signals, that is, signal A and signal B as a trigger condition. The characteristic of this circuit is to configure one base cell for each signal, and to configure the common cell for outputting the final trigger satisfaction signal SAT by connecting the outputs of the base cells. In other words, the first stage logic trigger condition circuit of FIG. 1 configured for each signal is provided. Address Arbitration Bus Group (ARG), Address Bus Group (DGR), Address Status Bus Group (AkG), Data Arbitration Bus Group (DRG), Data Bus Group (DG), Data Status Bus Group (DkG) ), An interrupt bus group (IBG), a utility bus group (UG), and the like can all be configured by extending the circuit of FIG. Here, the trigger satisfaction signal SAT is 'SAT-ARG', 'SAT-AG'… according to each group. , 'SAT-UG', etc.

To illustrate FIG. 3, signal A assumes an address signal and signal B assumes a 'transmission type signal'.

In FIG. 3, the first Exclusive-NOR gate 1 inputs an address signal (bus Addr) driven on a bus and an address value (data Addr) stored in a data register as logic 1, If it is different, it outputs logic 0 and the first AND gate 2 inputs the inverted value of the mask value (mask Addr) stored in the mask resist and the output of the first exclusive-NOR gate 1 as input. The second AND gate 3 outputs an AND result by inputting a mask value (mask Addr) and an AND / OR value stored in the mask register.

The first OR gate 4 inputs the output value of the first AND gate 2 and the output value of the second AND gate 3 to output the OR result, and the first EXCLUSIVE-OR gate. (5) inputs an output value of the first OR gate 4 and a nat addr value stored in bit 7 of the instruction register shown in FIG. 2, and outputs logic 0 if it is the same and logic 1 if it is different.

The second exclusive-NOR gate 6 inputs a transmission type signal (bus TT) driven on the bus and a transmission type value (data TT) stored in the data register and outputs logic 1 if it is the same and logic 0 if it is different. And the third AND gate 7 inputs the output of the first exclusive-NOR gate 6 and the inverted value of the mask value (mask Addr) stored in the mast register, and outputs the AND result. The fourth AND gate 8 inputs a mask value (mask TT) and an AND / OR value stored in the mask register, and outputs an AND result.

The second OR gate 9 inputs the output value of the third AND gate 7 and the output value of the fourth AND gate 8 to output the OR result, and the second exclusive-OR gate. (10) inputs an output value of the second OR gate 9 and a nat TT value stored in bit 6 of the instruction register shown in FIG. 2, and outputs logic 0 if it is the same and logic 1 if it is different.

The fifth AND gate 11 inputs an output value of the first exclusive-OR gate 5, an output value of the second exclusive-OR gate 10, and an inverted value of the AND / OR value. Therefore, when the AND / Or value is logic 1, logic 0 is unconditionally outputted. When the AND / Or value is logic 0, the circuit outputs AND by outputting the two output values (5, 10).

In addition, the third OR gate 12 may convert the output value of the first exclusive-OR gate 5, the output value of the second exclusive-OR gate 10, and the inverted value of the AND / OR value. It is a circuit that outputs logic 1 unconditionally when the AND / or value is logic 0 and inputs and outputs the two output values 5 and 10 when the AND / OR value is logic 1.

The sixth AND gate 13 inputs the output value of the third OR gate 12 and the AND / OR value, and when the AND / OR value is logic 0, outputs an unconditional logic 0 and the AND / OR value is logic. 1, the circuit outputs the output of the third OR gate 12 as it is. Finally, the fourth OR gate 14 includes the output value of the fifth AND gate 11 and the sixth AND gate. This circuit outputs the trigger satisfaction signal by cutting the output value of (13).

Each AND / OA value is stored in the command register shown in FIG. 2. In this implementation, as described in FIG. 1, the OR and OR combinations are not allowed. The AND / OR value for is fixed to logic 0 without the need to store in the command register.

In addition, the number of inputs of the fifth AND gate 11 and the third orphan gate 12 is determined according to the number of signals constituting the trigger condition. In the case of the address group (AG) of FIG. It receives two signals (Address, AE, SI, AS, BE, TT, and / or (logic 0)) and outputs the result.

4 is an overall connection diagram consisting of one-step, two-step, and three-step logic trigger conditions. Data transfer bus group (DTB), a two-stage logic trigger condition, has six outputs: SAT-ARG, SAT-AG, SAT-AkG, SAT-DRG, SAT-DG, and SAT-DkG, which are outputs of the first-stage tissue trigger condition. The signal is ANDed to output a trigger satisfaction signal SAT-ALL. The first stage logic trigger condition groups (ARG, AG, AkG, DRG, DG, DkG, IBG, UG) are all configured by extending the logic trigger circuit of FIG.

Therefore, according to the present invention, even if the logic condition changes, it can be easily expanded, and only this optimum circuit can be configured according to the condition.

As described above, the present invention implements most combination trigger conditions desired by a user with minimum hardware cost by implementing only a minimum combination trigger condition having a meaningful meaning in providing combination trigger conditions such as ANDLOGIC, OLOGIC, and natlogic. Can support

In addition, it has a combination trigger condition composed of end-or-nat and can perform various and effective data retrieval.

Claims (3)

The signals of the respective trigger items are selectively ANDed by combining the signals of the trigger items such as the bus, data, and mask signals in the bus information processor with the end, oA, and nat signals, which are preset according to a user's desired trigger condition. A basic cell composed of a predetermined number of logic elements in combination with a logic, ora, and nat logic to satisfy a trigger condition for which a search is desired; Based on the AND / OA / NAT signal, output signals of a plurality of basic cells are selectively combined with AND, OR, and NAT Logic to form a common cell composed of a predetermined number of logic elements to satisfy a trigger condition desired for searching. An end-or-knit combination trigger circuit in a bus information processor, characterized in that configured. The method of claim 1, wherein a desired trigger condition is implemented for each group of buses by the plurality of basic cells and one common cell, and the signals of some groups are combined by one AND logic according to a trigger condition among the output signals for each group. And, in the bus information processor, an end-or-natt combination trigger circuit configured to form a hierarchical structure by combining the end logic signal and the remaining group output signals that are not AND-combined again by end logic. The bus according to claim 1, wherein a plurality of basic cells are configured in response to modification and addition of a trigger item in units of basic cells, and one common cell is configured by connecting outputs of the basic cells to multiple inputs. End-or-Nat Combination Trigger Circuit in the Information Processor.