CN114996178A - Bus arbitration method, system, equipment and storage medium - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/1668—Details of memory controller
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention provides a method, a system, equipment and a storage medium for bus arbitration, wherein the method comprises the following steps: preprocessing a plurality of request signals of an input port, and preselecting a corresponding arbitration mode; responding to the fact that the pre-selected arbitration mode is polling arbitration, and adopting a corresponding arbitration mode according to the fact that the request signal is triggered by a single port or triggered by multiple ports simultaneously; responding to the arbitration mode which is pre-selected as fixed priority arbitration, and carrying out arbitration according to the mode of the least significant bit and the most significant bit; and piecing up the arbitrated results to obtain a final result, and outputting the final result through a cache register. The computational logic of the invention is realized by adopting combinational logic, thereby reducing power consumption and complexity, improving operation efficiency and having high multiplexing rate of double arbitration modules.
Description
Technical Field
The present invention relates to the field of chip design, and more particularly, to a method, system, device and storage medium for bus arbitration.
Background
Because the FPGA has the advantages of high speed, high efficiency, flexibility, stability, high integration level and the like, the FPGA is very necessary in hardware logic verification and design. And the arbiter (arbiter) responds to the corresponding source according to the corresponding priority when the FPGA is mainly used for a plurality of source sources to send requests simultaneously. Commonly used arbiters are classified into Round-Robin arbiters (Round-Robin) and Fixed-Priority arbiters (Fixed-Priority). The combinational logic of the conventional arbiter can only handle one arbitration scheme, and most arbitration schemes require multiple flip-flops for round-robin arbitration, resulting in multiple clocks for calculating and retaining the result.
The prior art has the following defects: 1. the arbitration mode is single; 2. the Round-Robin arbitration is adopted, and the arbitration time is too long when large data volume transmission is handled; 3. the polling arbitration rejects the rest requests when arbitrating the result every time, generates an AXI bus request next time, and clears the last record, so that repeated requests are frequently sent if the device does not obtain the bus use right.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a system, a computer device and a computer readable storage medium for bus arbitration, in which verilog is used to implement an arbitration function, and polling arbitration is implemented in parallel, and only requests are triggered to enter polling arbitration at the same time; the computational logic is realized by adopting combinational logic, so that the power consumption and the complexity are reduced, the operation efficiency is improved, and the multiplexing rate of the double arbitration modules is high; two arbitration modes and support the LSB/MSB switching, thereby providing great convenience for meeting various arbitration mode requirements.
In view of the above, an aspect of the embodiments of the present invention provides a method for bus arbitration, including the following steps: preprocessing a plurality of request signals of an input port, and preselecting a corresponding arbitration mode; responding to the pre-selected arbitration mode as polling arbitration, and adopting a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously; responding to the arbitration mode which is pre-selected as fixed priority arbitration, and carrying out arbitration according to the mode of the least significant bit and the most significant bit; and piecing up the arbitrated results to obtain a final result, and outputting the final result through a cache register.
In some embodiments, said employing a corresponding arbitration mode depending on whether said request signal is single-port triggered or multi-port simultaneous triggered comprises: in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and employing polling arbitration on the request signals in response to the request signals being multi-ported concurrent triggered.
In some embodiments, said employing round-robin arbitration on said request signals comprises: and the request signal and a mask signal to complete the screening of the input signal.
In some embodiments, said employing fixed priority arbitration on said request signal comprises: the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
In another aspect of the embodiments of the present invention, a system for bus arbitration is provided, including: the device comprises a preprocessing module, a signal processing module and a signal processing module, wherein the preprocessing module is configured to preprocess a plurality of request signals of an input port and preselect a corresponding arbitration mode; the polling module is configured to respond to a preselected arbitration mode as polling arbitration and adopt a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously; the priority module is configured for responding to the arbitration mode which is pre-selected as fixed priority arbitration and carrying out arbitration according to the mode of least significant bit and most significant bit; and the output module is configured to splice the arbitrated results to obtain a final result, and output the final result through the cache register.
In some embodiments, the polling module is configured to: in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and employing polling arbitration for the request signals in response to the request signals being multi-port simultaneous triggers.
In some embodiments, the polling module is configured to: and the request signal and a mask signal to complete the screening of the input signal.
In some embodiments, the polling module is configured to: the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: verilog is adopted to realize arbitration function, parallel design is adopted for polling arbitration, and only requests are triggered to enter polling arbitration at the same time; the computational logic is realized by adopting combinational logic, so that the power consumption and the complexity are reduced, the operation efficiency is improved, and the multiplexing rate of the double arbitration modules is high; two arbitration modes and support LSB/MSB switching, thereby providing great convenience for meeting various arbitration mode requirements.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a diagram illustrating an embodiment of a method for bus arbitration according to the present invention;
FIG. 2 is a schematic diagram of an implementation of an embodiment of the present invention;
FIG. 3 is a block diagram of the LSB/MSB priority module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a system for bus arbitration according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a hardware structure of an embodiment of a bus-arbitrated computer apparatus according to the present invention;
FIG. 6 is a schematic diagram of an embodiment of a bus-arbitrated computer storage medium according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of embodiments of the present invention, an embodiment of a method for bus arbitration is provided. Fig. 1 is a schematic diagram illustrating an embodiment of a method for bus arbitration provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, preprocessing a plurality of request signals of the input port and preselecting corresponding arbitration modes;
s2, responding to the pre-selected arbitration mode as polling arbitration, and adopting a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously;
s3, responding the arbitration mode selected in advance as fixed priority arbitration, and arbitrating according to the mode of least significant bit and most significant bit; and
and S4, splicing the arbitrated results to obtain a final result, and outputting the final result through a cache register.
Fig. 2 is a schematic diagram of an implementation of the embodiment of the present invention, and the embodiment of the present invention is described with reference to fig. 2.
A req preprocessing module: preprocessing N req (request signals) input into ports, dividing working conditions into two conditions of single port triggering and multi-port simultaneous triggering, and distributing the req to a corresponding priority processing module;
a fixed priority module: acquiring req triggered by a single port, and directly selecting the port as a priority acquisition module; when the Round-Robin mode is forbidden, the arbitration result, the arbitration effective level and the arbitration result table are output through the circuit structure of FIG. 3 according to the mode that MSB (Most Significant Bit) or LSB (Least Significant Bit) fixes the priority;
Round-Robin priority module: the modular circuit result is the same as the LSB/MSB priority module, and the difference is that the input signal req of the modular circuit needs to be operated with a mask (mask signal) to complete the screening of the input signal of the modular circuit;
a priority granting module: splicing the results obtained by the priority module by pins, and sending the final result to a cache register module;
a cache register module: and the output result is output through the first-level trigger buffer.
A plurality of request signals of the input port are preprocessed, and a corresponding arbitration mode is preselected. Port inputs are received and a fixed priority arbitration or a round-robin arbitration is selected based on the inputs.
And responding to the preselected arbitration mode as polling arbitration, and adopting the corresponding arbitration mode according to the condition that the request signal is triggered by a single port or simultaneously triggered by multiple ports.
In some embodiments, said employing a corresponding arbitration mode depending on whether said request signal is single-port triggered or multi-port simultaneous triggered comprises: in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and employing polling arbitration for the request signals in response to the request signals being multi-port simultaneous triggers. Judging multi-PORTS input request arbitration, if the requests are triggered at the same time, arbitrating LSB or MSB selection, executing Round-Robin priority arbitration, and outputting the result to a priority granting module; if the arbitration is single port arbitration, fixed priority arbitration is executed, and the result is output to a priority granting module.
In some embodiments, said employing round-robin arbitration on said request signal comprises: and the request signal and a mask signal to complete the screening of the input signal.
In some embodiments, said employing fixed priority arbitration on said request signal comprises: the triggered port is selected to get priority and the polling arbitration mode is disabled.
In response to the preselected arbitration mode being a fixed priority arbitration, arbitration is performed in terms of least significant bits and most significant bits. If the fixed priority arbitration is selected, the LSB or MSB selection is arbitrated, the fixed priority arbitration is executed, and the result is output to the priority granting module.
And splicing the arbitrated results to obtain a final result, and outputting the final result through a cache register.
The design of the invention adopts verilog to realize the arbitration function, and when Round-Robin arbitrates, parallel design is adopted, and only requests are triggered to enter Round-Robin arbitration at the same time; the computational logic is realized by adopting combinational logic, so that the power consumption and the complexity are reduced, the operation efficiency is improved, and the multiplexing rate of the double arbitration modules is high; two arbitration modes and support the LSB/MSB switching, thereby providing great convenience for meeting various arbitration mode requirements.
It should be particularly noted that the steps in the embodiments of the method for bus arbitration described above can be mutually intersected, replaced, added, or deleted, and therefore, the method for bus arbitration converted by these reasonable permutation and combination shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.
In view of the above objects, a second aspect of the embodiments of the present invention provides a system for bus arbitration. As shown in fig. 4, the system 200 includes the following modules: the device comprises a preprocessing module, a signal processing module and a signal processing module, wherein the preprocessing module is configured to preprocess a plurality of request signals of an input port and preselect a corresponding arbitration mode; the polling module is configured to respond to a preselected arbitration mode as polling arbitration and adopt a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously; the priority module is configured for responding to the arbitration mode which is pre-selected as fixed priority arbitration and carrying out arbitration according to the mode of least significant bit and most significant bit; and the output module is configured to splice the arbitrated results to obtain a final result, and output the final result through the cache register.
In some embodiments, the polling module is configured to: in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and employing polling arbitration for the request signals in response to the request signals being multi-port simultaneous triggers.
In some embodiments, the polling module is configured to: and the request signal and a mask signal to complete the screening of the input signal.
In some embodiments, the polling module is configured to: the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, preprocessing a plurality of request signals of the input port and preselecting corresponding arbitration modes; s2, responding to the pre-selected arbitration mode as polling arbitration, and adopting a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously; s3, responding the arbitration mode selected in advance as fixed priority arbitration, and arbitrating according to the mode of least significant bit and most significant bit; and S4, splicing the arbitrated results to obtain a final result, and outputting the final result through a cache register.
In some embodiments, said employing a corresponding arbitration mode depending on whether said request signal is single-port triggered or multi-port simultaneous triggered comprises: in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and employing polling arbitration on the request signals in response to the request signals being multi-ported concurrent triggered.
In some embodiments, said employing round-robin arbitration on said request signals comprises: and the request signal and a mask signal to complete the screening of the input signal.
In some embodiments, said employing fixed priority arbitration on said request signal comprises: the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
Fig. 5 is a schematic hardware structure diagram of an embodiment of the bus-arbitrated computer device according to the present invention.
Taking the apparatus shown in fig. 5 as an example, the apparatus includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection in fig. 3.
The memory 302 is a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the bus arbitration method in the embodiment of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., a method of implementing bus arbitration, by executing nonvolatile software programs, instructions, and modules stored in the memory 302.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of bus arbitration, or the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Any embodiment of a computer device implementing the method of bus arbitration described above may achieve the same or similar effects as any of the preceding method embodiments corresponding thereto.
The present invention also provides a computer readable storage medium storing a computer program for performing a method of bus arbitration when executed by a processor.
Fig. 6 is a schematic diagram of an embodiment of a computer storage medium for bus arbitration provided by the present invention. Taking the computer storage medium as shown in fig. 6 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware to implement the methods of the bus arbitration. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), or a Random Access Memory (RAM). The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of bus arbitration comprising the steps of:
preprocessing a plurality of request signals of an input port and preselecting a corresponding arbitration mode;
responding to the pre-selected arbitration mode as polling arbitration, and adopting a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously;
responding to the arbitration mode which is pre-selected as fixed priority arbitration, and carrying out arbitration according to the mode of the least significant bit and the most significant bit; and
and splicing the arbitrated results to obtain a final result, and outputting the final result through a cache register.
2. The method of claim 1, wherein employing the corresponding arbitration mode according to whether the request signal is single-port triggered or multi-port simultaneous triggered comprises:
in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and
polling arbitration is employed on the request signals in response to the request signals being multi-port simultaneous triggers.
3. The method of claim 2, wherein employing round-robin arbitration for the request signals comprises:
and the request signal and a mask signal to complete the screening of the input signal.
4. The method of claim 2, wherein said employing fixed priority arbitration for said request signals comprises:
the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
5. A system for bus arbitration, comprising:
the device comprises a preprocessing module, a signal processing module and a signal processing module, wherein the preprocessing module is configured to preprocess a plurality of request signals of an input port and preselect a corresponding arbitration mode;
the polling module is configured to respond to a preselected arbitration mode as polling arbitration and adopt a corresponding arbitration mode according to whether the request signal is triggered by a single port or triggered by multiple ports simultaneously;
the priority module is configured for responding to the arbitration mode which is pre-selected as fixed priority arbitration and carrying out arbitration according to the mode of least significant bit and most significant bit; and
and the output module is configured to splice the arbitrated results to obtain a final result, and output the final result through the cache register.
6. The system of claim 5, wherein the polling module is configured to:
in response to the request signal being a single port trigger, employing fixed priority arbitration for the request signal; and
polling arbitration is employed on the request signals in response to the request signals being multi-port simultaneous triggers.
7. The system of claim 6, wherein the polling module is configured to:
and the request signal and a mask signal to complete the screening of the input signal.
8. The system of claim 6, wherein the polling module is configured to:
the triggered port is selected to acquire priority and the polling arbitration mode is disabled.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115454912A (en) * | 2022-11-09 | 2022-12-09 | 苏州浪潮智能科技有限公司 | Parallel arbitration method, system, equipment and storage medium |
| CN117435252A (en) * | 2023-12-19 | 2024-01-23 | 苏州元脑智能科技有限公司 | Hardware implementation device, system and application method of mutual exclusion lock |
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| CN114567607A (en) * | 2022-02-25 | 2022-05-31 | 山东云海国创云计算装备产业创新中心有限公司 | Multi-port arbitration method, device, equipment and computer readable storage medium |
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