KR0117570Y1 - Image data processing apparatus - Google Patents

Abstract

The present invention relates to an image data processing apparatus.

The present invention maintains an image by using dummy data when an error occurs when the image is restored by demultiplexing the image data, so that a phenomenon in which the image is broken due to an error occurrence can be prevented and a good quality image can be provided. Can be.

Description

Image data processing device

1 is a block diagram of a conventional image data processing apparatus.

2 is a schematic diagram of image data in accordance with Recommendation H.261 of the ITU-T.

3 is a block diagram of an image data processing apparatus according to the present invention.

4 is a block diagram showing a dummy data generation logic.

5 is an operation timing diagram of an image data processing apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

50: demultiplexer 60: switch unit

70: buffer portion 80: multiplexer portion

90: buffer unit 100: inverse quantization unit

110: interframe processor

The present invention relates to an image data processing apparatus for processing image data according to ITU-T Recommendation H.261. In particular, the present invention relates to preventing image breakdown due to an error when reconstructing an image by demultiplexing the image data. An image data processing apparatus.

The digital picture data encoded by the multiplex encoder according to Recommendation H.261 of the ITU-T is a picture layer, a group of block layer (GOB) layer, a macro block layer (MB) layer, and the like, as shown in FIG. It consists of a block hierarchy. The picture layer includes picture start information (PSC), picture time base reference information (TR), picture type information (PTYPE), picture other embedding information (PEI), picture spare code (PSPARE), and GOB layer. Start information (GBSC), group number information (GN), group quantization information (GQUANT), group other insertion information (GEI), group reserve code (GSPARE) and MB layer. In addition, the MB layer includes MB address (MBA), MB type information (MTYPE), macro quantization information (MQUANT), motion vector data (MVD), coding block pattern information (CBP), MBA stuffing information (MBAS) and block layer. The block layer includes a transform coefficient TCOEFF and block end indication information EOB. The picture layer consists of 12 GOB layers, the GOB layer consists of 33 MB layers, and the MB layer consists of 6 block layers. In addition, in FIG. 2, the square is the information of fixed length, and the ellipse is the information of variable length.

A conventional image data processing apparatus for processing encoded digital image data according to Recommendation H.261 of the ITU-T, as shown in FIG. 1, has a demultiplexer 10, a buffer unit 20, and inverse quantization. The unit 30 and the interframe processor 40 are provided. When the multiplexed data is input, the demultiplexer 10 demultiplexes and decodes the corresponding data into separate data and outputs the control data. The buffer unit 20 includes a plurality of buffers 21 to 24, and under the control of the demultiplexer 10, the dequantization unit 30 and the interframe processor 40 may control data applied from the demultiplexer 10. Output to the The buffer 21 stores run information applied from the demultiplexer 10 and outputs the run information to the dequantizer 30, and the buffer 22 is applied from the demultiplexer 10. The information is stored and output to the dequantizer 30, and the buffer 23 transmits the quantization step size information applied from the demultiplexer 10 to the dequantizer 30 and the interframe processor 40. At the same time, the flag information is output to the interframe processor 40, and the buffer 24 stores motion vector information applied from the demultiplexer 10 and outputs the motion vector information to the interframe processor 40. The inverse quantization unit 30 inversely quantizes the run information, the level information, and the quantization step size information applied from the buffer unit 20 according to a control signal from the demultiplexing unit 10 to the inverse discrete cosine transform (IDCT) processor. Output to. The interframe processor 40 processes the inverse quantization step size information, the frag information, and the motion vector information applied from the buffer unit 20 according to the control signal from the demultiplexing unit 10 to reconstruct the image data, thereby reconstructing the frame memory. Output to the controller side.

The image data multiplexed in the form of FIG. 2 includes codes having a fixed length only in the picture layer and the GOB layer, and codes having a variable length in the remaining layers by Huffman coding. The demultiplexer 10 separates the multiplexed image data by layers. The demultiplexer 10 has only an error detection function. When an error occurs while processing data in a GOB layer unit, the demultiplexer 10 inputs the next GOB layer. Since the multiplexed data is discarded, the screen is broken due to the lost multiplexed data.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an image data processing apparatus that prevents an image from being broken due to an error when restoring an image by demultiplexing the image data. have.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of an image data processing apparatus according to the present invention, FIG. 4 is a block diagram showing a dummy data generation logic, and FIG. 5 is an operation timing diagram of the image data processing apparatus according to the present invention.

As shown in FIG. 3, the image data processing apparatus according to the present invention includes a demultiplexer 50, a switch 60, a buffer 70, a multiplexer 80, a buffer 90, and inverse quantization. The unit 100 includes an interframe processor 110 and a controller 120. When the multiplexed data is input, the demultiplexer 50 demultiplexes and decodes the corresponding data to separate and output real data and a control signal. The switch unit 60 includes a plurality of switches SW1 to SW4, and selectively outputs data applied from the demultiplexer 50 under the control of the controller 120. The buffer unit 70 includes a plurality of buffers 71 to 78, and stores data applied from the switch unit 60 according to a control signal from the demultiplexer 50, and stores the data applied to the control unit ( Output to the multiplexer unit 80 according to the control of 120. The multiplexer unit 80 includes a plurality of multiplexers 81 to 84 and selectively selects data applied from the buffer unit 70 and dummy data applied from the control unit 120 under the control of the control unit 120. To the buffer unit 90. The buffer unit 90 includes a plurality of buffers 91 to 94, and the inverse quantization unit 100 and the interframe processor 110 control the data applied from the multiplexer unit 80 under the control of the control unit 120. Output to the The inverse quantization unit 100 inversely quantizes the data applied from the buffer unit 90 under the control of the control unit 120 and outputs the data to the IDCT processor. The interframe processor 110 processes the data applied from the buffer unit 90 under the control of the controller 120 to reconstruct the image data and output the image data to the frame memory controller.

The switch SW1 of the switch unit 60 selectively outputs run information applied from the demultiplexer 50 to the buffer 71 and the buffer 72 under the control of the controller 120, and switches SW2. ) Selectively outputs the level information applied from the demultiplexer 50 to the buffer 73 and the buffer 74 under the control of the controller 120, and the switch SW3 is output from the demultiplexer 50. The quantization step size information and the flag information to be applied are selectively output to the buffer 75 and the buffer 76 under the control of the controller 120, and the switch SW4 is a motion vector applied from the demultiplexer 50. The information is selectively output to the buffer 77 and the buffer 78 under the control of the controller 120.

The buffers 71 and 72 of the buffer unit 70 store the run information applied from the switch SW1 under the control of the demultiplexer 50, and store the stored run information under the control of the controller 120. On the 81) side. The buffers 73 and 74 store the level information applied from the switch SW2 under the control of the demultiplexer 50, store the stored level information under the control of the demultiplexer 50, and store the stored level information. Is output to the multiplexer 82 side according to the control of the control unit 120. The buffers 75 and 76 store the quantization step size information and the flag information applied from the switch SW3 under the control of the demultiplexer 50, and store the stored step size information and the flag information to the control of the controller 120. Therefore, the output to the multiplexer 83 side. The buffers 77 and 78 store the motion vector information applied from the switch SW4 under the control of the demultiplexer 50, and store the stored motion vector information on the multiplexer 84 side under the control of the controller 120. Output

The multiplexer 81 of the multiplexer unit 80 selects one of the run information from the buffers 71 and 72 and the dummy run information from the control unit under the control of the control unit 120 and outputs it to the buffer 91 side. The multiplexer 82 selects one of the level information from the buffers 73 and 74 and the dummy level information from the controller 120 under the control of the controller 120 and outputs the same to the buffer 92. The multiplexer 83 selects one of the quantization step size information and the flag information from the buffers 75 and 76 and the dummy quantization step size information and the dummy flag information from the control unit 120 under the control of the control unit 120 to perform a buffer. The multiplexer 84 selects one of the motion vector information from the buffers 77 and 78 and the dummy motion vector information from the control unit 120 according to the control of the control unit 120. Output to 94).

The buffer 91 of the buffer unit 90 outputs run information applied from the multiplexer 81 to the inverse quantization unit 100 under the control of the control unit 120, and the buffer 92 from the multiplexer 82. The applied level information is output to the inverse quantization unit 100 under the control of the controller 120. The buffer 93 receives the quantization step size information and the flag information applied from the multiplexer 83, and outputs the quantization step size information to the inverse quantization unit 100 under the control of the control unit 120, and the flag information is interframed. Output to the processor 110 side. The buffer 94 outputs motion vector information applied from the multiplexer 84 to the interframe processor 110 under the control of the controller 120.

The controller 120 is provided with a dummy data generation logic 125 as shown in FIG. The dummy data generation logic 125 generates dummy run information, dummy level information, dummy motion vector information, dummy quantization step size information, and dummy flag information according to an applied clock and an error signal applied from the demultiplexer 50. The output signal is output to the multiplexer section 80 via the data bus DB, and the control signal is output to the buffer section 90 via the output terminal R / W. The dummy data generation logic 125 may be configured using a programmable gate array (PGA).

The image data processing device of the present invention operates as follows.

When the multiplexed data is input to the demultiplexer 50, the demultiplexer 50 demultiplexes the multiplexed data into a header and data. When the GOB header is found, the decoded data is output to the switch unit 60. do. At this time, each switch SW1 to SW4 of the switch unit 60 selectively decodes the decoded data received from the demultiplexer 50 to one of the buffers 71 to 78 connected thereto under the control of the controller 120. Will print In addition, the buffers 71 to 78 receive and store data from the switch unit 60 under the control of the demultiplexer 50 and output the data to the multiplexer unit 80 under the control of the controller 120. The multiplexers 81 to 84 output data applied from the buffers 71 to 78 connected to the buffer unit 90 to the buffer unit 90 under the control of the controller 120, and the buffers 91 to 94 are connected to the multiplexers 81 to 84. The data applied from the multiplexers 81 to 84 is output to the dequantization unit 100 and the interframe processor 110 under the control of the controller 120.

If no error occurs while the demultiplexer 50 demultiplexes the data, as described above, the data from the demultiplexer 50 is transferred to the switch unit 60, the buffer unit 70, and the multiplexer unit ( 80) and the buffer unit 90, the dequantization unit 100 and the interframe processor 110 are transferred.

In this state, if an error occurs while the demultiplexer 50 demultiplexes the data, the dummy data generation logic 125 of the control unit 120 returns to FIG. 5 according to an error signal from the demultiplexer 50. The dummy data as shown are generated and output to the multiplexer section 80 via the bus DB, and at the same time, a write control signal as shown in FIG. 5 is output to the buffer section 90 side. In this case, the multiplexer 81 outputs dummy run information, the multiplexer 82 outputs dummy level information, the multiplexer 83 outputs dummy quantization step size information and dummy flag information, and the multiplexer 84 outputs a dummy. Outputs motion vector information. Accordingly, the buffers 91 to 94 apply the corresponding information from the multiplexers 81 to 84 connected thereto to the inverse quantization unit 100 and the interframe processor 110 side of the control unit 120. In this case, the dequantization unit 100 and the interframe processor 110 output the result data processed using the dummy data to the IDCT processor and the frame memory controller to prevent the image from being broken.

As described above, the present invention maintains the image by using dummy data when an error occurs when restoring the image by demultiplexing the image data, thereby preventing the image from being broken due to an error. It is possible to provide an image of.

Claims (6)

A demultiplexer for demultiplexing the multiplexed data and outputting data including run information, level information, quantization step size information, flag information, and motion vector information; An inverse quantization unit which inversely quantizes run information, level information, and quantization step size information and outputs them to an IDCT processor; An image data processing apparatus comprising an interframe processor for processing preg information and motion vector information and outputting the same to a frame memory controller; According to the error signal applied from the demultiplexer, dummy data including dummy run information, dummy level information, dummy quantization step size information, dummy flag information, and dummy motion vector information is generated, and according to the operation state of the demultiplexer. A control unit which performs a control operation; A switch unit for selectively thrusting data applied from the demultiplexer under the control of the controller; A first buffer unit for storing data applied from the switch unit under the control of the demultiplexer and outputting the data under the control of the controller; A multiplexer unit which selects and outputs data applied from the first buffer unit and dummy data applied from the controller under the control of the controller; And a second buffer unit configured to output data applied from the multiplexer unit to the dequantizer and the interframe processor under control of the controller. The method of claim 1, And the control unit includes a dummy data generation logic that generates the dummy data according to an applied clock and an error signal applied from the demultiplexer. The method of claim 1, The switch unit may include: a first switch selectively outputting run information applied from demultiplexing to one of two output terminals under control of the controller; A second switch selectively outputting level information applied from the demultiplexer to one of two output terminals under control of the controller; A third switch selectively outputting quantization step size information and flag information applied from the demultiplexer to one of two output terminals under control of the controller; And a fourth switch for selectively outputting motion vector information applied from the demultiplexer to one of two output terminals under control of the controller. The method of claim 1, First and second buffers configured to store run information applied from a switch unit according to the control of the demultiplexer and output the run information applied by a switch unit; Third and fourth buffers for storing the level information applied from the switch unit under the control of the demultiplexer and outputting the level information under the control of the controller; Fifth and sixth buffers for storing quantization step size information and flag information applied from the switch unit and outputting the quantization step size information and flag information according to the control of the demultiplexer and outputting the control unit according to the control of the controller; And a seventh and eighth buffers configured to store motion vector information applied from the switch unit under the control of the demultiplexer and output the same under the control of the controller. The method of claim 1, The multiplexer may include: a first multiplexer configured to selectively output run information applied to two input terminals from a first buffer unit and dummy run information applied from the controller according to the control of the controller; A second multiplexer for selectively outputting level information applied from the first buffer unit to two input terminals and dummy level information applied from the controller according to the control of the controller; A third multiplexer for selectively outputting quantization step size information and flag information applied from the first buffer unit to two input terminals, and dummy quantization step size information and dummy flag information applied from the controller according to the control of the controller; And a fourth multiplexer for selectively outputting motion vector information applied from the first buffer unit to two input terminals and dummy motion vector information applied from the controller under the control of the controller. The method of claim 1, The second buffer unit may include: a first buffer configured to output run information applied from a multiplexer unit to the inverse quantization unit under control of the controller; A second buffer for outputting level information applied from the multiplexer to the inverse quantization unit under control of the controller; A third step of receiving the quantization step size bounce and flag information applied from the multiplexer unit and outputting quantization step size information to the dequantizer side under control of the controller and simultaneously outputting the flag information to the interframe processor side; buffer ; And a fourth buffer configured to output motion vector information applied from the multiplexer to the interframe processor under the control of the controller.