JPWO2025013417A1 - - Google Patents
Info
- Publication number
- JPWO2025013417A1 JPWO2025013417A1 JP2025532406A JP2025532406A JPWO2025013417A1 JP WO2025013417 A1 JPWO2025013417 A1 JP WO2025013417A1 JP 2025532406 A JP2025532406 A JP 2025532406A JP 2025532406 A JP2025532406 A JP 2025532406A JP WO2025013417 A1 JPWO2025013417 A1 JP WO2025013417A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023113964 | 2023-07-11 | ||
| PCT/JP2024/018380 WO2025013417A1 (ja) | 2023-07-11 | 2024-05-17 | アナログデジタル変換器、集積回路、および、アナログデジタル変換器の制御方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2025013417A1 true JPWO2025013417A1 (https=) | 2025-01-16 |
Family
ID=94215340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025532406A Pending JPWO2025013417A1 (https=) | 2023-07-11 | 2024-05-17 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2025013417A1 (https=) |
| WO (1) | WO2025013417A1 (https=) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359579B1 (en) * | 2000-02-17 | 2002-03-19 | Advanced Micro Devices, Inc. | Digital logic correction circuit for a pipeline analog to digital (A/D) converter |
| JP2015097332A (ja) * | 2013-11-15 | 2015-05-21 | 旭化成エレクトロニクス株式会社 | サンプルホールド回路のキャリブレーション方法、キャリブレーション装置、およびサンプルホールド回路 |
| JP2016213531A (ja) * | 2015-04-28 | 2016-12-15 | 国立大学法人金沢大学 | Ａｄ変換器およびａｄ変換方法 |
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2024
- 2024-05-17 WO PCT/JP2024/018380 patent/WO2025013417A1/ja active Pending
- 2024-05-17 JP JP2025532406A patent/JPWO2025013417A1/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2025013417A1 (ja) | 2025-01-16 |