JPWO2023100964A1 - - Google Patents

Info

Publication number
JPWO2023100964A1
JPWO2023100964A1 JP2023565074A JP2023565074A JPWO2023100964A1 JP WO2023100964 A1 JPWO2023100964 A1 JP WO2023100964A1 JP 2023565074 A JP2023565074 A JP 2023565074A JP 2023565074 A JP2023565074 A JP 2023565074A JP WO2023100964 A1 JPWO2023100964 A1 JP WO2023100964A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023565074A
Other languages
Japanese (ja)
Other versions
JPWO2023100964A5 (https=
JP7693830B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023100964A1 publication Critical patent/JPWO2023100964A1/ja
Publication of JPWO2023100964A5 publication Critical patent/JPWO2023100964A5/ja
Application granted granted Critical
Publication of JP7693830B2 publication Critical patent/JP7693830B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
JP2023565074A 2021-12-03 2022-12-01 配線基板及び電子装置 Active JP7693830B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021196776 2021-12-03
JP2021196776 2021-12-03
PCT/JP2022/044308 WO2023100964A1 (ja) 2021-12-03 2022-12-01 配線基板及び電子装置

Publications (3)

Publication Number Publication Date
JPWO2023100964A1 true JPWO2023100964A1 (https=) 2023-06-08
JPWO2023100964A5 JPWO2023100964A5 (https=) 2024-08-16
JP7693830B2 JP7693830B2 (ja) 2025-06-17

Family

ID=86612307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023565074A Active JP7693830B2 (ja) 2021-12-03 2022-12-01 配線基板及び電子装置

Country Status (5)

Country Link
US (1) US20260122768A1 (https=)
EP (1) EP4444046A1 (https=)
JP (1) JP7693830B2 (https=)
CN (1) CN118339929A (https=)
WO (1) WO2023100964A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056163A (ja) * 1996-08-07 1998-02-24 Fujitsu Ltd 集積回路パッケージ
JP2002057513A (ja) * 2000-08-11 2002-02-22 Denso Corp ミリ波モジュール
WO2017170389A1 (ja) * 2016-03-30 2017-10-05 京セラ株式会社 高周波基板、高周波パッケージおよび高周波モジュール
WO2018074100A1 (ja) * 2016-10-21 2018-04-26 京セラ株式会社 高周波基体、高周波パッケージおよび高周波モジュール
WO2020040072A1 (ja) * 2018-08-21 2020-02-27 Ｎｇｋエレクトロデバイス株式会社 配線基板、パッケージおよびモジュール

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056163A (ja) * 1996-08-07 1998-02-24 Fujitsu Ltd 集積回路パッケージ
JP2002057513A (ja) * 2000-08-11 2002-02-22 Denso Corp ミリ波モジュール
WO2017170389A1 (ja) * 2016-03-30 2017-10-05 京セラ株式会社 高周波基板、高周波パッケージおよび高周波モジュール
WO2018074100A1 (ja) * 2016-10-21 2018-04-26 京セラ株式会社 高周波基体、高周波パッケージおよび高周波モジュール
WO2020040072A1 (ja) * 2018-08-21 2020-02-27 Ｎｇｋエレクトロデバイス株式会社 配線基板、パッケージおよびモジュール

Also Published As

Publication number Publication date
CN118339929A (zh) 2024-07-12
EP4444046A1 (en) 2024-10-09
WO2023100964A1 (ja) 2023-06-08
US20260122768A1 (en) 2026-04-30
JP7693830B2 (ja) 2025-06-17

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