JPWO2022264414A5 - - Google Patents
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- JPWO2022264414A5 JPWO2022264414A5 JP2023528924A JP2023528924A JPWO2022264414A5 JP WO2022264414 A5 JPWO2022264414 A5 JP WO2022264414A5 JP 2023528924 A JP2023528924 A JP 2023528924A JP 2023528924 A JP2023528924 A JP 2023528924A JP WO2022264414 A5 JPWO2022264414 A5 JP WO2022264414A5
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- JP
- Japan
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- optimization problem
- combinatorial optimization
- constraints
- cnf
- variables
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000005457 optimization Methods 0.000 claims 3
- 238000000034 method Methods 0.000 claims 1
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/023239 WO2022264414A1 (ja) | 2021-06-18 | 2021-06-18 | シミュレーテッドアニーリング装置およびシミュレーテッドアニーリング方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2022264414A1 JPWO2022264414A1 (https=) | 2022-12-22 |
| JPWO2022264414A5 true JPWO2022264414A5 (https=) | 2024-02-08 |
| JP7582471B2 JP7582471B2 (ja) | 2024-11-13 |
Family
ID=84525980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023528924A Active JP7582471B2 (ja) | 2021-06-18 | 2021-06-18 | シミュレーテッドアニーリング装置およびシミュレーテッドアニーリング方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20240289640A1 (https=) |
| JP (1) | JP7582471B2 (https=) |
| WO (1) | WO2022264414A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025136252A (ja) * | 2024-03-07 | 2025-09-19 | 東芝情報システム株式会社 | 検証システム及び検証方法 |
| EP4718303A1 (en) * | 2024-09-26 | 2026-04-01 | Multiverse Computing S.L. | An encryption system and method for quantum annealers |
| CN119861769B (zh) * | 2025-03-24 | 2025-07-04 | 武汉克莱美特环境设备有限公司 | 一种试验箱温度智能调控方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7386818B2 (en) * | 2004-01-22 | 2008-06-10 | Nec Laboratories America, Inc. | Efficient modeling of embedded memories in bounded memory checking |
| JP2015172873A (ja) * | 2014-03-12 | 2015-10-01 | 富士通株式会社 | 検証プログラム、検証方法および検証装置 |
| JP7297540B2 (ja) * | 2019-06-06 | 2023-06-26 | 株式会社東芝 | 情報処理装置、puboソルバ、情報処理方法およびプログラム |
-
2021
- 2021-06-18 US US18/569,705 patent/US20240289640A1/en active Pending
- 2021-06-18 JP JP2023528924A patent/JP7582471B2/ja active Active
- 2021-06-18 WO PCT/JP2021/023239 patent/WO2022264414A1/ja not_active Ceased
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