JP7582471B2 - シミュレーテッドアニーリング装置およびシミュレーテッドアニーリング方法 - Google Patents

シミュレーテッドアニーリング装置およびシミュレーテッドアニーリング方法 Download PDF

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JP7582471B2
JP7582471B2 JP2023528924A JP2023528924A JP7582471B2 JP 7582471 B2 JP7582471 B2 JP 7582471B2 JP 2023528924 A JP2023528924 A JP 2023528924A JP 2023528924 A JP2023528924 A JP 2023528924A JP 7582471 B2 JP7582471 B2 JP 7582471B2
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combinatorial optimization
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simulated annealing
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JPWO2022264414A5 (https=
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拓也 荒木
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NEC Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/80—Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing

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JP2023528924A 2021-06-18 2021-06-18 シミュレーテッドアニーリング装置およびシミュレーテッドアニーリング方法 Active JP7582471B2 (ja)

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JP7582471B2 true JP7582471B2 (ja) 2024-11-13

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JP2025136252A (ja) * 2024-03-07 2025-09-19 東芝情報システム株式会社 検証システム及び検証方法
EP4718303A1 (en) * 2024-09-26 2026-04-01 Multiverse Computing S.L. An encryption system and method for quantum annealers
CN119861769B (zh) * 2025-03-24 2025-07-04 武汉克莱美特环境设备有限公司 一种试验箱温度智能调控方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2007524165A (ja) 2004-01-22 2007-08-23 エヌイーシー ラボラトリーズ アメリカ インク 有限メモリ検査における埋込みメモリの効率的なモデリング方法
JP2015172873A (ja) 2014-03-12 2015-10-01 富士通株式会社 検証プログラム、検証方法および検証装置
JP2020201598A (ja) 2019-06-06 2020-12-17 株式会社東芝 情報処理装置、ｐｕｂｏソルバ、情報処理方法およびプログラム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007524165A (ja) 2004-01-22 2007-08-23 エヌイーシー ラボラトリーズ アメリカ インク 有限メモリ検査における埋込みメモリの効率的なモデリング方法
JP2015172873A (ja) 2014-03-12 2015-10-01 富士通株式会社 検証プログラム、検証方法および検証装置
JP2020201598A (ja) 2019-06-06 2020-12-17 株式会社東芝 情報処理装置、ｐｕｂｏソルバ、情報処理方法およびプログラム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
土居 翼 外2名，シフトスケジューリング問題に対する分解法の検討，第５８回 システム制御情報学会 研究発表講演会講演論文集，2014年05月23日，予稿集2014-10024-087

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