JPWO2022107270A1 - - Google Patents

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Publication number
JPWO2022107270A1
JPWO2022107270A1 JP2022563327A JP2022563327A JPWO2022107270A1 JP WO2022107270 A1 JPWO2022107270 A1 JP WO2022107270A1 JP 2022563327 A JP2022563327 A JP 2022563327A JP 2022563327 A JP2022563327 A JP 2022563327A JP WO2022107270 A1 JPWO2022107270 A1 JP WO2022107270A1
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JP
Japan
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JP2022563327A
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JP7444285B2 (ja
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
JP2022563327A 2020-11-19 2020-11-19 半導体構造および電界効果トランジスタの作製方法 Active JP7444285B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/043162 WO2022107270A1 (ja) 2020-11-19 2020-11-19 半導体構造および電界効果トランジスタの作製方法

Publications (2)

Publication Number Publication Date
JPWO2022107270A1 true JPWO2022107270A1 (ja) 2022-05-27
JP7444285B2 JP7444285B2 (ja) 2024-03-06

Family

ID=81708612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022563327A Active JP7444285B2 (ja) 2020-11-19 2020-11-19 半導体構造および電界効果トランジスタの作製方法

Country Status (2)

Country Link
JP (1) JP7444285B2 (ja)
WO (1) WO2022107270A1 (ja)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2007266577A (ja) * 2006-03-03 2007-10-11 Matsushita Electric Ind Co Ltd 窒化物半導体装置及びその製造方法
WO2013165620A1 (en) * 2012-05-04 2013-11-07 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
JP2014078653A (ja) 2012-10-12 2014-05-01 Waseda Univ Ｉｉｉ族窒化物半導体層の製造方法
JP2019134101A (ja) 2018-01-31 2019-08-08 京セラ株式会社 半導体素子の製造方法

Also Published As

Publication number Publication date
JP7444285B2 (ja) 2024-03-06
WO2022107270A1 (ja) 2022-05-27

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