JPWO2022004837A1 - - Google Patents
Info
- Publication number
- JPWO2022004837A1 JPWO2022004837A1 JP2022534108A JP2022534108A JPWO2022004837A1 JP WO2022004837 A1 JPWO2022004837 A1 JP WO2022004837A1 JP 2022534108 A JP2022534108 A JP 2022534108A JP 2022534108 A JP2022534108 A JP 2022534108A JP WO2022004837 A1 JPWO2022004837 A1 JP WO2022004837A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020115307 | 2020-07-03 | ||
JP2020115307 | 2020-07-03 | ||
PCT/JP2021/024911 WO2022004837A1 (ja) | 2020-07-03 | 2021-07-01 | 情報処理装置、情報処理方法及び情報処理プログラムの記録媒体 |
Publications (3)
Publication Number | Publication Date |
---|---|
JPWO2022004837A1 true JPWO2022004837A1 (ja) | 2022-01-06 |
JPWO2022004837A5 JPWO2022004837A5 (ja) | 2023-03-10 |
JP7420251B2 JP7420251B2 (ja) | 2024-01-23 |
Family
ID=79316293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022534108A Active JP7420251B2 (ja) | 2020-07-03 | 2021-07-01 | 情報処理装置、情報処理方法及び情報処理プログラム |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP7420251B2 (ja) |
WO (1) | WO2022004837A1 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6437654A (en) * | 1987-08-03 | 1989-02-08 | Nec Corp | Inter-processor communication memory |
JP2010211506A (ja) * | 2009-03-10 | 2010-09-24 | Nec Corp | 不均一メモリアクセス機構を備えるコンピュータ、コントローラ、及びデータ移動方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10268284B2 (en) | 2015-07-29 | 2019-04-23 | Maxell, Ltd. | Image display system |
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2021
- 2021-07-01 JP JP2022534108A patent/JP7420251B2/ja active Active
- 2021-07-01 WO PCT/JP2021/024911 patent/WO2022004837A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6437654A (en) * | 1987-08-03 | 1989-02-08 | Nec Corp | Inter-processor communication memory |
JP2010211506A (ja) * | 2009-03-10 | 2010-09-24 | Nec Corp | 不均一メモリアクセス機構を備えるコンピュータ、コントローラ、及びデータ移動方法 |
Also Published As
Publication number | Publication date |
---|---|
JP7420251B2 (ja) | 2024-01-23 |
WO2022004837A1 (ja) | 2022-01-06 |
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