JPWO2021209858A1 - - Google Patents

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Publication number
JPWO2021209858A1
JPWO2021209858A1 JP2022514870A JP2022514870A JPWO2021209858A1 JP WO2021209858 A1 JPWO2021209858 A1 JP WO2021209858A1 JP 2022514870 A JP2022514870 A JP 2022514870A JP 2022514870 A JP2022514870 A JP 2022514870A JP WO2021209858 A1 JPWO2021209858 A1 JP WO2021209858A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022514870A
Other languages
Japanese (ja)
Other versions
JPWO2021209858A5 (https=
JP7653416B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021209858A1 publication Critical patent/JPWO2021209858A1/ja
Publication of JPWO2021209858A5 publication Critical patent/JPWO2021209858A5/ja
Priority to JP2025042528A priority Critical patent/JP7782085B2/ja
Application granted granted Critical
Publication of JP7653416B2 publication Critical patent/JP7653416B2/ja
Priority to JP2025203644A priority patent/JP2026032141A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Neurology (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
JP2022514870A 2020-04-17 2021-04-06 半導体装置 Active JP7653416B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2025042528A JP7782085B2 (ja) 2020-04-17 2025-03-17 半導体装置
JP2025203644A JP2026032141A (ja) 2020-04-17 2025-11-26 半導体装置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2020073841 2020-04-17
JP2020073841 2020-04-17
JP2020076478 2020-04-23
JP2020076478 2020-04-23
PCT/IB2021/052826 WO2021209858A1 (ja) 2020-04-17 2021-04-06 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025042528A Division JP7782085B2 (ja) 2020-04-17 2025-03-17 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2021209858A1 true JPWO2021209858A1 (https=) 2021-10-21
JPWO2021209858A5 JPWO2021209858A5 (https=) 2024-03-28
JP7653416B2 JP7653416B2 (ja) 2025-03-28

Family

ID=78084353

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2022514870A Active JP7653416B2 (ja) 2020-04-17 2021-04-06 半導体装置
JP2025042528A Active JP7782085B2 (ja) 2020-04-17 2025-03-17 半導体装置
JP2025203644A Pending JP2026032141A (ja) 2020-04-17 2025-11-26 半導体装置

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2025042528A Active JP7782085B2 (ja) 2020-04-17 2025-03-17 半導体装置
JP2025203644A Pending JP2026032141A (ja) 2020-04-17 2025-11-26 半導体装置

Country Status (6)

Country Link
US (2) US12106823B2 (https=)
JP (3) JP7653416B2 (https=)
KR (1) KR20230003476A (https=)
CN (1) CN115443505A (https=)
DE (1) DE112021002394T5 (https=)
WO (1) WO2021209858A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12481867B2 (en) * 2021-04-28 2025-11-25 Arm Limited Memory for artificial neural network accelerator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003283272A (ja) * 2002-01-17 2003-10-03 Semiconductor Energy Lab Co Ltd ソースフォロワ回路
JP2015195074A (ja) * 2014-03-14 2015-11-05 株式会社半導体エネルギー研究所 半導体装置およびその駆動方法、並びに電子機器
JP2016105343A (ja) * 2014-11-21 2016-06-09 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
JP2018156699A (ja) * 2017-03-16 2018-10-04 株式会社半導体エネルギー研究所 半導体装置、電子部品、及び電子機器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262907B1 (en) * 2000-05-18 2001-07-17 Integrated Device Technology, Inc. Ternary CAM array
TWI277290B (en) 2002-01-17 2007-03-21 Semiconductor Energy Lab Electric circuit
JP2004220677A (ja) * 2003-01-14 2004-08-05 Renesas Technology Corp メモリ装置
US20110051484A1 (en) * 2009-08-28 2011-03-03 International Business Machines Corporation Low active power content addressable memory
WO2011089835A1 (en) * 2010-01-20 2011-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US8588000B2 (en) * 2010-05-20 2013-11-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device having a reading transistor with a back-gate electrode
TWI555128B (zh) 2010-08-06 2016-10-21 半導體能源研究所股份有限公司 半導體裝置及半導體裝置的驅動方法
JP6298657B2 (ja) * 2013-03-07 2018-03-20 株式会社半導体エネルギー研究所 半導体装置
WO2014142043A1 (en) 2013-03-14 2014-09-18 Semiconductor Energy Laboratory Co., Ltd. Method for driving semiconductor device and semiconductor device
JP6773453B2 (ja) * 2015-05-26 2020-10-21 株式会社半導体エネルギー研究所 記憶装置及び電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003283272A (ja) * 2002-01-17 2003-10-03 Semiconductor Energy Lab Co Ltd ソースフォロワ回路
JP2015195074A (ja) * 2014-03-14 2015-11-05 株式会社半導体エネルギー研究所 半導体装置およびその駆動方法、並びに電子機器
JP2016105343A (ja) * 2014-11-21 2016-06-09 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
JP2018156699A (ja) * 2017-03-16 2018-10-04 株式会社半導体エネルギー研究所 半導体装置、電子部品、及び電子機器

Also Published As

Publication number Publication date
US12106823B2 (en) 2024-10-01
DE112021002394T5 (de) 2023-01-26
US20250014616A1 (en) 2025-01-09
JP7782085B2 (ja) 2025-12-08
US20230147770A1 (en) 2023-05-11
KR20230003476A (ko) 2023-01-06
CN115443505A (zh) 2022-12-06
JP2025089335A (ja) 2025-06-12
WO2021209858A1 (ja) 2021-10-21
JP2026032141A (ja) 2026-02-25
JP7653416B2 (ja) 2025-03-28

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