JPWO2021084902A1 - - Google Patents

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Publication number
JPWO2021084902A1
JPWO2021084902A1 JP2021554128A JP2021554128A JPWO2021084902A1 JP WO2021084902 A1 JPWO2021084902 A1 JP WO2021084902A1 JP 2021554128 A JP2021554128 A JP 2021554128A JP 2021554128 A JP2021554128 A JP 2021554128A JP WO2021084902 A1 JPWO2021084902 A1 JP WO2021084902A1
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JP
Japan
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JP2021554128A
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Japanese (ja)
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JPWO2021084902A5 (en
JP7330284B2 (en
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/7999—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto for disconnecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

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  • Laser Beam Processing (AREA)
  • Dicing (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
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US20190035688A1 (en) * 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures
US20190081200A1 (en) * 2017-09-13 2019-03-14 PlayNitride Inc. Method of manufacturing micro light-emitting element array, transfer carrier, and micro light-emitting element array

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JP2015046569A (en) 2013-07-31 2015-03-12 マイクロン テクノロジー， インク． Semiconductor device manufacturing method
CN106601657B (en) 2016-12-12 2019-12-17 厦门市三安光电科技有限公司 Micro-component transfer system, micro-component transfer method, micro-component manufacturing apparatus, and electronic device
WO2018157937A1 (en) 2017-03-02 2018-09-07 Ev Group E. Thallner Gmbh Method and device for bonding chips
KR102515684B1 (en) 2017-11-16 2023-03-30 린텍 가부시키가이샤 Manufacturing method of semiconductor device

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US20190035688A1 (en) * 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures
US20190081200A1 (en) * 2017-09-13 2019-03-14 PlayNitride Inc. Method of manufacturing micro light-emitting element array, transfer carrier, and micro light-emitting element array

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