JPWO2021019674A1 - - Google Patents

Info

Publication number
JPWO2021019674A1
JPWO2021019674A1 JP2021536509A JP2021536509A JPWO2021019674A1 JP WO2021019674 A1 JPWO2021019674 A1 JP WO2021019674A1 JP 2021536509 A JP2021536509 A JP 2021536509A JP 2021536509 A JP2021536509 A JP 2021536509A JP WO2021019674 A1 JPWO2021019674 A1 JP WO2021019674A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021536509A
Other versions
JP7226557B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021019674A1 publication Critical patent/JPWO2021019674A1/ja
Application granted granted Critical
Publication of JP7226557B2 publication Critical patent/JP7226557B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
JP2021536509A 2019-07-30 2019-07-30 キャッシュ使用指標算出装置、キャッシュ使用指標算出方法、および、キャッシュ使用指標算出プログラム Active JP7226557B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/029789 WO2021019674A1 (ja) 2019-07-30 2019-07-30 キャッシュ使用指標算出装置、キャッシュ使用指標算出方法、および、キャッシュ使用指標算出プログラム

Publications (2)

Publication Number Publication Date
JPWO2021019674A1 true JPWO2021019674A1 (ja) 2021-02-04
JP7226557B2 JP7226557B2 (ja) 2023-02-21

Family

ID=74229388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021536509A Active JP7226557B2 (ja) 2019-07-30 2019-07-30 キャッシュ使用指標算出装置、キャッシュ使用指標算出方法、および、キャッシュ使用指標算出プログラム

Country Status (3)

Country Link
US (1) US11822476B2 (ja)
JP (1) JP7226557B2 (ja)
WO (1) WO2021019674A1 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017073045A (ja) * 2015-10-09 2017-04-13 日本電信電話株式会社 キャッシュ競合管理システム、リソース割当サーバおよびリソース割当方法
JP2018112946A (ja) * 2017-01-12 2018-07-19 富士通株式会社 情報処理装置、情報処理装置の制御方法及び情報処理装置の制御プログラム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195867A (ja) * 2005-01-17 2006-07-27 Matsushita Electric Ind Co Ltd バス調停方法及び半導体装置
US8275942B2 (en) * 2005-12-22 2012-09-25 Intel Corporation Performance prioritization in multi-threaded processors
US8560779B2 (en) * 2011-05-20 2013-10-15 International Business Machines Corporation I/O performance of data analytic workloads
KR102441178B1 (ko) * 2015-07-29 2022-09-08 삼성전자주식회사 컴퓨팅 장치에서 캐시 플루딩 프로세스를 관리하기 위한 장치 및 방법
WO2017022002A1 (ja) * 2015-07-31 2017-02-09 株式会社日立製作所 ストレージ装置、ストレージシステム、ストレージシステムの制御方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017073045A (ja) * 2015-10-09 2017-04-13 日本電信電話株式会社 キャッシュ競合管理システム、リソース割当サーバおよびリソース割当方法
JP2018112946A (ja) * 2017-01-12 2018-07-19 富士通株式会社 情報処理装置、情報処理装置の制御方法及び情報処理装置の制御プログラム

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
中村 哲朗 ほか: "キャッシュ競合制御方式の検討 −ＮｅｔｒｏＳｐｈｅｒｅ構想実現に向けて−", 電子情報通信学会２０１６年総合大会講演論文集 通信２, JPN6022045051, 1 March 2016 (2016-03-01), pages 2, ISSN: 0004905220 *
中村 哲朗 ほか: "仮想環境下でのＣＰＵキャッシュにおけるリソース競合回避方式と評価", 電子情報通信学会２０１６年通信ソサイエティ大会講演論文集２, JPN6022045050, 6 September 2016 (2016-09-06), pages 32, ISSN: 0004905219 *

Also Published As

Publication number Publication date
US20220261348A1 (en) 2022-08-18
JP7226557B2 (ja) 2023-02-21
WO2021019674A1 (ja) 2021-02-04
US11822476B2 (en) 2023-11-21

Similar Documents

Publication Publication Date Title
BR112019017762A2 (ja)
BR112021013854A2 (ja)
BR112021018450A2 (ja)
BR112021017939A2 (ja)
BR112021017892A2 (ja)
BR112019016141A2 (ja)
AU2020104490A4 (ja)
BR112021017738A2 (ja)
BR112021017782A2 (ja)
BR112019016138A2 (ja)
BR112019016142A2 (ja)
BR112021018168A2 (ja)
BR112021017728A2 (ja)
BR112021008711A2 (ja)
BR112021018452A2 (ja)
BR112021017703A2 (ja)
BR112021018102A2 (ja)
BR112021012348A2 (ja)
BR112021018250A2 (ja)
BR112021020262A2 (ja)
BR112021018084A2 (ja)
BR112021018093A2 (ja)
BR112021013944A2 (ja)
BR112021013128A2 (ja)
BR112021018484A2 (ja)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221216

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230110

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230123

R150 Certificate of patent or registration of utility model

Ref document number: 7226557

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150