JPWO2020167331A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2020167331A5 JPWO2020167331A5 JP2021547481A JP2021547481A JPWO2020167331A5 JP WO2020167331 A5 JPWO2020167331 A5 JP WO2020167331A5 JP 2021547481 A JP2021547481 A JP 2021547481A JP 2021547481 A JP2021547481 A JP 2021547481A JP WO2020167331 A5 JPWO2020167331 A5 JP WO2020167331A5
- Authority
- JP
- Japan
- Prior art keywords
- misalignment
- semiconductor device
- target
- measuring
- tool
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (20)
同一であることを意図された半導体デバイスウエハのバッチから選択された半導体デバイスの2つの層の間の少なくとも1つのターゲットにおける位置ずれを測定するように構成された光位置ずれ計測ツールと、
前記バッチから選択された半導体デバイスの2つの層の間の前記少なくとも1つのターゲットにおいて位置ずれを測定するように構成された電子ビーム位置ずれ計測ツールと、
前記光位置ずれ計測ツールおよび前記電子ビーム位置ずれ計測ツールの出力を結合して結合された位置ずれメトリックを提供するように機能する結合器と
を備えることを特徴とする、システム。 A misalignment measurement system useful for manufacturing semiconductor device wafers.
An optical misalignment measurement tool configured to measure misalignment at at least one target between two layers of semiconductor devices selected from a batch of semiconductor device wafers intended to be identical.
An electron beam misalignment measuring tool configured to measure misalignment at said at least one target between two layers of semiconductor devices selected from the batch.
The system comprises a coupler that functions to combine the outputs of the optical misalignment measurement tool and the electron beam misalignment measurement tool to provide a coupled misalignment metric.
同一であることを意図された半導体デバイスウエハのバッチから選択された少なくとも1つの半導体デバイスウエハでリソグラフィプロセス内の少なくとも初期ステージを実行することと、
同一であることを意図された半導体デバイスウエハの前記バッチから選択された、少なくとも1つの半導体デバイスウエハのうちの少なくとも1つの2つの層の間の少なくとも1つのターゲットにおける位置ずれを測定するために光位置ずれ計測ツールを使用すること、
同一であることを意図された半導体デバイスウエハの前記バッチから選択された、前記少なくとも1つの半導体デバイスウエハのうちの少なくとも1つの2つの層の間の前記少なくとも1つのターゲットにおける位置ずれを測定するために電子ビーム位置ずれ計測ツールを使用すること、および、
前記光位置ずれ計測ツールおよび前記電子ビーム位置ずれ計測ツールの出力を結合して結合された位置ずれメトリックを提供すること
によって、同一であることを意図された前記半導体デバイスウエハのバッチから選択された、前記少なくとも1つの半導体デバイスウエハの前記少なくとも2つの層の位置ずれをその後に測定することと、
前記リソグラフィプロセスを調整して調整されたリソグラフィプロセスを提供するために前記結合された位置ずれメトリックを使用することと
を含むことを特徴とする、方法。 A method for manufacturing semiconductor device wafers,
Performing at least the initial stage in the lithography process on at least one semiconductor device wafer selected from a batch of semiconductor device wafers intended to be identical.
Optical to measure misalignment at at least one target between at least one two layers of at least one semiconductor device wafer selected from said batch of semiconductor device wafers intended to be identical. Using a misalignment measurement tool,
To measure misalignment in the at least one target between at least one two layers of the at least one semiconductor device wafer selected from the batch of semiconductor device wafers intended to be identical. Using an electron beam misalignment measurement tool, and
Selected from a batch of the semiconductor device wafers intended to be identical by combining the outputs of the optical misalignment measurement tool and the electron beam misalignment measurement tool to provide a combined misalignment metric. Subsequent measurement of the misalignment of the at least two layers of the at least one semiconductor device wafer.
A method comprising adjusting the lithography process to use the combined misalignment metric to provide a tuned lithography process.
同一であることを意図された半導体デバイスウエハのバッチから選択された少なくとも1つの半導体デバイスでリソグラフィプロセスを実行することと、
同一であることを意図された半導体デバイスウエハの前記バッチから選択された少なくとも1つの半導体デバイスの少なくとも2つの層のリソグラフィ後の位置ずれをその後に測定することと、
同一であることを意図された半導体デバイスウエハの前記バッチから選択された少なくとも1つの半導体デバイスでエッチングプロセスをその後に実行することと
を含むことを特徴とする、方法。 The method for manufacturing a semiconductor device wafer according to claim 5, wherein at least one initial stage in the lithography process is performed on the at least one semiconductor device wafer.
Performing a lithography process on at least one semiconductor device selected from a batch of semiconductor device wafers intended to be identical.
Subsequent measurement of post-lithographic misalignment of at least two layers of at least one semiconductor device selected from said batch of semiconductor device wafers intended to be identical.
A method comprising the subsequent execution of an etching process on at least one semiconductor device selected from said batch of semiconductor device wafers intended to be identical.
リソグラフィ後の光位置ずれ計測ツールを使用して、同一であることを意図された半導体デバイスウエハの前記バッチから選択された前記少なくとも1つの半導体デバイスウエハのうちの少なくとも1つの2つの層の間の少なくとも1つのターゲットにおける位置ずれを測定することと、
リソグラフィ後の電子ビーム位置ずれ計測ツールを使用して、同一であることを意図された半導体デバイスウエハの前記バッチから選択された前記少なくとも1つの半導体デバイスウエハのうちの少なくとも1つの前記2つの層の間の前記少なくとも1つのターゲットにおける位置ずれを測定することと、
前記リソグラフィ後の光位置ずれ計測ツールおよび前記リソグラフィ後の電子ビーム位置ずれ計測ツールの出力を結合して結合された位置ずれメトリックを提供することと
を含むことを特徴とする、方法。 The method according to claim 10, wherein the measurement of the positional deviation after the lithography can be performed.
Using a post-lithographic optical misalignment measurement tool, between at least one two layers of the at least one semiconductor device wafer selected from said batch of semiconductor device wafers intended to be identical. Measuring misalignment at at least one target and
At least one of the two layers of the at least one semiconductor device wafer selected from the batch of semiconductor device wafers intended to be identical using a post-lithographic electron beam misalignment measurement tool. Measuring the misalignment of the at least one target between
A method comprising combining the outputs of the post-lithographic optical misalignment measurement tool and the post-lithographic electron beam misalignment measurement tool to provide a combined misalignment metric.
軸に沿った第1のピッチを有する半導体デバイスの第1の層上に形成された第1の周期的構造、および、
前記半導体デバイスの第2の層上に形成されたおよび前記軸に平行な軸に沿った第2のピッチを有する第2の周期的構造
を含むターゲットであり、
前記ターゲットが、光計測に特に適した少なくとも1つの第1の領域と、電子ビーム計測に特に適した、前記少なくとも第1の領域とは別の、少なくとも1つの第2の領域とを含むことを特徴とする、ターゲット。 A target for use in measuring misalignment during manufacturing of semiconductor devices.
A first periodic structure formed on a first layer of a semiconductor device having a first pitch along the axis, and
A target comprising a second periodic structure formed on a second layer of the semiconductor device and having a second pitch along an axis parallel to the axis.
The target includes at least one first region particularly suitable for optical measurement and at least one second region separate from the at least first region particularly suitable for electron beam measurement. Characteristic target.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962806226P | 2019-02-15 | 2019-02-15 | |
US62/806,226 | 2019-02-15 | ||
PCT/US2019/035282 WO2020167331A1 (en) | 2019-02-15 | 2019-06-04 | Misregistration measurements using combined optical and electron beam technology |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2022521490A JP2022521490A (en) | 2022-04-08 |
JPWO2020167331A5 true JPWO2020167331A5 (en) | 2022-06-08 |
JP7317131B2 JP7317131B2 (en) | 2023-07-28 |
Family
ID=72044211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021547481A Active JP7317131B2 (en) | 2019-02-15 | 2019-06-04 | Displacement measurement using combined optical and electron beam technology |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP7317131B2 (en) |
KR (1) | KR20210120110A (en) |
CN (1) | CN113366619A (en) |
TW (1) | TWI804708B (en) |
WO (1) | WO2020167331A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020263461A1 (en) | 2019-06-25 | 2020-12-30 | Kla Corporation | Selection of regions of interest for measurement of misregistration and amelioration thereof |
KR102630496B1 (en) | 2020-04-15 | 2024-01-29 | 케이엘에이 코포레이션 | Mismatch target with device scale features useful for measuring mismatch in semiconductor devices |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891627B1 (en) * | 2000-09-20 | 2005-05-10 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension and overlay of a specimen |
US7009704B1 (en) * | 2000-10-26 | 2006-03-07 | Kla-Tencor Technologies Corporation | Overlay error detection |
US6678038B2 (en) * | 2001-08-03 | 2004-01-13 | Nikon Corporation | Apparatus and methods for detecting tool-induced shift in microlithography apparatus |
US7804994B2 (en) * | 2002-02-15 | 2010-09-28 | Kla-Tencor Technologies Corporation | Overlay metrology and control method |
US6778275B2 (en) * | 2002-02-20 | 2004-08-17 | Micron Technology, Inc. | Aberration mark and method for estimating overlay error and optical aberrations |
US7138629B2 (en) * | 2003-04-22 | 2006-11-21 | Ebara Corporation | Testing apparatus using charged particles and device manufacturing method using the testing apparatus |
JPWO2004107415A1 (en) * | 2003-05-28 | 2006-07-20 | 株式会社ニコン | Position information measuring method and apparatus, and exposure method and apparatus |
US7550361B2 (en) * | 2007-01-02 | 2009-06-23 | International Business Machines Corporation | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
JP2011155119A (en) * | 2010-01-27 | 2011-08-11 | Hitachi High-Technologies Corp | Inspection apparatus and inspection method |
US9093458B2 (en) * | 2012-09-06 | 2015-07-28 | Kla-Tencor Corporation | Device correlated metrology (DCM) for OVL with embedded SEM structure overlay targets |
US9214317B2 (en) * | 2013-06-04 | 2015-12-15 | Kla-Tencor Corporation | System and method of SEM overlay metrology |
WO2016202695A1 (en) * | 2015-06-17 | 2016-12-22 | Asml Netherlands B.V. | Recipe selection based on inter-recipe consistency |
KR102296942B1 (en) * | 2017-05-05 | 2021-09-01 | 에이에스엠엘 네델란즈 비.브이. | How to predict the yield of a device manufacturing process |
-
2019
- 2019-06-04 JP JP2021547481A patent/JP7317131B2/en active Active
- 2019-06-04 WO PCT/US2019/035282 patent/WO2020167331A1/en active Application Filing
- 2019-06-04 CN CN201980091117.6A patent/CN113366619A/en active Pending
- 2019-06-04 KR KR1020217029424A patent/KR20210120110A/en active Search and Examination
-
2020
- 2020-01-22 TW TW109102370A patent/TWI804708B/en active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10249523B2 (en) | Overlay and semiconductor process control using a wafer geometry metric | |
TWI587096B (en) | Overlay target geometry for measuring multiple pitches | |
TWI752237B (en) | Overlay metrology method and system | |
KR101367238B1 (en) | Method of manufacturing semiconductor device and system for manufacturing semiconductor device | |
KR20190026958A (en) | Method and computer program product for controlling positioning of patterns on a substrate in a manufacturing process | |
US11366397B2 (en) | Method and apparatus for simulation of lithography overlay | |
JP7345572B2 (en) | Methods for measuring and correcting misalignment between layers in semiconductor devices, and misalignment targets useful therein | |
US6803292B2 (en) | Method for manufacturing a semiconductor device and semiconductor device with overlay mark | |
JPWO2020167331A5 (en) | ||
CN116203808B (en) | Overlay error measurement method and overlay mark | |
TWI405245B (en) | Semiconductor-device manufacturing method and exposure method | |
US20200266112A1 (en) | Misregistration Measurements Using Combined Optical and Electron Beam Technology | |
JP2022521490A (en) | Misalignment measurement using combined light and electron beam technology | |
JPH11132716A (en) | Overlapping accuracy measuring method in photolithography process and overlapping accuracy measuring mark in photolithography process | |
CN114144730B (en) | Overlay measurement target design | |
JP2663623B2 (en) | Method of forming resist pattern | |
KR20220125338A (en) | How to check a multi-step process | |
US9978625B2 (en) | Semiconductor method and associated apparatus | |
JP2008205312A (en) | Exposure method | |
US20120202142A1 (en) | Manufacturing method of exposure mask, shipment judgment method and manufacturing method of semiconductor device using exposure mask | |
CN115981114B (en) | Method for determining lithography limit stress and method for improving lithography process quality | |
KR100594199B1 (en) | Grid calibration method of exposure apparatus | |
JPH05217845A (en) | Pattern for alignment measurement | |
KR101835806B1 (en) | Method for detecting shape change values on the surface of wafer using a reference mirror | |
CN113835302A (en) | Double patterning exposure method |