JPWO2020160169A5

JPWO2020160169A5 -

Info

Publication number: JPWO2020160169A5
Application number: JP2021541611A
Authority: JP
Publication date: 2023-02-06
Anticipated expiration: 2040-01-29

Claims

A memory circuit formed on a planar surface of a semiconductor substrate and including a plurality of modular memory units,
said memory circuit wherein each of said plurality of modular memory units includes a three-dimensional array of storage transistors accessed by wordlines and bitlines;
A support circuit for the memory circuit formed on the semiconductor substrate underlying the memory circuit and comprising a plurality of modular circuit units, comprising:
said support circuitry being formed such that each of said plurality of modular circuit units underlies an associated one of each modular memory unit to assist memory operations of said modular memory unit;
Each modular memory unit is configured to operate independently with the associated modular circuit unit to perform the memory operation, and operate in parallel with two or more of the modular circuit units to perform the memory operation. A memory device that is configured to

2. The memory device of claim 1, wherein said memory operations include erase, program, read and refresh operations.

receiving one or more control signals each including a command signal and an associated address signal, wherein the address signal included in each control signal designates one of the modular memory units for receiving the associated command signal; 3. The memory device of claim 2, wherein:

each of the modular memory units specified by the address signal is configured to operate in parallel with each associated modular circuit unit to perform the memory operation specified by the associated command signal; 4. The memory device of claim 3.

4. The memory device of claim 3, wherein said control signal is received from a controller integrated circuit formed on another said semiconductor substrate.

The controller integrated circuit includes a host interface for communicating with a host device, logic circuitry configured to implement management functions for the memory device, and one or more for storing write data stored in the memory device. 6. The memory device of claim 5, comprising a write buffer and error correction circuitry for performing error correction on data stored in said memory device.

3. The memory device of claim 2, wherein said memory operation comprises a write operation comprising said program operation followed by said erase operation.

8. The memory device of claim 7, further receiving a write data signal specifying a write data value associated with said write operation.

each modular circuit unit includes a word line driver circuit and a bit line driver circuit; an address decoder that selects the specified modular memory unit and the storage transistor specified therein by decoding the address signal; sense amplifiers for reading storage data from selected storage transistors; voltage sources for generating operating voltages for driver circuits, latches or registers; 4. The memory device of claim 3, comprising a state machine that manages erase operations and said refresh operations.

each modular memory unit is formed to overlie the three-dimensional array of storage transistors and the associated modular circuit unit, and the three-dimensional array of storage transistors and the associated modular circuit unit; further comprising an interconnecting conductor layer electrically connected to
10. The memory device of claim 9, wherein said interconnect conductor layer is provided for performing said memory operations by routing control and data signals between said storage transistors and said modular circuit units.

2. The memory device of claim 1, wherein said memory circuit comprises a semi-volatile memory circuit.

12. The memory device of claim 11, wherein the storage transistors of the semi-volatile memory circuit each have a retention time of one day or more and a lifetime of one million program/erase cycles or more.

2. The memory device of claim 1, wherein said memory circuit comprises a non-volatile memory circuit.

2. The memory device of claim 1, wherein said storage transistors each comprise a storage material programmable by direct tunneling technology.

2. The memory device of claim 1, wherein said storage transistors each comprise a ferromagnetic storage transistor.

4. The memory device of claim 3, wherein said three-dimensional array of storage transistors comprises a plurality of NOR memory strings.

The three-dimensional array of NOR memory strings are arranged parallel in a first direction, and each NOR memory string stacked in a second direction has a common source layer and a common drain, each extending in a third direction. comprising a plurality of said storage transistors sharing a layer, said array of said NOR memory strings further comprising:
(1) a plurality of local word line structures formed between adjacent stacks of said NOR memory strings;
(2) a plurality of said wordlines formed overlying said three-dimensional array and extending in said first direction and each connected to a respective subset of said local wordline structure; and
Each storage transistor is formed at the junction of each NOR memory string and each local word line structure and includes (i) a channel region formed between the common source layer and the common drain layer, (ii) a gate isolation layer. 17. The memory device of claim 16, comprising a layer and (iii) the local wordline structure as a gate conductor.

2. The memory device of claim 1, wherein each modular circuit unit has the same dimensions in first and second directions as the associated modular memory unit.

wherein said address signal of said control signals designates said modular memory unit to be accessed in response to one of said control signals, said modular circuit unit of said designated modular memory unit comprising: 18. The memory device of claim 17, activating one of said word lines to select and activate a page of said bit lines and perform said memory operation indicated by said associated command signal.

Each modular circuit unit
an address decoder and a plurality of word line driver circuits coupled together to select and activate one of the word lines;
a plurality of bit line select transistors coupled together to select the page of the bit lines;
a plurality of sense amplifiers coupled to the bit line select transistors to sense data values associated with the selected bit lines;
one or more data latches for storing data sensed from selected storage transistors;
a voltage generator for generating a power supply voltage, a ground voltage, a program voltage, an erase voltage, a read voltage, or a reference voltage;
20. The state machine of claim 19 for controlling operations of associated memory units to perform said erase, program, read and refresh operations in response to said command signals. memory device.
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