JPWO2020122989A5 - - Google Patents

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Publication number
JPWO2020122989A5
JPWO2020122989A5 JP2021527859A JP2021527859A JPWO2020122989A5 JP WO2020122989 A5 JPWO2020122989 A5 JP WO2020122989A5 JP 2021527859 A JP2021527859 A JP 2021527859A JP 2021527859 A JP2021527859 A JP 2021527859A JP WO2020122989 A5 JPWO2020122989 A5 JP WO2020122989A5
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JP
Japan
Prior art keywords
speed
link
controller
interconnect
improved speed
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JP2021527859A
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English (en)
Japanese (ja)
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JP2022510812A5 (https=
JP2022510812A (ja
JP7420804B2 (ja
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Priority claimed from US16/221,181 external-priority patent/US11151075B2/en
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Publication of JP2022510812A5 publication Critical patent/JP2022510812A5/ja
Publication of JPWO2020122989A5 publication Critical patent/JPWO2020122989A5/ja
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JP2021527859A 2018-12-14 2019-06-27 改良された速度モードによるデータ通信 Active JP7420804B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/221,181 2018-12-14
US16/221,181 US11151075B2 (en) 2018-12-14 2018-12-14 Data communications with enhanced speed mode
PCT/US2019/039505 WO2020122989A1 (en) 2018-12-14 2019-06-27 Data communications with enhanced speed mode

Publications (4)

Publication Number Publication Date
JP2022510812A JP2022510812A (ja) 2022-01-28
JP2022510812A5 JP2022510812A5 (https=) 2022-06-27
JPWO2020122989A5 true JPWO2020122989A5 (https=) 2022-06-27
JP7420804B2 JP7420804B2 (ja) 2024-01-23

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ID=71071666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021527859A Active JP7420804B2 (ja) 2018-12-14 2019-06-27 改良された速度モードによるデータ通信

Country Status (6)

Country Link
US (2) US11151075B2 (https=)
EP (1) EP3895029B1 (https=)
JP (1) JP7420804B2 (https=)
KR (1) KR102865968B1 (https=)
CN (1) CN113196254B (https=)
WO (1) WO2020122989A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11151075B2 (en) * 2018-12-14 2021-10-19 Ati Technologies Ulc Data communications with enhanced speed mode
US11386026B1 (en) 2021-02-09 2022-07-12 Microsoft Technology Licensing, Llc Shell PCIe bridge and shared-link-interface services in a PCIe system
CN120336240B (zh) * 2025-06-20 2025-10-21 上海芯力基半导体有限公司 一种基于PCIe的高速数据传输方法、设备及系统

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US8059673B2 (en) * 2003-05-01 2011-11-15 Genesis Microchip Inc. Dynamic resource re-allocation in a packet based video display interface
US7620062B2 (en) * 2003-05-01 2009-11-17 Genesis Microchips Inc. Method of real time optimizing multimedia packet transmission rate
US7426597B1 (en) * 2003-05-07 2008-09-16 Nvidia Corporation Apparatus, system, and method for bus link width optimization of a graphics system
US9262837B2 (en) * 2005-10-17 2016-02-16 Nvidia Corporation PCIE clock rate stepping for graphics and platform processors
US7461195B1 (en) * 2006-03-17 2008-12-02 Qlogic, Corporation Method and system for dynamically adjusting data transfer rates in PCI-express devices
WO2008076700A2 (en) * 2006-12-13 2008-06-26 Rambus Inc. Interface with variable data rate
US7660925B2 (en) * 2007-04-17 2010-02-09 International Business Machines Corporation Balancing PCI-express bandwidth
US8477831B2 (en) 2010-02-17 2013-07-02 Altera Corporation Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device
TWI408557B (zh) * 2010-03-18 2013-09-11 Faraday Tech Corp 高速輸入輸出系統及其節能控制方法
US9268732B2 (en) 2012-06-08 2016-02-23 Advanced Micro Devices, Inc. Tunnel suitable for multi-segment communication links and method therefor
US8972640B2 (en) * 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
JP6139689B2 (ja) * 2012-10-22 2017-05-31 インテル・コーポレーション 装置
US9244872B2 (en) * 2012-12-21 2016-01-26 Ati Technologies Ulc Configurable communications controller
US9692426B2 (en) * 2013-05-06 2017-06-27 Advanced Micro Devices, Inc. Phase locked loop system with bandwidth measurement and calibration
KR101995623B1 (ko) 2014-01-16 2019-07-02 인텔 코포레이션 고속 구성 메커니즘을 위한 장치, 방법, 및 시스템
US10275387B2 (en) * 2015-08-10 2019-04-30 Mediatek Inc. Method and associated interface circuit for mitigating interference due to signaling of a bus
US9825730B1 (en) 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds
US20180173666A1 (en) 2016-12-16 2018-06-21 Intel Corporation APPARATUSES AND METHODS TO COUPLE AN EMBEDDED UNIVERSAL SERIAL BUS (eUSB) CIRCUIT TO A UNIVERSAL SERIAL BUS (USB) TRANSCEIVER INTERFACE CIRCUIT
US10789201B2 (en) 2017-03-03 2020-09-29 Intel Corporation High performance interconnect
US10880137B2 (en) * 2017-05-12 2020-12-29 Intel Corporation Bypassing equalization at lower data rates
US10545773B2 (en) * 2018-05-23 2020-01-28 Intel Corporation System, method, and apparatus for DVSEC for efficient peripheral management
US11151075B2 (en) * 2018-12-14 2021-10-19 Ati Technologies Ulc Data communications with enhanced speed mode

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