JPWO2020060734A5 - - Google Patents

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JPWO2020060734A5
JPWO2020060734A5 JP2021514963A JP2021514963A JPWO2020060734A5 JP WO2020060734 A5 JPWO2020060734 A5 JP WO2020060734A5 JP 2021514963 A JP2021514963 A JP 2021514963A JP 2021514963 A JP2021514963 A JP 2021514963A JP WO2020060734 A5 JPWO2020060734 A5 JP WO2020060734A5
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Japan
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loop
instructions
processor
component
low power
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JP2021514963A
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Japanese (ja)
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JP7301955B2 (ja
JP2022500777A5 (https=
JP2022500777A (ja
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Priority claimed from US16/134,440 external-priority patent/US10915322B2/en
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JP2021514963A 2018-09-18 2019-08-28 ループ終了予測を用いたプロセッサのループモードの促進又は抑制 Active JP7301955B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/134,440 US10915322B2 (en) 2018-09-18 2018-09-18 Using loop exit prediction to accelerate or suppress loop mode of a processor
US16/134,440 2018-09-18
PCT/US2019/048487 WO2020060734A1 (en) 2018-09-18 2019-08-28 Using loop exit prediction to accelerate or suppress loop mode of a processor

Publications (4)

Publication Number Publication Date
JP2022500777A JP2022500777A (ja) 2022-01-04
JP2022500777A5 JP2022500777A5 (https=) 2022-09-01
JPWO2020060734A5 true JPWO2020060734A5 (https=) 2022-09-01
JP7301955B2 JP7301955B2 (ja) 2023-07-03

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JP2021514963A Active JP7301955B2 (ja) 2018-09-18 2019-08-28 ループ終了予測を用いたプロセッサのループモードの促進又は抑制

Country Status (6)

Country Link
US (2) US10915322B2 (https=)
EP (1) EP3853716A4 (https=)
JP (1) JP7301955B2 (https=)
KR (1) KR102556897B1 (https=)
CN (1) CN112740173A (https=)
WO (1) WO2020060734A1 (https=)

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US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache
US11294681B2 (en) * 2019-05-31 2022-04-05 Texas Instruments Incorporated Processing device with a microbranch target buffer for branch prediction using loop iteration count
US11256318B2 (en) * 2019-08-09 2022-02-22 Intel Corporation Techniques for memory access in a reduced power state
US20210200550A1 (en) * 2019-12-28 2021-07-01 Intel Corporation Loop exit predictor
US11520590B2 (en) * 2020-09-02 2022-12-06 Microsoft Technology Licensing, Llc Detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching
US20220283811A1 (en) * 2021-03-03 2022-09-08 Microsoft Technology Licensing, Llc Loop buffering employing loop characteristic prediction in a processor for optimizing loop buffer performance
US12288067B2 (en) * 2022-06-23 2025-04-29 Arm Limited Prediction of number of iterations of a fetching process
US12373215B2 (en) * 2022-07-25 2025-07-29 Apple Inc. Using a next fetch predictor circuit with short branches and return fetch groups
US20240112050A1 (en) * 2022-09-29 2024-04-04 Nvidia Corporation Identifying idle-cores in data centers using machine-learning (ml)
US12541371B2 (en) 2023-08-23 2026-02-03 Arm Limited Predicting behaviour of control flow instructions using prediction entry types
CN117170747B (zh) * 2023-08-28 2025-10-17 海光信息技术股份有限公司 程序与指令处理、训练与预测方法与装置、处理器
US12411692B2 (en) * 2023-09-07 2025-09-09 Arm Limited Storage of prediction-related data
US12517732B2 (en) 2024-03-22 2026-01-06 Tenstorrent USA, Inc. Processor with one or more progressive conservative execution modes
US12450060B1 (en) * 2024-08-28 2025-10-21 Qualcomm Incorporated Sharing loop cache instances among multiple threads in processor devices

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US6578138B1 (en) 1999-12-30 2003-06-10 Intel Corporation System and method for unrolling loops in a trace cache
JP5043560B2 (ja) 2007-08-24 2012-10-10 パナソニック株式会社 プログラム実行制御装置
US9952869B2 (en) * 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
US8667257B2 (en) 2010-11-10 2014-03-04 Advanced Micro Devices, Inc. Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit
US9116686B2 (en) * 2012-04-02 2015-08-25 Apple Inc. Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction
US9753733B2 (en) * 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9557999B2 (en) * 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9710276B2 (en) * 2012-11-09 2017-07-18 Advanced Micro Devices, Inc. Execution of instruction loops using an instruction buffer
US9459871B2 (en) * 2012-12-31 2016-10-04 Intel Corporation System of improved loop detection and execution
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US9524011B2 (en) * 2014-04-11 2016-12-20 Apple Inc. Instruction loop buffer with tiered power savings
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