JPWO2020060734A5

JPWO2020060734A5 -

Info

Publication number: JPWO2020060734A5
Application number: JP2021514963A
Authority: JP
Publication date: 2022-09-01
Anticipated expiration: 2039-08-28

Claims

predicting the number of loop iterations expected to be executed for a loop associated with a set of loop instructions in a processor;
executing the set of loop instructions in a loop mode responsive to a predicted number of loop iterations exceeding a first loop iteration threshold to reduce power at least one component of an instruction pipeline of the processor; placing in a mode; and executing the set of loop instructions from a loop buffer;
Method.

responsive to the predicted number of loop iterations being less than a second loop iteration threshold, delaying transitioning to the loop mode until a threshold number of loop iterations have been performed;
The method of Claim 1.

responsive to the predicted number of loop iterations being greater than the second loop iteration threshold, transitioning to the loop mode before the threshold number of loop iterations are performed;
3. The method of claim 2.

placing at least one component of the instruction pipeline in a low power mode includes placing a loop end predictor of the processor in the low power mode;
The method of Claim 1.

updating by a loop end predictor a loop iteration number associated with the set of loop instructions after placing at least one component of the instruction pipeline in a low power mode;
determining when to return power to at least one component of the instruction pipeline that is in a low power mode based on the updated loop iteration number;
The method of Claim 1.

further comprising, prior to predicting the number of loop iterations, identifying instructions as the set of loop instructions by matching characteristics of the loop instructions to identifiers in a set of stored loop identifiers;
The method according to any one of claims 1-5.

placing at least one component of the instruction pipeline in a low power mode prior to executing an instruction of the set of loop instructions;
The method of Claim 1.

further comprising predicting the end of the set of loop instructions during the loop mode;
The method of Claim 1.

In response to predicting the number of loop iterations expected to be executed for a loop associated with a set of loop instructions in a processor,
storing the set of loop instructions in a loop buffer;
placing components of the processor's instruction pipeline in a low power mode;
executing the set of loop instructions from the loop buffer;
predicting loop termination by a loop termination predictor of the processor;
returning power to the component placed in a low power mode based on a predicted loop termination.
Method.

further comprising comparing a predicted number of loop iterations to a first loop iteration threshold prior to powering down components of the instruction pipeline;
10. The method of claim 9.

components of the instruction pipeline are placed in a low power mode prior to executing the set of loop instructions from a loop buffer;
10. The method of claim 9.

powering down components of the instruction pipeline includes powering down a loop end predictor of the processor;
The method according to any one of claims 9-11.

a processor,
an instruction cache having a set of loop instructions;
a loop buffer configured to store the set of loop instructions;
a loop end predictor configured to predict the number of loop iterations expected to be executed for a loop associated with the set of loop instructions ;
The processor
executing the set of loop instructions in a loop mode responsive to a predicted number of loop iterations exceeding a first loop iteration threshold to reduce power at least one component of an instruction pipeline of the processor; placing in a mode; and executing the set of loop instructions from the loop buffer;
executing the set of loop instructions in a non-loop mode in response to a predicted number of loop iterations being less than or equal to the first loop iteration threshold, comprising: maintaining an active state; and executing the set of loop instructions fetched from the instruction cache by an instruction fetch unit of the instruction pipeline;
is configured to do
processor.

further comprising a decoder for decoding the set of loop instructions into micro-ops for execution by functional units of the processor;
the instruction fetch unit is configured to provide the loop instruction from the instruction cache to the decoder;
14. The processor of claim 13.

the instruction fetch unit is configured to provide instructions to the loop end predictor;
15. The processor of claim 14.

at least one component of the instruction pipeline placed in the low power mode is an instruction fetch component of the processor;
14. The processor of claim 13.

at least one component of the instruction pipeline placed in the low power mode is the loop end predictor;
14. The processor of claim 13.

The loop end predictor is
configured to update a loop iteration number associated with the set of loop instructions after placing the at least one component of the instruction pipeline in the low power mode;
a timing for returning power to at least one component of the instruction pipeline placed in the low power mode is based on an updated loop iteration number;
A processor according to any of claims 13-17.

further comprising a buffer of stored loop identifiers;
the loop termination predictor is configured to match characteristics of the set of loop instructions to identifiers in the stored buffer of loop identifiers;
14. The processor of claim 13.

Placing at least one component of the instruction pipeline in the low power mode predicts the loop iteration number associated with the set of loop instructions prior to executing instructions associated with the set of loop instructions. is done after
14. The processor of claim 13.