JP7301955B2 - ループ終了予測を用いたプロセッサのループモードの促進又は抑制 - Google Patents

ループ終了予測を用いたプロセッサのループモードの促進又は抑制 Download PDF

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JP7301955B2
JP7301955B2 JP2021514963A JP2021514963A JP7301955B2 JP 7301955 B2 JP7301955 B2 JP 7301955B2 JP 2021514963 A JP2021514963 A JP 2021514963A JP 2021514963 A JP2021514963 A JP 2021514963A JP 7301955 B2 JP7301955 B2 JP 7301955B2
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loop
instructions
processor
mode
instruction
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JP2022500777A5 (https=
JPWO2020060734A5 (https=
JP2022500777A (ja
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アンナマライ アルナーチャラム
エバース マリウス
シャガラジャン アパルナ
ジャービス アンソニー
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
JP2021514963A 2018-09-18 2019-08-28 ループ終了予測を用いたプロセッサのループモードの促進又は抑制 Active JP7301955B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/134,440 US10915322B2 (en) 2018-09-18 2018-09-18 Using loop exit prediction to accelerate or suppress loop mode of a processor
US16/134,440 2018-09-18
PCT/US2019/048487 WO2020060734A1 (en) 2018-09-18 2019-08-28 Using loop exit prediction to accelerate or suppress loop mode of a processor

Publications (4)

Publication Number Publication Date
JP2022500777A JP2022500777A (ja) 2022-01-04
JP2022500777A5 JP2022500777A5 (https=) 2022-09-01
JPWO2020060734A5 JPWO2020060734A5 (https=) 2022-09-01
JP7301955B2 true JP7301955B2 (ja) 2023-07-03

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Country Link
US (2) US10915322B2 (https=)
EP (1) EP3853716A4 (https=)
JP (1) JP7301955B2 (https=)
KR (1) KR102556897B1 (https=)
CN (1) CN112740173A (https=)
WO (1) WO2020060734A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache
US11294681B2 (en) * 2019-05-31 2022-04-05 Texas Instruments Incorporated Processing device with a microbranch target buffer for branch prediction using loop iteration count
US11256318B2 (en) * 2019-08-09 2022-02-22 Intel Corporation Techniques for memory access in a reduced power state
US20210200550A1 (en) * 2019-12-28 2021-07-01 Intel Corporation Loop exit predictor
US11520590B2 (en) * 2020-09-02 2022-12-06 Microsoft Technology Licensing, Llc Detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching
US20220283811A1 (en) * 2021-03-03 2022-09-08 Microsoft Technology Licensing, Llc Loop buffering employing loop characteristic prediction in a processor for optimizing loop buffer performance
US12288067B2 (en) * 2022-06-23 2025-04-29 Arm Limited Prediction of number of iterations of a fetching process
US12373215B2 (en) * 2022-07-25 2025-07-29 Apple Inc. Using a next fetch predictor circuit with short branches and return fetch groups
US20240112050A1 (en) * 2022-09-29 2024-04-04 Nvidia Corporation Identifying idle-cores in data centers using machine-learning (ml)
US12541371B2 (en) 2023-08-23 2026-02-03 Arm Limited Predicting behaviour of control flow instructions using prediction entry types
CN117170747B (zh) * 2023-08-28 2025-10-17 海光信息技术股份有限公司 程序与指令处理、训练与预测方法与装置、处理器
US12411692B2 (en) * 2023-09-07 2025-09-09 Arm Limited Storage of prediction-related data
US12517732B2 (en) 2024-03-22 2026-01-06 Tenstorrent USA, Inc. Processor with one or more progressive conservative execution modes
US12450060B1 (en) * 2024-08-28 2025-10-21 Qualcomm Incorporated Sharing loop cache instances among multiple threads in processor devices

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120117362A1 (en) 2010-11-10 2012-05-10 Bhargava Ravindra N Replay of detected patterns in predicted instructions
JP2013254484A (ja) 2012-04-02 2013-12-19 Apple Inc ベクトル分割ループの性能の向上
US20150293577A1 (en) 2014-04-11 2015-10-15 Apple Inc. Instruction loop buffer with tiered power savings
US20160092230A1 (en) 2014-09-29 2016-03-31 Via Alliance Semiconductor, Ltd. Loop predictor-directed loop buffer
US20160179549A1 (en) 2014-12-23 2016-06-23 Intel Corporation Instruction and Logic for Loop Stream Detection
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
JP2018005488A (ja) 2016-06-30 2018-01-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6578138B1 (en) 1999-12-30 2003-06-10 Intel Corporation System and method for unrolling loops in a trace cache
JP5043560B2 (ja) 2007-08-24 2012-10-10 パナソニック株式会社 プログラム実行制御装置
US9952869B2 (en) * 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
US9753733B2 (en) * 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9710276B2 (en) * 2012-11-09 2017-07-18 Advanced Micro Devices, Inc. Execution of instruction loops using an instruction buffer
US9459871B2 (en) * 2012-12-31 2016-10-04 Intel Corporation System of improved loop detection and execution
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US9875106B2 (en) 2014-11-12 2018-01-23 Mill Computing, Inc. Computer processor employing instruction block exit prediction

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120117362A1 (en) 2010-11-10 2012-05-10 Bhargava Ravindra N Replay of detected patterns in predicted instructions
JP2013254484A (ja) 2012-04-02 2013-12-19 Apple Inc ベクトル分割ループの性能の向上
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US20150293577A1 (en) 2014-04-11 2015-10-15 Apple Inc. Instruction loop buffer with tiered power savings
US20160092230A1 (en) 2014-09-29 2016-03-31 Via Alliance Semiconductor, Ltd. Loop predictor-directed loop buffer
US20160179549A1 (en) 2014-12-23 2016-06-23 Intel Corporation Instruction and Logic for Loop Stream Detection
JP2018005488A (ja) 2016-06-30 2018-01-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Also Published As

Publication number Publication date
CN112740173A (zh) 2021-04-30
US11256505B2 (en) 2022-02-22
US20200089498A1 (en) 2020-03-19
EP3853716A4 (en) 2022-06-15
US20210191722A1 (en) 2021-06-24
JP2022500777A (ja) 2022-01-04
KR20210046806A (ko) 2021-04-28
WO2020060734A1 (en) 2020-03-26
KR102556897B1 (ko) 2023-07-18
US10915322B2 (en) 2021-02-09
EP3853716A1 (en) 2021-07-28

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