JPWO2020031538A1 - Drive circuit, drive system - Google Patents

Abstract

A drive circuit is provided that includes a drive NMOS transistor and a drive MIMO transistor in which a common drain is connected to the load, and a level shift circuit. The level shift circuit consists of a first transistor which is an NMOS transistor, a second transistor which is an NMOS transistor, a third source which is set to a second potential, a third transistor which is a MPa transistor, and a fourth transistor which is a MPa transistor. It has a transistor. The first drain of the first transistor and the fourth gate of the fourth transistor are connected, and the second drain of the second transistor and the third gate of the third transistor are connected. A complementary pulse signal is input to each input terminal, and the pulse signal is set to a period in which each input terminal becomes a reference potential when the signal level is switched.

Description

The present invention relates to drive circuits and drive systems.

Conventionally, as an inverter device for driving a motor, a device provided with a dedicated IC that generates a signal for a switch element that controls a voltage applied to the motor based on a command from a microcontroller is known (for example, Japan). See FIG. 1 of National Registered Gazette Patent No. 5652240).

Japan Registration Gazette: Patent No. 5652240

When a dedicated IC is provided in a drive circuit that drives a load such as a motor, the degree of freedom in design is high, so that it is more advantageous in terms of characteristics such as power consumption, responsiveness, and energy loss than when a dedicated IC is not provided. However, it is disadvantageous in terms of cost.

Therefore, it is preferable to configure the drive circuit without using a dedicated IC. In that case, it is also required to prevent the through current in the drive circuit from the viewpoint of protecting the element.

Therefore, an object of the present invention is to realize performance improvement without using a dedicated IC when switching and driving a load, and to prevent a through current.

An exemplary first invention of the present application is a first in which a common drain is connected to a load, a driving NMOS transistor and a driving MIMO transistor, and a reference potential fluctuating between a reference potential and a first potential higher than the reference potential. Based on the potentials of the input terminal and the second input terminal, the gate potentials of the driving NMOS transistor and the driving MIMO transistor fluctuate between the reference potential and the second potential higher than the first potential. A level shift circuit for processing signals as described above is provided, the source of the driving NMOS transistor is provided on the reference potential side, the source of the driving MIMO transistor is set to the second potential, and the level shift circuit is provided. The first transistor, which is an NMOS transistor having a first source set to the reference potential, a first gate connected to the first input terminal, and a first drain, is set to the reference potential. A second transistor, which is an NMOS transistor having a second source, a second gate connected to the second input terminal, and a second drain connected to the gate of the driving NMOS transistor, and the second potential. A third transistor, which is a epitaxial transistor having a third source set to, a third gate, and a third drain connected to the first drain, and a fourth source set to the second potential. A fourth transistor, which is a epitaxial transistor having a fourth gate, a fourth drain connected to the second drain and a fourth drain connected to the gate of the driving MIMO transistor, and the first drain and the fourth drain. A gate is connected, the second drain and the third gate are connected, and complementary pulse signals are input to the first input terminal and the second input terminal, and the pulse signal is a signal level. This is a drive circuit in which a period during which both the first input terminal and the second input terminal become the reference potential when is switched is set.

According to the present invention, when the load is switched and driven, the performance can be improved without using a dedicated IC, and the through current can be prevented.

It is a figure which shows the system structure of the motor drive system of 1st Embodiment. It is a circuit diagram of the drive circuit of 1st Embodiment. It is a timing chart which shows the operation of the drive circuit of 1st Embodiment. It is a figure which shows the structural example of the MOS transistor of the drive circuit of 1st Embodiment. It is a figure which shows another structural example of the MOS transistor of the drive circuit of 1st Embodiment. It is a circuit diagram of the drive circuit of the 2nd Embodiment. It is a figure which shows an example of the current waveform of each part of the drive circuit of 2nd Embodiment. It is a figure which shows an example of the current waveform of each part of the drive circuit of 2nd Embodiment. It is a figure which shows an example of the current waveform of each part of the drive circuit of 2nd Embodiment. It is a circuit diagram of the drive circuit of the 3rd Embodiment. It is a figure which shows the equivalent circuit of each variable resistor included in the drive circuit of 3rd Embodiment. It is a figure which shows the structural example of the P / N type variable resistor included in the drive circuit of 3rd Embodiment. It is a circuit diagram of the drive circuit of 4th Embodiment. It is a circuit diagram of the drive circuit of the 5th Embodiment.

Hereinafter, a motor drive system according to an embodiment of the drive system of the present invention will be described.

(1) First embodiment

(1-1) System configuration

Hereinafter, an embodiment of the motor drive system of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a system configuration of the motor drive system 1 of the embodiment. The motor drive system 1 includes an inverter device 2, a linear regulator (LDO: Low Dropout) 3, a CPU (Central Processing Unit) 5, and a three-phase AC motor M. CPU 5 is an example of a microcontroller.

The inverter device 2 includes a three-phase voltage generation unit 10 and a level shift circuit group 20, generates three-phase AC power, and supplies the three-phase AC power to the three-phase AC motor M. The three-phase AC motor M is equipped with a Hall sensor 100 for each phase that detects the position of the rotor.

In the following description, the voltage of the node or terminal in the circuit means a potential based on the ground potential GND (in the following description, it is referred to as “GND potential”). For example, although the highest potential in the inverter apparatus 2 is at the power supply potential _V CC (+ 12V), GND potential for good regarded as 0V, as appropriate, also referred to as "power supply voltage Vcc '.

The linear regulator 3 lowers the power supply voltage Vcc (+ 12V) to a predetermined voltage required for the CPU 5 to operate (+ 3.3V in the example of the present embodiment) and supplies the power supply voltage to the CPU 5.

The CPU 5 supplies a pulse signal having an amplitude of 3.3 V to each of the level shift circuits 21 to 23 of the level shift circuit group 20. Each level shift circuit converts the pulse signal from the CPU 5 into a signal level at which the MOS transistor in the three-phase voltage generation unit 10 can operate.

In FIG. 1, the level shift circuits 21 to 23 correspond to the nodes N11 to N13, respectively, and correspond to the output terminals of the drive circuit described later.

(1-2) Configuration of inverter device 2

Hereinafter, the configuration of the inverter device 2 will be described in detail.

As shown in FIG. 1, the three-phase voltage generation unit 10 of the inverter device 2 includes an NMOS transistors Q11, Q21, and Q31 as low-side switches and epitaxial transistors Q12, Q22, and Q32 as high-side switches. Since the three-phase AC motor M may operate with 100% duty, the three-phase voltage generator 10 uses a high-side switch as a epitaxial transistor.

In the present embodiment, the epitaxial transistor Q12 and the NMOS transistor Q11 are provided for the U phase of the three-phase AC power supplied to the three-phase AC motor M. The U-phase voltage Vu, which is the U-phase output voltage, is generated by the switching operation of the epitaxial transistor Q12 and the NMOS transistor Q11.

Similarly, the epitaxial transistor Q22 and the NMOS transistor Q21 are provided for the V phase of the three-phase AC power supplied to the three-phase AC motor M. A V-phase voltage Vv, which is a V-phase output voltage, is generated by the switching operation of the epitaxial transistor Q22 and the NMOS transistor Q21. The epitaxial transistor Q32 and the NMOS transistor Q31 are provided for the W phase of the three-phase AC power supplied to the three-phase AC motor M. A W-phase voltage Vw, which is a W-phase output voltage, is generated by performing a switching operation between the epitaxial transistor Q32 and the NMOS transistor Q31.

The sources of the NMOS transistors Q11, Q21, and Q31 are set to the ground potential GND. The sources of the epitaxial transistors Q12, Q22, and Q32 are connected to the power supply voltage Vcc of the inverter device 2.

A common drain (node N11) of the U-phase NMOS transistor Q11 and the epitaxial transistor Q12 is connected to one end of the U-phase winding (not shown) of the three-phase AC motor M. Similarly, the common drain (node N12) of the V-phase IMS transistor Q21 and the epitaxial transistor Q22 is connected to one end of the V-phase winding (not shown) of the three-phase AC motor M and is a W-phase NMOS transistor. A common drain (node N13) of the Q31 and the epitaxial transistor Q32 is connected to one end of a W-phase winding (not shown) of the three-phase AC motor M.

The CPU 5 informs the level shift circuits 21 to 23 of the level shift circuit group 20 based on the signals Hu, Hv, and Hw indicating the detection values of each phase of the Hall sensor 100 that detects the position of the rotor of the three-phase AC motor M. Determine the duty ratio of the pulse signal to be supplied. The signals Hu, Hv, and Hw are sinusoidal signals having a phase difference of 120 degrees in order. The CPU 5 supplies a pulse signal having a determined duty ratio to each level shift circuit. The amplitude of the pulse signal supplied to each level shift circuit is 3.3 V, which is the same as the operating voltage of the CPU 5.

Each level shift circuit of the level shift circuit group 20 converts the pulse signal from the CPU 5 having an amplitude of 3.3 V into a pulse signal having an amplitude of 12 V. The level shift circuit 21 inputs a level-converted pulse signal to each gate of the U-phase NMOS transistor Q11 and the polyclonal transistor Q12. The level shift circuit 22 inputs a level-converted pulse signal to each gate of the V-phase NMOS transistor Q21 and the MPa transistor Q22. The level shift circuit 23 inputs a level-converted pulse signal to each gate of the W-phase NMOS transistor Q31 and the Possible transistor Q32.

The pulse signals level-converted by the level shift circuits 21, 22, and 23 control the operations of the low-side switches Q11, Q21, and Q31 and the high-side switches µtransistors Q12, Q22, and Q32.

(1-3) Configuration of level shift circuit group 20

Hereinafter, the configuration of the level shift circuit group 20 will be described in more detail with reference to FIG. FIG. 2 shows a circuit configuration of a drive circuit including a level shift circuit 21 and a U-phase NMOS transistor Q11 and a epitaxial transistor Q12 corresponding to the level shift circuit 21 in the three-phase voltage generation unit 10.

It comprises a drive circuit with a level shift circuit 22 and corresponding V-phase NMOS transistors Q21 and ProLiant transistors Q22, and a level shift circuit 23 and corresponding W-phase IMS transistors Q31 and ProLiant transistors Q32. The drive circuit is the same as in the case of the U phase. Therefore, in the following, only the case of the U phase will be described, and the duplicate description of the V phase and the W phase will be omitted.

A common drain of the NMOS transistor Q11 (example of a driving NMOS transistor) and the epitaxial transistor Q12 (example of a driving MIMO transistor) is connected to a three-phase AC motor M as a load. The source of the NMOS transistor Q11 is set to the ground potential GND, and the source of the PMOS transistor Q12 is set to the power supply potential _{V CC.}

The level shift circuit 21 is based on the potentials of the first input terminal P1 and the second input terminal P2 that fluctuate between the ground potential GND (example of reference potential) and 3.3V (example of first potential), and NOTE Signal processing is performed so that the potentials of the gates of the transistor Q11 and the epitaxial transistor Q12 _{fluctuate between the ground potential GND and the power supply potential VCC} (+ 12V; example of the second potential).

To the first input terminal P1 and the second input terminal P2, pulse signals that are complementary to each other and fluctuate between the ground potential GND and 3.3 V are input from the CPU 5.

The level shift circuit 21 includes an NMOS transistor M1 (example of the first transistor), an NMOS transistor M2 (example of the second transistor), a MPa transistor M3 (an example of the third transistor), and a MIMO transistor M4 (an example of the fourth transistor). Example) and.

The NMOS transistor M1 includes a source set to the ground potential GND (example of the first source), a gate connected to the first input terminal P1 (example of the first gate), and a drain (example of the first drain). , Have.

The NMOS transistor M2 is connected to a source set to the ground potential GND (example of the second source), a gate connected to the second input terminal P2 (example of the second gate), and a gate of the NMOS transistor Q11. It has a drain (an example of a second drain) and.

The epitaxial transistor M3 includes _{a source (example of the third source) set to the power potential VCC} , a gate (example of the third gate), and a drain connected to the drain of the NMOS transistor M1 (example of the third drain). And have.

The epitaxial transistor M4 includes _{a source (example of the fourth source) set to the power potential VCC} , a gate (example of the fourth gate), and a drain connected to the gate of the epitaxial transistor Q12 (example of the fourth drain). And have. The gate of the epitaxial transistor M4 is connected to the drain of the NMOS transistor M2.

The drain of the NMOS transistor M1 and the gate of the epitaxial transistor M4 are connected, and the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3 are connected.

The level shift circuit 21 has a drain resistor Rd1 (an example of a first drain resistor) and a drain resistor Rd2 (an example of a second drain resistor). The drain resistor Rd1 is provided between the drain of the NMOS transistor M1 and the drain of the epitaxial transistor M3. The drain resistor Rd2 is provided between the drain of the NMOS transistor M2 and the drain of the epitaxial transistor M4.

(1-4) Operation of drive circuit

Next, the operation of the drive circuit including the level shift circuit 21, the NMOS transistor Q11 and the epitaxial transistor Q12 will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the drive circuit shown in FIG. In FIG. 3, the first and second timing charts from the top show the ON / OFF state of the epitaxial transistor Q12 and the ON / OFF state of the NMOS transistor Q11, respectively. In FIG. 3, the third, fourth, and fifth timing charts from the top show the drain voltage Vd1 of the NMOS transistor M1, the drain voltage Vd4 of the epitaxial transistor M4, and the drain voltage Vd2 of the NMOS transistor M2, respectively. .. In FIG. 3, the sixth and seventh timing charts from the top show the voltage V2 of the second input terminal P2 and the voltage V1 of the first input terminal P1.

The maximum value (12V) of each drain voltage shown in FIG. 3 is a value ignoring the voltage drop due to the on-resistance and the drain resistance of each MOS transistor.

In the operation example shown in FIG. 3, for the purpose of explanation, a case where the voltage V2 of the second input terminal P2 and the voltage V1 of the first input terminal P1 are pulses and the duty ratio thereof is approximately 50% is shown.

From time t0 to before reaching time t1, the voltage V1 of the first input terminal P1 is 3.3V (hereinafter referred to as “H level”), and the voltage V2 of the second input terminal P2 is the GND level (hereinafter referred to as “H level”). It is called "L level". Therefore, from time t0 to before reaching time t1, the NMOS transistor M1 is off, the NMOS transistor M2 is on, the epitaxial transistor M3 is on, the epitaxial transistor M4 is off, the epitaxial transistor Q12 is on, and the NMOS transistor Q11 is off. There is.

At time t1, the voltage V2 of the second input terminal P2 changes from H level to L level. During the period from the time t1 to the time t2 (dead time dt), the voltage V1 of the first input terminal P1 and the voltage V2 of the second input terminal P2 are both set to L level, so that both the NMOS transistors M1 and M2 are set to L level. Turn off to prevent through current.

At this time, the drain voltage Vd2 of the NMOS transistor M2 (that is, the gate of the NMOS transistor Q11) is at the GND level, and the NMOS transistor Q11 is off.

At time t2, the voltage V1 of the first input terminal P1 becomes H level, so that the NMOS transistor M1 is turned on, and as shown in FIG. 3, the drain voltage Vd1 of the NMOS transistor M1 drops from 12V to the GND level. When the drain voltage Vd1 reaches the threshold voltage TH1 in the middle of the decrease, the voltage at the gate of the epitaxial transistor M4 also drops to the threshold voltage TH1, so that the epitaxial transistor M4 is turned on. Therefore, the drain voltage Vd4 of the epitaxial transistor M4 rises from the GND level to 12V. When the drain voltage Vd4 reaches the threshold voltage TH4 in the middle of the rise, the gate of the epitaxial transistor Q12 also rises to the threshold voltage TH4, so that the epitaxial transistor Q12 is turned off.

On the other hand, as the drain voltage Vd4 of the epitaxial transistor M4 rises, the drain voltage Vd2 of the NMOS transistor M2 rises with a delay time determined by the drain resistor Rd2 and the parasitic capacitor. When the drain voltage Vd2 reaches the threshold voltage TH2, the gate of the NMOS transistor Q11 also rises to the threshold voltage TH2, so that the NMOS transistor Q11 is turned on.

As the drain voltage Vd2 of the NMOS transistor M2 rises, the gate potential of the epitaxial transistor M3 rises, so that the epitaxial transistor M3 is turned off.

At time t3, the voltage V1 of the first input terminal P1 changes from H level to L level. During the period from time t3 to time t4 (dead time dt), the voltage V1 of the first input terminal P1 and the voltage V2 of the second input terminal P2 are both set to L level, so that both the NMOS transistors M1 and M2 are set to L level. Turn off to prevent through current.

At this time, the drain voltage Vd1 of the NMOS transistor M1 maintains the GND level.

At time t4, the voltage V2 of the second input terminal P2 changes from the L level to the H level, so that the NMOS transistor M2 is turned on, and as shown in FIG. 3, the drain voltage Vd2 of the NMOS transistor M2 changes from 12V to the GND level. Descend. When the drain voltage Vd2 reaches the threshold voltage TH2 in the middle of the decrease, the gate of the NMOS transistor Q11 also drops to the threshold voltage TH2, so that the NMOS transistor Q11 is turned off.

With a decrease of the drain voltage Vd2 of the NMOS transistors M2, also decreases the voltage of the gate of the PMOS transistor M3 connected to the drain of the NMOS transistors M2, the gate-source voltage _{V GS} of the PMOS transistor M3 exceeds the threshold voltage, The epitaxial transistor M3 is turned on. When the epitaxial transistor M3 is turned on, the drain voltage Vd1 of the NMOS transistor M1 rises with a delay time determined by the drain resistor Rd1 and the parasitic capacitor, as shown in FIG. When the drain voltage Vd1 reaches the threshold voltage TH1 in the middle of its raised, the gate voltage of the PMOS transistor M4 connected to the drain of the NMOS transistor M1 becomes the threshold voltage TH1, the gate-source voltage _{V GS} of the PMOS transistor M4 is the threshold It drops below the voltage. As a result, the epitaxial transistor M4 is turned off.

When the epitaxial transistor M4 is turned off, the drain voltage Vd4 of the epitaxial transistor M4 drops. When the drain voltage Vd4 decreases to the threshold voltage TH4, the PMOS transistor Q12 also decreases to the threshold voltage TH4, the PMOS transistor Q12 is turned on the gate-source voltage _{V GS} of the PMOS transistor Q12 exceeds the threshold voltage.

At time t5, the voltage V2 of the second input terminal P2 changes from H level to L level. The state of each part at time t5 is the same as the state of each part at time t1, and the same operation is repeated thereafter.

In FIG. 3, the period during which both the epitaxial transistor Q12 and the NMOS transistor Q11 are off is shown as a dead time DT. That is, the dead time DT is a period in which the pulse signals input to the first input terminal P1 and the second input terminal P2 both become the ground potential GND when the signal level is switched. The dead time DT is determined by the dead time dt set at the voltage V1 of the first input terminal P1 and the voltage V2 of the second input terminal P2, and the delay time caused by the drain resistors Rd1 and Rd2 and the parasitic capacitor.

As described with reference to FIGS. 2 and 3, the drive circuit of the present invention has the following advantageous effects.

(i) When the epitaxial transistor Q12 is on, the NMOS transistor M1 is off, the NMOS transistor M2 is on, the epitaxial transistor M3 is on, and the epitaxial transistor M4 is off. When the NMOS transistor Q11 is on, the NMOS transistor M1 is on, the NMOS transistor M2 is off, the epitaxial transistor M3 is off, and the epitaxial transistor M4 is on. Therefore, the current flowing through the polyclonal transistor M3, the drain resistor Rd1, and the NMOS transistor M1 and the current flowing through the epitaxial transistor M4, the drain resistors Rd2, and the NMOS transistor M2 become zero at steady state, and low power consumption is realized.

(ii) In the drive circuit of FIG. 2, the drain of the epitaxial transistor M4 is connected to the gate of the epitaxial transistor Q12. Therefore, when the voltage V1 of the first input terminal P1 changes from the L level to the H level (time t2 in FIG. 3), the NMOS transistor M1 is turned on and the epitaxial transistor M4 is turned on, and the gate potential of the epitaxial transistor Q12 rises rapidly. Then, the PRIVATE transistor Q12 is turned off. That is, the epitaxial transistor Q12 can be turned off at high speed.

(iii) When the NMOS transistor Q11 is turned on, the NMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, the epitaxial transistor M3 is turned off, and the epitaxial transistor M4 is turned on. Therefore, the gate-source voltage _{V GS} of the NMOS transistor Q11 is a rather 3.3V Input Voltage power supply voltage Vcc (+ 12V). Therefore, the on-resistance of the NMOS transistor Q11 can be set to a low value, which contributes to loss reduction.

As described above, in the motor drive system 1 of the present embodiment, the drive circuit for driving the three-phase AC motor M boosts the low power pulse signal of 3.3 V from the CPU 5 to the power supply voltage Vcc (+ 12 V). The driving MOS transistor is controlled by providing the level shift circuits 21 to 23 to be operated. Since each level shift circuit has low power consumption, excellent responsiveness, and operates with low loss, performance improvement can be realized without using a dedicated IC.

In the drive circuit of the above-described embodiment, it is not always essential to have the drain resistance Rd1 and the drain resistance Rd2. However, by providing the drain resistor Rd1 and the drain resistor Rd2, it is possible to provide the dead time DT of the NMOS transistor Q11 and the epitaxial transistor Q12 even when the dead time dt is not set in the input signal. Further, by setting the dead time dt in the input signal, the dead time margin can be expanded.

(1-5) Structure of MOS transistor

A preferred MOS transistor structure in the drive circuit of the present embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram showing a structural example of the MOS transistor of the drive circuit of the present embodiment. FIG. 5 is a diagram showing another structural example of the MOS transistor of the drive circuit of the present embodiment.

Note that, in FIG. 4, of the level shift circuits 21 of the drive circuit shown in FIG. 2, only the NMOS transistor M2, the drain resistor Rd2, and the epitaxial transistor M4 are shown, but the NMOS transistor M1, the drain resistor Rd1, and the MIMO transistor are shown. The transistor M3 can have the same structure.

In the structural example of the MOS transistor shown in FIG. 4, the NMOS transistor Q11 and the MPLS transistor Q12, which are the driving MOS transistors, have a vertical structure. In the vertical structure, as shown in FIG. 4, the drain electrode is provided on the side opposite to the gate electrode and the source electrode. Since the common drain of the NMOS transistor Q11 and the polyclonal transistor Q12 is connected to the node N11 (see FIG. 1), they can be mounted on the same metal (lead frame).

By adopting the vertical structure, the on-resistance of the NMOS transistor Q11 and the epitaxial transistor Q12 can be lowered.

On the other hand, in the structural example of the MOS transistor shown in FIG. 4, the NMOS transistor M2 and the MPLS transistor M4 included in the level shift circuit 21 have a horizontal structure. As will be clarified in the embodiment described later, since a large number of level shift circuits may be provided, the degree of integration can be increased and the cost can be reduced by integrating the MOS transistors in the level shift circuits into one chip as a horizontal structure. Can be done.

The MOS transistors in the level shift circuit may have a vertical structure, and all the MOS transistors in the drive circuit may be configured only in the vertical structure together with the NMOS transistors Q11 and the NMOS transistors Q12 having the vertical structure.

In the NMOS transistor M2 and the NMOS transistor M4, the maximum rated voltage V _GSS between the gate and source must satisfy the power supply voltage Vcc (+ 12V), but in the case of a general MOS transistor having a horizontal structure inside an IC, the gate source The maximum rated voltage _GSS is about 5V. However, since each MOS transistor of the level shift circuit 21 shown in FIG. 2 does not require a large drive capability or low on-resistance, the gate oxide film is made thicker than that of a general MOS transistor having a horizontal structure between gate sources. The maximum rated voltage V _GSS can be increased. That is, even if the MOS transistor has a horizontal structure, the maximum rated voltage V _GSS between the gate and source can be set to 12 V or more.

Since the p-type substrate of the NMOS transistor M2 and the MIMO transistor M4 has a GND potential, it is necessary to separate the lead frame of the NMOS transistor Q11 and the MIMO transistor Q12. Therefore, a bonding pad region is provided on the chip for the MOS transistor having a horizontal structure of the level shift circuit, and the connection with the driving MOS transistor having a vertical structure is performed by wire bonding.

The structure example of the MOS transistor shown in FIG. 5 has a structure in which there is no p-well of the MOS transistor having a horizontal structure as compared with FIG. Such a structure may be applied as a MOS transistor having a horizontal structure, or may be combined with a MOS transistor having a vertical structure shown in FIG.

(2) Second embodiment

Next, the motor drive system of the second embodiment will be described. The overall configuration of the motor drive system of this embodiment is the same as that shown in FIG. 1, and the drive circuit is different from that shown in FIG.

FIG. 6 is a circuit diagram of the drive circuit of the second embodiment. The drive circuit shown in FIG. 6 differs from the drive circuit shown in FIG. 2 in that each MOS transistor in the level shift circuit is provided with a source resistor and a gate resistor. That is, the level shift circuit 21A of the drive circuit of the present embodiment includes the following resistors.

Ground potential source resistance between the source GND node _{N GND} and the NMOS transistor M1 Rs1 (first example of the source resistance)

-Gate resistance Rg1 between the first input terminal P1 and the gate of the NMOS transistor M1 (example of first gate resistance)

Ground potential source resistance between the GND node _{N GND} and the source of the NMOS transistor M2 of Rs2 (example of the second source resistor)

-Gate resistance Rg2 between the second input terminal P2 and the gate of the NMOS transistor M2 (example of second gate resistance)

- power supply potential source resistance between the Vcc node source of _{N VCC} and PMOS transistor M3 of the Rs3 (third example of the source resistance)

-Gate resistance Rg3 between the gate of the epitaxial transistor M3 and the drain of the NMOS transistor M2 (example of the third gate resistance)

- power supply potential source resistance between the Vcc source node _{N VCC} and the PMOS transistor M4 of Rs4 (fourth example of the source resistance)

-Gate resistance Rg4 between the gate of the epitaxial transistor M4 and the drain of the NMOS transistor M1 (example of the fourth gate resistance)

In the example shown in FIG. 6, a level shift circuit 21A including all source resistors Rs1 to Rs4 and gate resistors Rg1 to Rg4 of each MOS transistor is shown, but the present invention is not limited to this, and at least one of these resistors is used. It suffices to have one resistor.

In the present embodiment, the source resistors Rs1 to Rs4 and the gate resistors Rg1 to Rg4 of each MOS transistor are provided in order to suppress the penetration current and the drain current of each MOS transistor.

7 to 9 show the current waveforms of each part when the NMOS transistor Q11 and the epitaxial transistor Q12 are turned on / off when the source resistors Rs1 to Rs4 and the gate resistors Rg1 to Rg4 are changed, respectively. Specifically, the waveforms of the output current I _OUT , the drain current I _{Q12 of the epitaxial} transistor Q12, the drain current IQ 11 of the NMOS transistor _Q11 , and the drain current I M4D of the epitaxial transistor M4 are shown. Of the drain currents of the MOS transistors in the level shift circuit 21A, the drain current I _M4D of the NMOS transistor M4 is the largest, so FIGS. 7 to 9 show only the waveform of the _{drain current I M4D.}

7 to 9 are all cases where the drain resistors Rd1 and Rd2 are both 500Ω. FIG. 7 shows a case where the source resistors Rs1 to Rs4 and the gate resistors Rg1 to Rg4 are not set.

FIG. 8 shows a case where the source resistors Rs1 and Rs2 are both 50Ω, the source resistors Rs3 and Rs4 are both 100Ω, the gate resistors Rg1 and Rg2 are both 500Ω, and the gate resistors Rg3 and Rg4 are both 100Ω. ing.

FIG. 9 shows a case where the drain resistance Rd2 is changed from 500Ω to 2000Ω with respect to the case of FIG.

In the case of FIG. 7, the conditions are substantially the same as in the case where the drain resistors Rd1 and Rd2 are set to 500Ω in FIG. In this case, the peak current of _{the drain current IM4D is as high as 800 mA.}

On the other hand, in FIG. 8, by setting the source resistance and the gate resistance, _{the peak current of the drain current IM4D} becomes 80 mA, and the drain current IM4D is about _{1/10 of that in the case of FIG.} However, the penetration current of the NMOS transistor Q11 and the epitaxial transistor Q12 increases up to 20A. This is because the NMOS transistor Q11 and the MPa transistor Q12 are turned on at the same time and a through current is flowing. Therefore, by increasing the drain resistance Rd2, as shown in FIG. 9, the penetrating current of the NMOS transistor Q11 and the epitaxial transistor Q12 is eliminated, the drain current is reduced to 600 mA of the stationary current, and the drain current I of the epitaxial transistor M4 is reduced. _M4D can be maintained at 80 mA.

As can be seen from FIGS. 7 to 9, by appropriately providing a source resistor and a gate resistor in each MOS transistor in the level shift circuit 21A, the penetration current of the NMOS transistor Q11 and the NMOS transistor Q12 can be reduced. At the same time, the drain current of each MOS transistor in the level shift circuit 21A can be reduced. In each MOS transistor in the level shift circuit 21A, the presence / absence of the source resistance and / or the gate resistance, and the resistance value when the source resistance and / or the gate resistance are provided are the value of the power supply voltage and the driving MOS transistor. It can be appropriately determined according to the on-resistance and the like. The upper limit of the resistance value of the source resistance and / or the gate resistance can be determined according to the permissible level of responsiveness to the high frequency pulse input signal.

As described above, according to the drive circuit of the present embodiment, since the source resistance and / or the gate resistance is provided for the MOS transistor in the level shift circuit with respect to the drive circuit of the first embodiment, it penetrates. It is possible to further suppress the current and drain current.

(3) Third embodiment

Next, the motor drive system of the third embodiment will be described with reference to FIGS. 10 to 12. The overall configuration of the motor drive system of this embodiment is the same as that shown in FIG. 1, and the gate drive circuit is different from that shown in FIG.

FIG. 10 is a circuit diagram of the drive circuit of the third embodiment. FIG. 11 is a diagram showing an equivalent circuit of each variable resistor included in the drive circuit of the present embodiment. FIG. 12 is a diagram showing a configuration example of a P / N type variable resistor included in the drive circuit of the present embodiment.

The drive circuit shown in FIG. 10 differs from the drive circuit shown in FIG. 6 in that each MOS transistor in the level shift circuit is provided with a drain variable resistor, a source variable resistor, and a gate variable resistor. That is, the level shift circuit 21B of the drive circuit of the present embodiment includes the following resistors.

-Drain variable resistor Rd1_pn between the drain of the NMOS transistor M1 and the drain of the epitaxial transistor M3 (example of the first drain variable resistor)

-Drain variable resistor Rd2_pn between the drain of the NMOS transistor M2 and the drain of the epitaxial transistor M4 (example of the second drain variable resistor)

Ground potential GND at the node _{N GND} and the source variable resistor Rs1_n between the source of the NMOS transistor M1 (first example of the source variable resistor)

-Gate variable resistor Rg1_n between the first input terminal P1 and the gate of the NMOS transistor M1 (example of the first gate variable resistor)

- the ground potential GND node _{N GND} and the source variable resistance between the source of the NMOS transistor M2 Rs2_n (second example of the source variable resistor)

-Gate variable resistor Rg2_n between the second input terminal P2 and the gate of the NMOS transistor M2 (example of the second gate variable resistor)

- power supply potential Vcc at the node _{N VCC} and the source variable resistance between the source of the PMOS transistor M3 Rs3_p (third example of the source variable resistor)

-Gate variable resistor Rg3_pn between the gate of the epitaxial transistor M3 and the drain of the NMOS transistor M2 (example of the third gate variable resistor)

- power supply potential source variable resistance between the Vcc source node _{N VCC} and the PMOS transistor M4 of Rs4_p (fourth example of the source variable resistor)

-Gate variable resistor Rg4_pn between the gate of the epitaxial transistor M4 and the drain of the NMOS transistor M1 (example of the fourth gate variable resistor)

The source variable resistors Rs1_n and Rs2_n and the gate variable resistors Rg1_n and Rg2_n are N-type variable resistors that exemplify an equivalent circuit in FIG. 11A. In the example of FIG. 11A, resistors Ra and Rb are provided in parallel between both ends T1 and T2 of the variable resistor (terminal T2 is a terminal on the high voltage side and terminal T1 is a terminal on the low voltage side), and one of the resistors is provided. A switch element SW is provided in series with Rb. The switch element SW can be configured by, for example, an NMOS transistor. The reason why the switch element SW is provided on the low voltage side in the N-type variable resistor is to make it possible to obtain a large _{gate-source voltage VGS when the switch element SW is on.}

The source variable resistors Rs3_p and Rs4_p are P-type variable resistors whose equivalent circuit is illustrated in FIG. 11 (b). In the example of FIG. 11B, resistors Ra and Rb are provided in parallel between both ends T1 and T2 of the variable resistor (terminal T2 is a terminal on the high voltage side and terminal T1 is a terminal on the low voltage side), and one of the resistors. A switch element SW is provided in series with Rb. The switch element SW can be configured by, for example, a epitaxial transistor. The reason why the switch element SW is provided on the high voltage side in the P-type variable resistor is to make it possible to obtain a large _{gate-source voltage VGS when the switch element SW is on.}

The drain variable resistors Rd1_pn and Rd2_pn and the gate variable resistors Rg3_pn and Rg4_pn are P / N type variable resistors whose equivalent circuits are illustrated in FIG. 11 (c). In the example of FIG. 11C, resistors Ra and Rb are provided in parallel between both ends T1 and T2 of the variable resistor (terminal T2 is a terminal on the high voltage side and terminal T1 is a terminal on the low voltage side), and one of the resistors is provided. Switch elements SW1 and SW2 are provided in series with Rb. The switch elements SW1 and SW2 can be composed of an NMOS transistor and a MPa transistor, respectively. The switch elements SW1 and SW2 are provided in the drain variable resistor and the gate variable resistor because the node in which the drain variable resistor and the gate variable resistor are set can be on either the low voltage side or the high voltage side.

In the variable resistor illustrated in FIG. 11, the conduction state of the switch element SW or the switch elements SW1 and SW2 is individually controlled by the control signal from the CPU 5, and the combined resistance value thereof is Ra or Ra · Rb / (Ra + Rb). ). In each variable resistor, the values of the resistors Ra and Rb may be set independently, but it is preferable that the resistor Ra not connected in series with the switch element has a relatively large value.

In the variable resistor illustrated in FIG. 11, an example in which two resistors are provided in parallel and a switch element is provided in series with one of the resistors is shown, but this is not the case. By providing three or more resistors in parallel and providing two or more switch elements, the variable resistance value (combined resistance value) can be set to an arbitrary value of the number of possible resistance values.

In the variable resistor illustrated in FIG. 11, the space between both ends T1 and T2 is not opened regardless of the state of the switch element, but the space between both ends T1 and T2 is set to be open depending on the state of the switch element. May be good. For example, as shown in FIG. 11, when two resistors are connected in parallel with each other, a switch element is provided in series with each resistor. Similarly, in the case of being composed of three or more resistors in parallel with each other, a switch element is provided in series with each resistor. As will be described later in the fifth embodiment, the output terminal can be in a floating state by configuring the P / N type variable resistor so as to be in an open state.

In the specific P / N type variable resistor shown in FIG. 12, the NMOS transistor m5 is provided as the switch element SW1, and the epitaxial transistor m6 is provided as the switch element SW2. In the P / N type variable resistor of FIG. 12, the level shift circuit 8 converts the switch control signals sw_off and sw_on (for example, GND level or 3.3V signal) from the CPU 5 into a signal that becomes the GND level or the power supply voltage Vcc (+ 12V). The level is converted and input to the gate of the NMOS transistor m5 and the epitaxial transistor m6. The circuit configuration of the level shift circuit 8 is the same as that of the level shift circuit 21 of FIG.

When the switch control signal sw_off is H level (3.3V) and the switch control signal sw_on is L level (GND level), both the NMOS transistor m5 and the PRIVATE transistor m6 are turned off, and the P / N type is variable. The resistance between the resistance terminals T1 and T2 is Ra. When the switch control signal sw_off is L level (GND level) and the switch control signal sw_on is H level (3.3 V), both the NMOS transistor m5 and the epitaxial transistor m6 are turned on, and the P / N type is variable. The resistance between the resistance terminals T1 and T2 is Ra · Rb / (Ra + Rb).

Since the switch control signals sw_off and sw_on usually have a fixed signal level initially set so as to have a desired resistance value, the operation of the level shift circuit 8 may be slow. Therefore, the drain resistors rd1 and rd2 of the level shift circuit 8 can be set to a large value, and the through current in the level shift circuit 8 can be suppressed.

In the example shown in FIG. 10, a level shift circuit 21B including all source variable resistors Rs1_n, Rs2_n, Rs3_p, Rs4_p, gate variable resistors Rg1_n, Rg2_n, Rg3_pn, Rg4_pn, and drain variable resistors Rd1_pn, Rd2_pn of each MOS transistor is shown. However, this is not the case, and at least one of these resistors may be provided with a variable resistor.

As described above, according to the drive circuit of the present embodiment, by providing variable resistances at the source, gate, and drain of each MOS transistor of the level shift circuit 21B, depending on the load (three-phase AC motor M). The optimum resistance value (that is, the resistance value that suppresses the through current and the drain current and does not deteriorate the responsiveness) can be obtained.

(4) Fourth embodiment

Next, the motor drive system of the fourth embodiment will be described with reference to FIG. The overall configuration of the motor drive system of this embodiment is the same as that shown in FIG. 1, and the gate drive circuit is different from that shown in FIG. FIG. 13 is a circuit diagram of the drive circuit of the fourth embodiment.

As shown in FIG. 2, in the drive circuit of FIG. 2, the dead time DT when the epitaxial transistor Q12 is turned from on to off and the NMOS transistor Q11 is turned from off to on, and the epitaxial transistor Q11 is turned from on to off to be epitaxial. This is the same as the dead time DT when the transistor Q12 goes from off to on. However, depending on the load, there are cases where it is desired to increase the dead time, and there are cases where it is desired to increase the dead time of either one.

Therefore, the drive circuit of the present embodiment shown in FIG. 13 is provided with level shift circuits independently for the NMOS transistor Q11 and the MPa transistor Q12.

That is, the level shift circuit 21C of the present embodiment includes a first level shift circuit 211 corresponding to the NMOS transistor Q11 and a second level shift circuit 212 corresponding to the epitaxial transistor Q12.

In the first level shift circuit 211, the potential of the gate of the NMOS transistor Q11 is set to the ground potential GND based on the potentials of the first input terminal P11 and the second input terminal P12 that fluctuate between the ground potential GND and 3.3 V. The signal is processed so as to fluctuate between the power supply potential _{VCC and the power supply potential.} The first level shift circuit 211 includes NMOS transistors M11, M21, polyclonal transistors M31, M41, and drain resistors Rd11, Rd21.

In the second level shift circuit 212, the potential of the gate of the epitaxial transistor Q12 is set to the ground potential GND based on the potentials of the third input terminal P13 and the fourth input terminal P14 that fluctuate between the ground potential GND and 3.3V. The signal is processed so as to fluctuate between the power supply potential _{VCC and the power supply potential.} The second level shift circuit 212 includes the NMOS transistors M12 and M22, the polyclonal transistors M32 and M42, and the drain resistors Rd12 and Rd22.

The operation of each of the first level shift circuit 211 and the second level shift circuit 212 is the same as that of the level shift circuit 21 of FIG.

In the first level shift circuit 211, the timing of turning the NMOS transistor Q11 from off to on and the timing of turning it from on to off are based on the pulse signals that are complementarily input to the first input terminal P11 and the second input terminal P12. The timing of becoming is determined. That is, when the first input terminal P11 is at H level and the second input terminal P12 is at L level, the NMOS transistor M11 is on, the NMOS transistor M21 is off, the epitaxial transistor M31 is off, and the epitaxial transistor M41 is on. Therefore, the NMOS transistor Q11 is turned on. On the other hand, when the first input terminal P11 is at L level and the second input terminal P12 is at H level, the NMOS transistor M11 is off, the NMOS transistor M21 is on, the epitaxial transistor M31 is on, and the epitaxial transistor M41 is off. Therefore, the NMOS transistor Q11 is turned off.

Further, in the second level shift circuit 212, the timing from off to on of the epitaxial transistor Q12 and on based on the pulse signals complementaryly input to the third input terminal P13 and the fourth input terminal P14. The timing to turn off is determined. That is, when the third input terminal P13 is at H level and the fourth input terminal P14 is at L level, the NMOS transistor M12 is on, the NMOS transistor M22 is off, the epitaxial transistor M32 is off, and the epitaxial transistor M42 is on. Therefore, the epitaxial transistor Q12 is turned off. On the other hand, when the third input terminal P13 is at the L level and the fourth input terminal P14 is at the H level, the NMOS transistor M12 is turned off, the NMOS transistor M22 is turned on, the epitaxial transistor M32 is turned on, and the PRIVATE transistor M42 is turned off. Therefore, the epitaxial transistor Q12 is turned on.

Therefore, in the drive circuit of the present embodiment, the timing of the level change of each signal of the first input terminal P11 and the second input terminal P12 and the timing of the level change of each signal of the third input terminal P13 and the fourth input terminal P14. By setting and individually, it is possible to independently set the dead times of the NMOS transistor Q11 and the epitaxial transistor Q12 to desired values.

(5) Fifth embodiment

Next, the motor drive system of the fifth embodiment will be described with reference to FIG. The overall configuration of the motor drive system of this embodiment is the same as that shown in FIG. 1, and the gate drive circuit is different from that shown in FIG. FIG. 14 is a circuit diagram of the drive circuit of the fifth embodiment.

The output terminal (node N11 in FIG. 1) may be in a floating state when the three-phase AC motor M is started, but the drive circuit shown in FIG. 2 cannot make the output terminal in a floating state. For example, in the drive circuit of FIG. 2, even if both the first input terminal P1 and the second input terminal P2 are at L level (GND level), the gate potentials of the NMOS transistor Q11 and the NMOS transistor Q12 are intermediate potentials of the power supply potential Vcc. Therefore, none of the MOS transistors are turned on and the output terminal is not in a floating state.

Therefore, the drive circuit of the present embodiment shown in FIG. 14 is configured so that the output terminal (node N11 in FIG. 1) is in a floating state when the three-phase AC motor M is started. The drive circuit shown in FIG. 14 is a level shift with respect to the drive circuit shown in FIG. 2 having a switch element composed of an NMOS transistor m5 and a MIMO transistor m6 between the drain of the NMOS transistor M2 and the gate of the MIMO transistor M3. Includes circuit 21D. This switch element controls the conduction state between the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3.

A level shift circuit 8 applied to the P / N type variable resistor shown in FIG. 12 is connected to each gate of the NMOS transistor m5 and the MIMO transistor m6. That is, the switch control signals sw_off and sw_on (for example, GND level or 3.3V signal) from the CPU 5 are level-converted to a signal that becomes the GND level or the power supply voltage Vcc (+ 12V) and used as the gate of the NMOS transistor m5 and the ProLiant transistor m6. input.

In the drive circuit of FIG. 14, when the three-phase AC motor M is started, the CPU 5 sets the switch control signals sw_off and sw_on to H level (3.3 V) and L level (GND level), respectively. Then, the gate of the NMOS transistor m5 becomes the GND level, and the gate of the MIMO transistor m6 becomes the power supply potential cc, so that both the NMOS transistor m5 and the MIMO transistor m6 are turned off. Therefore, a non-conducting state is established between the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3. At this time, by setting the signal levels given to the input terminals P1 and P2 from the CPU 5 to the H level (3.3 V; an example of the first potential), the node N11 which is the output terminal is in a floating state.

The operation of the motor drive system including the drive circuit of FIG. 14 is as follows.

When the three-phase AC motor M is started, the switch control signals sw_off and sw_on are set to H level and L level, respectively. As a result, a non-conducting state is established between the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3. In this state, both the input signals of the first input terminal P1 and the second input terminal P2 are set to H level. Then, the NMOS transistor M1 is turned on, the gate of the epitaxial transistor M4 is set to the GND level, and the epitaxial transistor M4 is turned on. Therefore, the epitaxial transistor Q12 is turned off. At this time, since the gate of the epitaxial transistor M3 becomes the power supply potential cc, the epitaxial transistor M3 is turned off.

On the other hand, since the input signal of the second input terminal P2 is H level, the NMOS transistor M2 is turned on, the gate potential of the NMOS transistor Q11 is set to GND level, and the NMOS transistor Q11 is turned off. At this time, the drain of the NMOS transistor M2 is at the GND level, but the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3 are in a non-conducting state, so that the OFF state of the epitaxial transistor M3 is maintained.

As described above, when the three-phase AC motor M is started, both the NMOS transistor Q11 and the epitaxial transistor Q12 are turned off, and the node N11, which is an output terminal, is in a floating state.

Next, by setting the switch control signals sw_off and sw_on to L level and H level, respectively, the gate of the NMOS transistor m5 becomes the power supply voltage Vcc, and the gate of the epitaxial transistor m6 becomes the GND level. Are both turned on. Therefore, the drain of the NMOS transistor M2 and the gate of the epitaxial transistor M3 are in a conductive state, and the operation is the same as that of the drive circuit of FIG.

As described above, according to the drive circuit of the present embodiment shown in FIG. 14, the output terminal can be in a floating state when the three-phase AC motor M is started.

The drive circuit capable of floating the output terminal when the three-phase AC motor M is started is not limited to FIG. 14, and can also be realized by the drive circuit shown in FIG. In the drive circuit of FIG. 13, when the three-phase AC motor M is started, the CPU 5 sets the first input terminal P11 to the L level (ground potential GND) and the second input terminal P12 to the H level (3.3 V). The setting is made, the third input terminal P13 is set to the H level (3.3V), and the fourth input terminal P14 is set to the L level (ground potential GND). In that case, as described above, both the NMOS transistor Q11 is turned off and the epitaxial transistor Q12 is turned off. Therefore, the output terminal is in a floating state.

Although the embodiment of the motor drive system of the present invention has been described in detail above, the scope of the present invention is not limited to the above embodiment. Further, the above-described embodiment can be improved or modified in various ways without departing from the spirit of the present invention.

For example, in the above-described embodiment, the case where the on / off control of each drive MOS transistor of the three-phase voltage generation unit 10 is performed by 120-degree energization based on the position information of the Hall sensor has been described, but this is not the case. .. As the on / off control method of each drive MOS transistor, another energization control method such as 180 degree energization may be applied.

Claims (6)

With a driving NMOS transistor and a driving ProLiant transistor with a common drain connected to the load,

Based on the potentials of the first input terminal and the second input terminal that fluctuate between the reference potential and the first potential higher than the reference potential, the gate potentials of the driving NMOS transistor and the driving MIMO transistor are determined. A level shift circuit that processes a signal so as to fluctuate between the reference potential and a second potential higher than the first potential, and

With

The source of the driving NMOS transistor is provided on the reference potential side, the source of the driving MIMO transistor is set to the second potential, and the source is set to the second potential.

The level shift circuit is

A first transistor which is an NMOS transistor having a first source set to the reference potential, a first gate connected to the first input terminal, and a first drain.

A second NMOS transistor having a second source set at the reference potential, a second gate connected to the second input terminal, and a second drain connected to the gate of the driving NMOS transistor. Transistor and

A third transistor, which is a epitaxial transistor having a third source set to the second potential, a third gate, and a third drain connected to the first drain,

A fourth transistor, which is a epitaxial transistor, has a fourth source set to the second potential, a fourth gate, and a fourth drain connected to the second drain and the gate of the driving photodiode.

The first drain and the fourth gate are connected, and the second drain and the third gate are connected.

A pulse signal complementary to each other is input to the first input terminal and the second input terminal, and in the pulse signal, both the first input terminal and the second input terminal have the reference potential when the signal level is switched. The period is set,

Drive circuit.
The level shift circuit is

A first drain resistor is provided between the first drain and the third drain, and a second drain resistor is provided between the second drain and the fourth drain.

The drive circuit according to claim 1.
The level shift circuit is

A first source resistor between the reference potential node and the first source,

A first gate resistor between the first input terminal and the first gate,

A second source resistor between the reference potential node and the second source,

A second gate resistor between the second input terminal and the second gate,

A third source resistor between the second potential node and the third source,

A third gate resistor between the third gate and the second drain,

A fourth source resistor between the second potential node and the fourth source, and

It has at least one of the fourth gate resistors between the fourth gate and the first drain.

The drive circuit according to claim 1 or 2.
The level shift circuit is

A first drain variable resistor between the first drain and the third drain,

A second drain variable resistor between the second drain and the fourth drain,

A first source variable resistor between the reference potential node and the first source,

A first gate variable resistor between the first input terminal and the first gate,

A second source variable resistor between the reference potential node and the second source,

A second gate variable resistor between the second input terminal and the second gate,

A third source variable resistor between the second potential node and the third source,

A third gate variable resistor between the third gate and the second drain,

A fourth source variable resistor between the second potential node and the fourth source, and

Of the 4th gate variable resistance between the 4th gate and the 1st drain, at least

With any one variable resistor,

The drive circuit according to claim 1.
The at least one variable resistor includes a switch element, and by controlling the switch element, it is set to any resistance value from a plurality of resistance values.

The drive circuit according to claim 4.
The drive circuit according to any one of claims 1 to 5.

With a microcontroller,

A drive system in which the potentials of the first input terminal and the second input terminal are set by the microcontroller.

Images