JPWO2020014424A5 - - Google Patents
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Claims (20)
第１の入力端子と第２の入力端子と制御端子と第１の出力端子と第２の出力端子とを含 む第１の比較交換回路であって、
前記第１の入力端子において第１のデータ値を受信し、
前記第２の入力端子において第２のデータ値を受信し、
前記制御端子において制御信号を受信し、
前記制御信号が第１の値を有すると判定することに応答して、前記第２の出力端子にお いて前記第１のデータ値を出力し、前記第１の出力端子において前記第２のデータ値を出 力し、
前記制御信号が第２の値を有すると判定することに応答して、前記第１の出力端子にお いて前記第１のデータ値と前記第２のデータ値との大きいものを出力し、前記第２の出力 端子において前記第１のデータ値と前記第２のデータ値との小さいものを出力し、
前記制御信号が第３の値を有すると判定することに応答して、前記第１の出力端子にお いて前記第１のデータ値と前記第２のデータ値との小さいものを出力し、前記第２の出力 端子において前記第１のデータ値と前記第２のデータ値との大きいものを出力する、
ように構成される、前記第１の比較変換回路と、
前記第１の比較交換回路の第１の出力端子に結合される入力端子と前記第１の比較変換 回路の第１の入力端子に結合される出力端子とを含む先入れ先出し（ＦＩＦＯ）バッファと、
を含む、ハードウェアアクセラレータ。a hardware accelerator,
A first comparison and exchange circuit including a first input terminal, a second input terminal, a control terminal, a first output terminal, and a second output terminal ,
receiving a first data value at the first input terminal;
receiving a second data value at the second input terminal;
receiving a control signal at the control terminal;
outputting the first data value at the second output terminal and the second data at the first output terminal in response to determining that the control signal has a first value; prints the value ,
outputting the greater of the first data value and the second data value at the first output terminal in response to determining that the control signal has a second value ; outputting the smaller of the first data value and the second data value at a second output terminal;
outputting the lesser of the first data value and the second data value at the first output terminal in response to determining that the control signal has a third value ; outputting the greater of said first data value and said second data value at a second output terminal;
the first comparison conversion circuit configured as;
a first-in first-out (FIFO) buffer including an input terminal coupled to the first output terminal of the first comparison and exchange circuit and an output terminal coupled to the first input terminal of the first comparison and conversion circuit ;
hardware accelerators, including
前記第１の比較交換回路の第２の入力端子に結合される第２の比較変換回路と、
前記第１の比較交換回路の第２の出力端子に結合される第３の比較変換回路と、
を更に含む、ハードウェアアクセラレータ。A hardware accelerator according to claim 1,
a second comparison/conversion circuit coupled to a second input terminal of the first comparison/exchange circuit;
a third comparator/converter circuit coupled to a second output terminal of the first comparator/exchange circuit;
A hardware accelerator, further comprising:
第１の入力端子と第２の入力端子と制御端子と第１の出力端子と第２の出力端子とを含 む第２の比較交換回路と、
メモリと、
前記第２の比較交換回路の第２の出力端子に結合される第１の入力端子と、前記メモリに結合される第２の入力端子と、前記第１の比較交換回路の第１の入力端子に結合される出力端子とを含むマルチプレクサ（ｍｕｘ）と、
を更に含む、ハードウェアアクセラレータ。A hardware accelerator according to claim 1,
a second comparison and exchange circuit including a first input terminal, a second input terminal, a control terminal, a first output terminal and a second output terminal ;
memory ;
a first input terminal coupled to a second output terminal of said second compare and switch circuit; a second input terminal coupled to said memory; and a first input terminal of said first compare and switch circuit. an output terminal coupled to a multiplexer (mux) ;
A hardware accelerator, further comprising:
前記第２の比較交換回路の第２の出力端子が前記メモリに結合される、ハードウェアアクセラレータ。A hardware accelerator according to claim 3 ,
A hardware accelerator, wherein a second output terminal of said second compare and exchange circuit is coupled to said memory.
第１の反復において、前記ｍｕｘが、データ値のＮ要素ベクトルを前記メモリからシリアルに受信し、前記第１の比較交換回路の第２の入力端子に提供するように構成される、ハードウェアアクセラレータ。A hardware accelerator according to claim 3 ,
A hardware accelerator, wherein in a first iteration, the mux is configured to serially receive an N-element vector of data values from the memory and provide it to a second input terminal of the first compare-and-swap circuit. .
後続の反復において、前記ｍｕｘが、前記第２の比較交換回路の第２の出力端子を前記第１の比較交換回路の第２の入力端子に結合するように更に構成される、ハードウェアアクセラレータ。A hardware accelerator according to claim 5 ,
In subsequent iterations, the mux is further configured to couple a second output terminal of the second compare and switch circuit to a second input terminal of the first compare and switch circuit.
制御信号を含む制御信号バッファを更に含み、
前記制御信号が、前記第１及び第２の比較交換回路に提供されると、前記第１及び第２ の比較交換回路に、第１の反復又は一連の反復の間に前記Ｎ要素ベクトルをバイトニックシーケンスに配置させ、最終反復の間に前記Ｎ要素ベクトルを完全にソートされたアレイに配置させる、ハードウェアアクセラレータ。A hardware accelerator according to claim 6 ,
further comprising a control signal buffer containing the control signal;
The control signal is provided to the first and second compare and switch circuits to cause the first and second compare and switch circuits to byte the N-element vector during a first iteration or series of iterations. A hardware accelerator that places the N-element vector into a fully sorted array during the final iteration.
前記第２の入力端子に結合されるメモリと、a memory coupled to the second input terminal;
前記第２の出力端子に結合される第２の比較交換回路と、a second comparison and exchange circuit coupled to the second output terminal;
を更に含む、ハードウェアアクサラレータ。A hardware accelerator, further comprising:
前記第２の入力端子に結合される第２の比較交換回路と、a second comparison and exchange circuit coupled to the second input terminal;
前記第２の出力端子に結合されるメモリと、a memory coupled to the second output terminal;
を更に含む、ハードウェアアクセラレータ。A hardware accelerator, further comprising:
４つのマルチプレクサ（ｍｕｘ）であって、各々が、出力端子と、メモリに結合されるように適合される第１の入力端子と、第２の入力端子とを含む、前記４つのマルチプレクサ（ｍｕｘ）と、
４つの入力端子と４つの出力端子とを含む比較交換回路と、
第１のソーティングアクセラレータと第２のソーティングアクセラレータと第３のソーティングアクセラレータと第４のソーティングアクセラレータとを含む４つのソーティン グアクセラレータであって、前記４つのソーティングアクセラレータの各々が入力端子と出力端子とを含む、前記４つのソーティングアクセラレータと、
を含み、
各ｍｕｘの出力端子が前記比較返還回路の入力端子の１つに結合され、
前記比較交換回路の各出力端子が前記４つのソーティングアクセラレータの入力端子の１つに結合され、
各ソーティングアクセラレータの出力端子が前記４つのｍｕｘの１つの第２の入力端子に結合される、ハードウェアアクセラレータ。a hardware accelerator,
four multiplexers (muxes), each including an output terminal, a first input terminal adapted to be coupled to a memory, and a second input terminal and
a comparison and exchange circuit including four input terminals and four output terminals ;
four sorting accelerators including a first sorting accelerator, a second sorting accelerator, a third sorting accelerator and a fourth sorting accelerator, each of the four sorting accelerators input the four sorting accelerators comprising a terminal and an output terminal ;
including
an output terminal of each mux being coupled to one of the input terminals of the compare-and-return circuit;
each output terminal of the compare and exchange circuit is coupled to one of the input terminals of the four sorting accelerators;
A hardware accelerator, wherein an output terminal of each sorting accelerator is coupled to a second input terminal of one of said four muxes.
前記比較交換回路が、
各々が第１及び第２の入力端子と第１及び第２の出力端子とを含む第１及び第２の２入力比較交換回路であって、前記第１の２入力比較交換回路の第１の入力端子が前記４つの ｍｕｘの第１のｍｕｘの出力端子に結合され、前記第１の２入力比較交換回路の第２の入力端子が前記４つのｍｕｘの第２のｍｕｘの出力端子に結合され、前記第２の２入力比較交換回路の第１の入力端子が前記４つのｍｕｘの第３のｍｕｘの出力端子に結合され、前記第２の２入力比較交換回路の第２の入力端子が前記４つのｍｕｘの第４のｍｕｘの出力端子に結合される、前記第１及び第２の２入力比較交換回路と、
各々が第１及び第２の入力端子と第１及び第２の出力端子とを含む第３及び第４の２入力比較交換回路であって、前記第３の２入力比較交換回路の第１の入力端子が前記第１の２入力比較交換回路の第１の出力端子に結合され、前記第３の２入力比較交換回路の第２の入力端子が前記第２の２入力比較交換回路の第１の出力端子に結合され、前記第４の２入力比較交換回路の第１の入力端子が前記第１の２入力比較交換回路の第２の出力端子に結合され、前記第４の２入力比較交換回路の第２の入力端子が前記第２の２入力比較交換回路の第２の出力端子に結合され、前記第３の２入力比較交換回路の第１の出力端子が前記第１のソーティングアクセラレータの入力端子に結合され、前記第３の２入力比較交換回路の第２の出力端子が前記第２のソーティングアクセラレータの入力端子に結合され、前記第４の２入力比較交換回路の第１の出力端子が前記第３のソーティングアクセラレータの入力端子に結合され、前記第４の２入力比較交換回路の第２の出力端子が前記第４のソーティングアクセラレータの入力端子に結合される、前記第３及び第４の２入力比較交 換回路と、
を更に含む、ハードウェアアクセラレータ。A hardware accelerator according to claim 10 ,
The comparison and exchange circuit is
First and second two-input compare-and-swap circuits each including first and second input terminals and first and second output terminals , wherein the first an input terminal coupled to an output terminal of a first mux of said four muxes and a second input terminal of said first two-input compare and switch circuit coupled to an output terminal of a second mux of said four muxes; , a first input terminal of said second two-input compare-and-exchange circuit is coupled to an output terminal of a third of said four muxes, and a second input terminal of said second two-input compare-and-exchange circuit is coupled to said said first and second two-input compare and switch circuits coupled to the output terminals of a fourth mux of the four muxes;
third and fourth two-input compare-and-swap circuits each including first and second input terminals and first and second output terminals , wherein the first An input terminal is coupled to a first output terminal of said first two-input compare-and-switch circuit, and a second input terminal of said third two-input compare-and-switch circuit is coupled to a first output terminal of said second two-input compare-and-switch circuit. and a first input terminal of said fourth two-input compare-exchange circuit is coupled to a second output terminal of said first two-input compare-exchange circuit, said fourth two-input compare-exchange circuit A second input terminal of a circuit is coupled to a second output terminal of said second two-input compare-and-switch circuit, and a first output terminal of said third two-input compare-and-switch circuit is coupled to said first sorting accelerator. a second output terminal of said third two-input compare-and-swap circuit coupled to an input terminal of said second sorting accelerator, and a first terminal of said fourth two-input compare-and-switch circuit; The output terminal is coupled to the input terminal of the third sorting accelerator, and the second output terminal of the fourth two-input comparison and switching circuit is coupled to the input terminal of the fourth sorting accelerator . third and fourth two-input comparison and switching circuits;
A hardware accelerator , further comprising:
前記第１のソーティングアクセラレータの出力端子が前記４つのｍｕｘの第４のｍｕｘの第２の入力端子に結合され、
前記第２のソーティングアクセラレータの出力端子が前記４つのｍｕｘの第２のｍｕｘの第２の入力端子に結合され、
前記第３のソーティングアクセラレータの出力端子が前記４つのｍｕｘの第３のｍｕｘの第２の入力端子に結合され、
前記第４のソーティングアクセラレータの出力端子が前記４つのｍｕｘの第１のｍｕｘの第２の入力端子に結合される、ハードウェアアクセラレータ。A hardware accelerator according to claim 10 ,
an output terminal of the first sorting accelerator is coupled to a second input terminal of a fourth mux of the four muxes;
an output terminal of the second sorting accelerator is coupled to a second input terminal of a second mux of the four muxes ;
an output terminal of the third sorting accelerator is coupled to a second input terminal of a third mux of the four muxes ;
A hardware accelerator, wherein the output terminal of the fourth sorting accelerator is coupled to the second input terminal of the first of the four muxes .
各ソーティングアクセラレータが、
複数の２入力比較交換回路と、
前記複数の２入力比較交換回路の各々に関連する先入れ先出し（ＦＩＦＯ）バッファで あって、各ＦＩＦＯバッファの出力がＦＩＦＯデータ値である、前記ＦＩＦＯバッファと、
前記複数の２入力比較交換回路が、
第１の動作モードにおいて、前の２入力比較交換回路又は前記比較交換回路からの前のデータ値を関連するＦＩＦＯバッファに記憶し、関連するＦＩＦＯバッファからのＦＩＦＯデータ値を後続の２入力比較交換回路、前記４つのｍｕｘの１つ、又は前記メモリに渡し、
第２の動作モードにおいて、前記前のデータ値を前記ＦＩＦＯデータ値と比較し、前記データ値の大きいものを関連するＦＩＦＯバッファに記憶し、前記データ値の小さいものを前記後続の２入力比較交換回路、前記４つのｍｕｘの１つ、又は前記メモリに渡し、
第３の動作モードにおいて、前記前のデータ値を前記ＦＩＦＯデータ値と比較し、前記 データ値の小さいものをその関連するＦＩＦＯバッファに記憶し、前記データ値の大きいものを前記後続の２入力比較交換回路、前記４つのｍｕｘの１つ、又は前記メモリに渡す、
ように構成される、ハードウェアアクセラレータ。A hardware accelerator according to claim 10 ,
Each sorting accelerator
a plurality of two-input comparison and exchange circuits;
a first-in first-out (FIFO) buffer associated with each of said plurality of two-input compare and switch circuits , wherein the output of each FIFO buffer is a FIFO data value;
The plurality of 2-input comparison and exchange circuits,
In a first mode of operation, a previous data value from a previous two-input compare-and-switch circuit or said compare-and-switch circuit is stored in an associated FIFO buffer, and a FIFO data value from the associated FIFO buffer is stored in a subsequent two-input compare-and-switch circuit. passing to a circuit, one of the four muxes, or the memory;
In a second mode of operation, comparing said previous data value with said FIFO data value, storing said larger data value in an associated FIFO buffer, and storing said smaller data value in said subsequent two-input compare exchange. passing to a circuit, one of the four muxes, or the memory;
In a third mode of operation, the previous data value is compared to the FIFO data value, the lower data value is stored in its associated FIFO buffer, and the higher data value is stored in the subsequent two data values. pass to an input compare and switch circuit, one of the four muxes, or the memory ;
A hardware accelerator that is configured to:
前記複数の２入力比較交換回路の各々が、
関連するＦＩＦＯバッファの出力端子に結合される第１の入力端子と、
関連するＦＩＦＯバッファの入力端子に結合される第１の出力端子と、
前記前の２入力比較交換回路の第２の出力端子又は前記比較交換回路の出力端子に結合される第２の入力端子と、
後続の２入力比較交換回路の第２の入力端子、前記４つのｍｕｘの１つ、又は前記メモリに結合される第２の出力端子と、
を含む、ハードウェアアクセラレータ。14. The hardware accelerator of claim 13 ,
Each of the plurality of two-input comparison and exchange circuits,
a first input terminal coupled to the output terminal of the associated FIFO buffer;
a first output terminal coupled to an input terminal of an associated FIFO buffer;
a second input terminal coupled to a second output terminal of the previous two-input compare and switch circuit or to an output terminal of the compare and switch circuit;
a second output terminal coupled to a second input terminal of a subsequent two-input compare and switch circuit, one of the four muxes, or the memory;
hardware accelerators, including
前記複数の２入力比較交換回路の各々が制御信号を受信するように更に構成され、
前記受信された制御信号が、前記２入力比較交換回路を前記第１、第２及び第３の動作モードの１つで動作させる、ハードウェアアクセラレータ。14. The hardware accelerator of claim 13 ,
each of the plurality of two-input compare and switch circuits is further configured to receive a control signal;
A hardware accelerator, wherein the received control signal causes the two-input compare and switch circuit to operate in one of the first, second and third modes of operation.
第１の反復において、前記４つのｍｕｘの各々が、データ値のＮ／４要素ベクトルを前記メモリからシリアルに受信し、前記比較交換回路の入力端子に提供するように構成される、ハードウェアアクセラレータ。14. The hardware accelerator of claim 13 ,
In a first iteration, each of said four muxes is configured to serially receive an N/4 element vector of data values from said memory and provide it to an input terminal of said compare-and-swap circuit. .
後続の反復において、前記４つのｍｕｘの各々が、前記４つのソーティングアクセラレータの出力端子の１つを前記比較交換回路の入力端子の１つに結合するように更に構成される、ハードウェアアクセラレータ。17. The hardware accelerator of claim 16 ,
A hardware accelerator, wherein in subsequent iterations, each of said four muxes is further configured to couple one of said four sorting accelerator output terminals to one of said compare and exchange circuit input terminals .
制御信号を含む制御信号バッファを更に含み、
前記制御信号が、前記比較交換回路と前記４つのソーティングアクセラレータの前記複 数の２入力比較交換回路とに提供されると、前記ハードウェアアクセラレータに、第１の反復又は一連の反復の間に前記Ｎ／４要素ベクトルをバイトニックシーケンスに配置させ、最終反復の間に前記Ｎ／４要素ベクトルを完全にソートされたアレイに配置させる、ハードウェアアクセラレータ。17. The hardware accelerator of claim 16 ,
further comprising a control signal buffer containing the control signal;
When the control signal is provided to the compare -and-swap circuit and the plurality of two-input compare-and-swap circuits of the four sorting accelerators, to the hardware accelerator during a first iteration or series of iterations: A hardware accelerator that arranges the N/4 element vector into a bitonic sequence and arranges the N/4 element vector into a fully sorted array during the final iteration.
比較交換回路によって制御信号を制御端子で受信することと、
前記比較交換回路によって第１のデータ値を第１の入力端子で受信することと、
前記比較交換回路によって第２のデータ値を第２の入力端子で受信することと、
前記制御信号が第１の値を有すると判定することに応答して、前記比較交換回路によって前記第１のデータ値を第１の出力端子に出力し、前記比較交換回路によって前記第２の データ値を第２の出力端子に出力することと、
前記制御信号が第２の値を有すると判定することに応答して、前記比較交換回路によっ て前記第１のデータ値と前記第２のデータ値との大きいものを前記第１の出力端子に出力 し、前記比較交換回路によって前記第１のデータ値と前記第２のデータ値との小さいものを前記第２の出力端子に出力することと、
前記制御信号が第３の値を有すると判定することに応答して、前記比較交換回路によっ て前記第１のデータ値と前記第２のデータ値との小さいものを前記第１の出力端子に出力 し、前記後続の比較交換回路によって前記第１のデータ値と前記第２のデータ値との大き いものを前記第２の出力端子に出力することと、
を含む、方法。a method,
Receiving a control signal at a control terminal by the comparison and exchange circuit ;
receiving a first data value at a first input terminal by the compare and exchange circuit;
receiving a second data value at a second input terminal by the compare and exchange circuit;
responsive to determining that the control signal has a first value, outputting the first data value to a first output terminal by the compare and switch circuit; outputting the value to a second output terminal ;
In response to determining that the control signal has the second value, the compare and switch circuit outputs the greater of the first data value and the second data value to the first output terminal. and outputting the smaller one of the first data value and the second data value to the second output terminal by the comparison exchange circuit ;
Outputting the lesser of the first data value and the second data value by the compare and switch circuit to the first output in response to determining that the control signal has a third value. terminals, and outputting the greater of said first data value and said second data value to said second output terminal by said subsequent compare and exchange circuit;
A method, including
前記比較交換回路を含む複数の比較交換回路に制御信号を提供することと、
前記複数の比較交換回路が、第１の反復又は一連の反復の間にＮ要素ベクトルをバイトニックシーケンスに配置させ、最終反復の間にＮ要素ベクトルを完全にソートされたアレイに配置させる、ように命令することと、
を更に含む、方法。20. The method of claim 19 , wherein
providing control signals to a plurality of compare and switch circuits including the compare and switch circuit;
wherein the plurality of compare-and-swap circuits arrange the N-element vectors into a bitonic sequence during a first iteration or series of iterations, and arrange the N-element vectors into a fully sorted array during a final iteration ; to command the
The method further comprising :
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| US16/237,447 US10901692B2 (en) | 2018-07-12 | 2018-12-31 | Bitonic sorting accelerator |
| PCT/US2019/041315 WO2020014424A1 (en) | 2018-07-12 | 2019-07-11 | Bitonic sorting accelerator |
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| US20220222510A1 (en) * | 2021-01-13 | 2022-07-14 | Apple Inc. | Multi-operational modes of neural engine circuit |
| JP2022117853A (en) * | 2021-02-01 | 2022-08-12 | パナソニックＩｐマネジメント株式会社 | Diagnostic circuit, electronic device and diagnostic method |
| US11593106B1 (en) * | 2021-09-24 | 2023-02-28 | Apple Inc. | Circuits and methods for vector sorting in a microprocessor |
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| US4567572A (en) | 1983-02-22 | 1986-01-28 | The United States Of America As Represented By The Director Of The National Security Agency | Fast parallel sorting processor |
| US5179717A (en) * | 1988-11-16 | 1993-01-12 | Manco, Ltd. | Sorting circuit using first and last buffer memories addressed by reference axis data and chain buffer memory addressed by datum number of the first and last buffer memories |
| US5206947A (en) * | 1989-06-30 | 1993-04-27 | Digital Equipment Corporation | Stable sorting for a sort accelerator |
| JP3518034B2 (en) * | 1995-03-30 | 2004-04-12 | 三菱電機株式会社 | Sorting method, sort processing device, and data processing device |
| US6088353A (en) | 1997-07-08 | 2000-07-11 | Lucent Technologies, Inc. | Sorting networks having reduced-area layouts |
| US9558903B2 (en) | 2012-05-02 | 2017-01-31 | National Instruments Corporation | MEMS-based switching system |
| US20160283549A1 (en) | 2015-03-27 | 2016-09-29 | Intel Corporation | Value sorter |
| US10102180B2 (en) | 2015-11-25 | 2018-10-16 | Hitachi, Ltd. | Majority circuit |
| WO2018089993A1 (en) * | 2016-11-14 | 2018-05-17 | Google Llc | Sorting for data-parallel computing devices |
| US10809978B2 (en) * | 2017-06-02 | 2020-10-20 | Texas Instruments Incorporated | Merge sort accelerator |
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