JPWO2020003559A1 - Light emitting element drive device - Google Patents

Abstract

The drive control unit includes a first external terminal connected to a control terminal of the switching element and a drive control unit that generates a drive signal for on / off driving the switching element and outputs the drive signal from the first external terminal. It is a light emitting element drive device having a coil current correction unit that corrects the coil current by adjusting the drive signal based on the delay of the turn-back timing at which the coil current flowing through the coil changes from increasing to decreasing.

Description

The present invention relates to a light emitting element driving device.

Conventionally, various light emitting element driving devices for driving a light emitting element represented by an LED (light emitting diode) have been proposed. Outside of a conventional light emitting element driving device that drives an LED, which is an example of a light emitting element, a coil and a switching element are sequentially connected to a low potential side end (cathode) of an LED array configured by connecting a plurality of LEDs in series. A diode is connected in parallel between both ends of the LED array, and a diode for free circulation is connected between both ends of the connection configuration between the capacitor and the coil.

By controlling the switching element on and off, the LED current flowing through the LED array is controlled. When the switching element is turned on, the current flowing through the coil increases, and when the switching element is turned off, the current flowing through the coil and the diode decreases. The capacitor averages the current flowing through the coil to obtain the LED current.

An example of such a conventional light emitting element driving device is disclosed in Patent Document 1.

Japanese Unexamined Patent Publication No. 2016-991781

In the conventional light emitting element driving device, the current flowing through the coil (coil current) changes from an increase to a decrease when the switching element is turned from the on state to the off state. However, for example, due to a delay in switching the control voltage applied to the control terminal to the off level due to an external resistance component or the like connected between the output terminal of the light emitting element drive device and the control terminal of the switching element. Therefore, there is a risk that the turnaround timing at which the coil current changes from an increase to a decrease may be delayed. In this case, the coil current continues to increase by the delay, and the value of the LED current obtained by averaging the coil current becomes higher than the desired value, which causes a problem in accuracy.

In view of the above problems, an object of the present invention is to provide a light emitting element driving device capable of improving the accuracy of the current flowing through the light emitting element.

In order to achieve the above object, the present invention comprises at least one light emitting element, and a light emitting unit to which an input voltage is applied to one end thereof.
A coil whose one end is connected to the other end of the light emitting portion,
A diode connected between the other end of the coil and one end of the light emitting portion,
A switching element having a first terminal connected to the other end of the coil,
A light emitting element driving device for driving the light emitting unit in an external configuration including the above.
A first external terminal connected to the control terminal of the switching element,
A drive control unit that generates a drive signal that drives the switching element on and off and outputs it from the first external terminal.
With
The drive control unit has a coil current correction unit that corrects the coil current by adjusting the drive signal based on the delay of the turn-back timing at which the coil current flowing through the coil changes from increasing to decreasing.

Further, another aspect of the present invention includes a light emitting unit composed of at least one light emitting element and to which an input voltage is applied to one end.
A coil whose one end is connected to the other end of the light emitting portion,
A diode connected between the other end of the coil and one end of the light emitting portion,
A switching element having a first terminal connected to the other end of the coil,
A light emitting element driving device for driving the light emitting unit in an external configuration including the above.
A first external terminal connected to the control terminal of the switching element,
A drive control unit that generates a drive signal that drives the switching element on and off and outputs it from the first external terminal.
The second external terminal to which the selection input signal is input and
With
The drive control unit is configured to operate by switching between a QR mode (quasi-resonant: pseudo-resonant method) and a CCM mode (continuous current mode: continuous current mode) according to the selection input signal.

According to the light emitting element driving device of the present invention, the accuracy of the current flowing through the light emitting element can be improved.

It is a circuit diagram which shows the whole structure of the light emitting element drive device which concerns on one Embodiment of this invention. It is a figure which shows an example of the waveform of the coil current and LED current in a QR mode. It is a figure which shows an example of the waveform of the coil current and LED current in CCM mode. It is a timing chart for demonstrating the LED current correction function in the QR mode. It is the figure which extracted only the configuration about the current feedback control in the CCM mode in the light emitting element drive apparatus shown in FIG. It is a figure which shows the light emitting element drive device which carried the LED current correction function in the CCM mode. FIG. 5 is a timing chart showing an example of various signal waveforms in the CCM mode in the configuration shown in FIG. 5 (FIG. 1). 6 is a timing chart showing an example of various signal waveforms in the CCM mode in the configuration shown in FIG. It is a figure which looked at the light emitting element drive device which concerns on one Embodiment from the top surface as an IC package product. It is a top view which shows the arrangement structure in the chip provided in the light emitting element drive device which concerns on one Embodiment. It is a figure which shows the structural example of the liquid crystal display device.

An embodiment of the present invention will be described below with reference to the drawings.

<1. Overall configuration of light emitting element drive device>
FIG. 1 is a circuit diagram showing an overall configuration of a light emitting element driving device according to an embodiment of the present invention. The light emitting element driving device 1 shown in FIG. 1 is a device that drives an LED array 50 configured by connecting a plurality of LEDs in series. That is, the light emitting element driving device 1 is a device that drives an LED as an example of a light emitting element to be driven. However, the light emitting element to be driven does not have to be limited to the LED.

Further, the light emitting element driving device 1 according to the present embodiment can be operated by switching between the QR mode (quasi-resonant: pseudo-resonant method) and the CCM mode (continuous current mode: continuous current mode). ing. That is, both modes are mounted on one IC. Details of both modes will be described later.

As shown in FIG. 1, the light emitting element driving device 1 includes an internal voltage generation unit 11, an IC power supply UVLO unit 12, a UVLO unit 13, an internal voltage UVLO unit 14, a low-pass filter 15, an amplifier 16, and an ODP. Each configuration includes an (Over Duty Protection) unit 17, a comparison voltage generation unit 18, a comparator 19, an error amplifier 20, a comparator 21, an oscillator 22, an abnormality detection unit 23, and a control logic unit 24. It is a semiconductor IC configured by integrating parts.

An example of a drive control unit is composed of a comparator 19, an error amplifier 20, a comparator 21, an oscillator 22, a control logic unit 24, a driver Dr1, and a comparator CP2. The drive control unit generates a gate output signal Gout (drive signal) output from the OUT terminal.

Further, the light emitting element driving device 1 has a VCS terminal, a ULVO terminal, a SEL terminal, a REG90 terminal, a QRCOMP terminal, a PWM terminal, a DUTYON terminal, an ADIM terminal, and an RT terminal as external terminals for establishing an electrical connection with the outside. , FAILB terminal, ZT terminal, OUT terminal, CS terminal, FB terminal, DGND terminal, and GND terminal.

External components such as voltage dividing resistors R1 and R2, diodes D1, capacitors C1, coils L1, LED array 50, capacitors C2, and voltage dividing resistors R11, are external to the light emitting element drive device 1, respectively. R12, a switching element M1, a gate resistor Rg, a current detection resistor Rs, a feedback capacitor Cfb, a capacitor C11, and a resistor R21 are arranged.

The LED array 50 is a light emitting unit configured by connecting a plurality of LEDs in series. However, in addition, for example, LEDs may be connected in series and parallel to form an LED array, or a single LED may be used instead of the LED array.

An input voltage Vin is applied to the high potential side end (anode) of the LED array 50. One end of the coil L1 is connected to the low potential side end (cathode) of the LED array 50. The anode of the freewheeling diode D1 is connected to the other end of the coil L1. The high potential side end of the LED array 50 is connected to the cathode of the diode D1. A capacitor C1 is connected in parallel between both ends of the LED array 50. The capacitor C1 averages the coil current Icoil, which is the current flowing through the coil L1, to obtain the LED current ILED, which is the current flowing through the LED array 50.

As an example, a drain of a switching element M1 composed of an n-channel MOSFET is connected to the other end of the coil L1. An application end of the ground potential is connected to the source of the switching element M1 via a current detection resistor Rs.

A voltage after dividing the input voltage Vin by the voltage dividing resistors R1 and R2 is applied to the UVLO (Under Voltage Lock Out) terminal. When the voltage applied to the UVLO terminal falls below a predetermined voltage, the UVLO unit 13 keeps the switching element M1 off in the control logic unit 24 to stop switching. That is, the UVLO terminal is a terminal for UVLO of the application power supply.

A power supply voltage Vcc is applied to the VCS terminal. That is, the VCS terminal is a power supply terminal for an IC. The IC power supply UVLO unit 12 causes the control logic unit 24 to shut down the IC when the power supply voltage Vcc falls below a predetermined voltage.

The internal voltage generation unit 11 generates an internal voltage Vreg based on the power supply voltage Vcc. The generated internal voltage Vreg can be output to the outside from the REG90 terminal. The REG90 terminal is a 9.0V output terminal. However, the output voltage value here is an example. An external capacitor C11 is connected to the REG90 terminal. The capacitor C11 is preferably a ceramic capacitor.

The internal voltage UVLO unit 14 causes the control logic unit 24 to shut down the IC when the internal voltage Vreg falls below a predetermined voltage.

The control logic unit 24 outputs the gate output signal Gout from the OUT terminal to the outside by using the driver Dr1. The gate output signal Gout is a pulse signal composed of High and Low. The OUT terminal is connected to the gate (control terminal) of the switching element M1 via a gate resistor Rg which is an external component. The gate output signal Gout is applied to the gate of the switching element M1 as a gate signal Gt via the gate resistor Rg. The switching element M1 is turned on and off by the gate output signal Gout.

A pulsed PWM dimming signal is input to the PWM terminal from the outside. The ODP unit 17 switches whether or not to activate the PWM on time limiting function according to the on / off setting signal input from the outside via the DUTYON terminal. For example, when the on / off setting signal is Low, the on time of the PWM dimming signal is limited, and when the on / off setting signal is High, the PWM on time limiting function is turned off.

The control logic unit 24 outputs a gate output signal Gout for on / off from the OUT terminal during the period when the PWM dimming signal output from the ODP unit 17 is High, and maintains the gate output signal Gout at Low during the period of Low. Thereby, the LED array 50 can be dimmed by adjusting the on-duty of the PWM dimming signal.

The SEL terminal is a terminal to which a selection input signal for selecting whether to operate the light emitting element driving device 1 in the QR mode or the CCM mode is input. The SEL terminal is pulled down by the pull-down resistor Rp inside the IC. The connection node between the SEL terminal and the pull-down resistor Rp is connected to the non-inverting input end of the comparator CP1. A predetermined reference voltage is applied to the inverting input end of the comparator CP1. Depending on whether the selection input signal is High or Low, the High or Low selection signal SEL_sig is output from the comparator CP1.

The control logic unit 24 selects the QR mode or the CCM mode according to the level of the input selection signal SEL_sig. For example, when the selection input signal is High, the QR mode is selected, and when the selection input signal is Low, the CCM mode is selected.

The CS terminal and the comparator 19 are used for current detection in the QR mode. The CS terminal is connected to a connection node between the switching element M1 and the current detection resistor Rs. At the non-inverting input end of the comparator 19, the current detection signal Vcs after the coil current Icon is converted into current and voltage by the current detection resistor Rs is input via the terminal CS.

The current detection threshold voltage Vcsqr output from the comparison voltage generation unit 18 is input to the inverting input end of the comparator 19. The comparator 19 outputs the comparison result of the current detection signal Vcs and the current detection threshold voltage Vcsqr to the control logic unit 24.

Here, the ADIM terminal is an external terminal for inputting an analog dimming signal (analog voltage signal) from the outside. When the QR mode is selected by the selection signal SEL_sig, the comparison voltage generation unit 18 outputs the current detection threshold voltage Vcsqr obtained by multiplying the analog dimming signal by the first gain magnification. By adjusting the analog dimming signal, the LED array 50 can be dimmed in the QR mode.

The CS terminal and the error amplifier 20 are used for current feedback control in the CCM mode. The current detection signal Vcs is input to the inverting input end of the error amplifier 20 via the CS terminal. A current feedback voltage Vcsccm as a reference voltage output from the comparison voltage generation unit 18 is input to the non-inverting input end of the error amplifier 20. An FB terminal is connected to the output terminal of the error amplifier 20. An external capacitor Cfb is connected to the FB terminal.

When the CCM mode is selected by the selection signal SEL_sig, the comparison voltage generation unit 18 outputs the current feedback voltage Vcsccm obtained by multiplying the analog dimming signal by the second gain magnification. By adjusting the analog dimming signal, the LED array 50 can be dimmed in the CCM mode.

More details of the operation by the comparison voltage generation unit 18 will be described later.

The output end of the error amplifier 20 is connected to the non-inverting input end of the comparator 21. An oscillation signal output from the oscillator 22 is input to the inverting input end of the comparator 21. The oscillation signal is, for example, a saw-shaped waveform. The comparator 21 outputs the PWM signal Spwm to the control logic unit 24 as a comparison result between the output of the error amplifier 20 and the oscillation signal.

In the CCM mode, the PWM control frequency is fixed, but this frequency is set by the external resistor R21 connected to the RT terminal.

Further, the ZT terminal is a terminal for detecting the zero cross of the coil current Icon in the QR mode, and is connected to the connection node of the voltage dividing resistors R11 and R12. The inverting input end of the comparator CP2 is connected to the ZT terminal. A predetermined reference voltage is applied to the non-inverting input end of the comparator CP2. The comparator CP2 outputs the zero-cross detection signal to the control logic unit 24. The comparator CP3 is also connected to the ZT terminal, but the comparator CP3 is used for correction control of the LED current ILED in the QR mode, and the details thereof will be described later.

When the QR mode is selected by the selection signal SEL_sig, the amplifier 16 amplifies the output from the low-pass filter 15 and outputs the output. When the PWM dimming signal is High, the control logic unit 24 outputs the gate output signal Gout of the OUT terminal to the low-pass filter 15. As a result, the low-pass filter 15 smoothes and outputs the gate output signal Gout. That is, the QRCOMP terminal outputs a DC voltage proportional to the on-duty of the gate output signal Gout to the outside when the QR mode is selected by the selection signal SEL_sig and the PWM dimming signal is High. The DC voltage output from the QRCOMP terminal is used to generate an analog dimming signal input to the ADIM terminal, and corrects the linearity of the LED current in the QR mode.

When the control logic unit 24 detects an abnormality, the control logic unit 24 uses the abnormality detection unit 23 to output an abnormality signal indicating an abnormality state from the FAILB terminal to the outside. The abnormal signal has a different level depending on whether it is in an abnormal state or a normal state.

The GND terminal is a terminal for grounding the IC. The DGND terminal is a terminal for taking the digital ground of the IC.

<2. QR mode and CCM mode>
Next, each operation in the QR mode and the CCM mode will be described. When the QR mode is selected by the selection input signal input to the SEL terminal, the control logic unit 24 controls the operation in the QR mode by the selection signal SEL_sig indicating to that effect.

First, the control logic unit 24 outputs the high gate output signal Gout from the OUT terminal and turns on the switching element M1. Then, the coil current Icoil starts to flow through the switching element M1 and the current detection resistor Rs, which are turned on, and increases. At this time, the current detection signal Vcs detected by the current detection resistor Rs increases. Then, when the current detection signal Vcs becomes equal to or higher than the current detection threshold voltage Vcsqr, the output of the comparator 19 rises to High, and the control logic unit 24 lowers the gate output signal Gout to Low.

As a result, the switching element M1 is turned off, the drain voltage Vrd of the switching element M1 rises, and the coil current Icoil starts to flow through the diode D1 and decreases. At this time, the ZT voltage Vzt applied to the ZT terminal increases as the drain voltage Vdr increases, and then gradually decreases. Then, when the coil current Icoil becomes zero, the drain voltage Vdr drops sharply, and the ZT voltage Vzz also drops sharply. Then, when the ZT voltage Vzt becomes equal to or lower than the predetermined reference voltage, the output of the comparator CP2 rises to High. As a result, zero crossing of the coil current Icoil is detected. Then, the control logic unit 24 raises the gate output signal Gout to High and turns on the switching element M1 again.

FIG. 2 shows an example of the waveforms of the coil current Icoil and the LED current ILED in such a QR mode. The coil current Icoil increases from zero, then starts to decrease at a predetermined current value, and increases again when it reaches zero. As shown in the region A1 in FIG. 2, in the QR mode, soft switching is performed in which no current flows through the switching element M1 when the switching element M1 is turned on, so that heat generation (loss) and generation of noise are suppressed. However, since the amplitude of the coil current Icoil becomes large, the ripple of the LED current ILED obtained by averaging the coil current Icoil becomes large.

On the other hand, when the CCM mode is selected by the selection input signal, the control logic unit 24 controls the operation of the CCM mode. Here, the error amplifier 20 and the comparator 21 are enabled, and the control logic unit 24 outputs a gate output signal Gout composed of High and Low according to the PWM signal Spwm output from the comparator 21, and controls the switching element M1 on and off. To do. That is, current feedback control is performed in which the on-duty of the PWM signal Spwm is adjusted so that the average value of the current detection signal Vcs matches the current feedback voltage Vcsccm. As a result, the average value of the coil current Icoil is controlled so as to match the desired value.

An example of the waveforms of the coil current Icoil and the LED current ILED in such a CCM mode is shown in FIG. The switching element M1 is turned on and off according to the PWM signal Spwm, and the coil current Icon repeatedly increases and decreases. The coil current Icon is controlled so that it always flows. The switching cycle of the switching element M1 is fixed. At this time, since the amplitude of the coil current Icoil is small, the ripple of the LED current ILED is small. However, as shown in the region A2 in FIG. 3, hard switching is performed in which a current flows through the switching element M1 when the switching element M1 is turned on, which is disadvantageous in terms of heat generation (loss) and generation of noise.

As described above, in the light emitting element driving device 1 of the present embodiment, the QR mode and the CCM mode can be selected by the selection input signal with one IC, so that the degree of freedom in design is improved. It is also possible to switch to the operation of the other mode while one of the two modes is operating. Thereby, for example, when switching the brightness of the LED from low brightness to high brightness, it is possible to switch from the QR mode to the CCM mode in which the ripple of the LED current is small.

<3. Setting of current detection threshold voltage Vcsqr and current feedback voltage Vcsccm>
Here, the setting of the current detection threshold voltage Vcsqr and the current feedback voltage Vcsccm by the comparative voltage generation unit 18 will be described in detail.

When the QR mode is selected, the current detection threshold voltage Vcsqr is basically set by the following equation (1).
Vcsqr = Vadim x G1 ... (1)
However, Vadim is an analog dimming signal, and G1 is the first gain magnification.

When the CCM mode is selected, the current feedback voltage Vcsccm is basically set by the following equation (2).
Vcsccm = Vadim x G2 ... (2)
However, Vadim is an analog dimming signal, and G2 is the second gain magnification.

Then, the first gain magnification G1 is set to twice the second gain magnification G2 (for example, G1 = 0.7, G2 = 0.35). Thereby, the current value of the LED current ILED can be made similar in both modes with the same analog dimming signal Vadim setting value.

More specifically, in the present embodiment, the current detection threshold voltage Vcsqr and the current feedback voltage Vcsccm are set as follows according to the on / off of the function of the ODP unit 17 by setting the on / off setting signal input to the DUTYON terminal. ..

* When the QR mode is selected and the function of the ODP unit 17 is on Vcsqr = Vadim x G1 (Vdim ≤ Vclp1) ... (11)
Vcsqr = Vclp1 x G1 (Vadim> Vclp1) ... (12)
* When the QR mode is selected and the function of the ODP unit 17 is off Vcsqr = Vadim x G1 (Vdim ≤ Vclp2) ... (13)
Vcsqr = Vclp2 x G1 (Vadim> Vclp2) ... (14)

* When CCM mode is selected and the function of ODP unit 17 is on Vcsccm = Vadim x G2 (Vdim ≤ Vclp1) ... (15)
Vcsccm = Vclp1 x G2 (Vadim> Vclp1) ... (16)
* When CCM mode is selected and the function of ODP unit 17 is off Vcsccm = Vadim x G2 (Vdim ≤ Vclp2) ... (17)
Vcsccm = Vclp2 x G2 (Vadim> Vclp2) ... (18)

However, Vclp1 and Vclp2 are clamp voltages of the analog dimming signal Vadim, and Vclp1> Vclp2.

That is, the current detection threshold voltage Vcsqr and the current feedback voltage Vcsccm can be limited by the clamp voltages Vclp1 and Vclp2. Further, the reason why Vclp1 used when the function of the ODP unit 17 is on is higher than Vclp2 used when the function is off is that the on time of the PWM dimming signal is limited when the function is on, so that the current detection threshold value is high. This is because there is no problem even if the limits of the voltage Vcsqr and the current feedback voltage Vcsccm are relaxed.

<4. LED current correction in QR mode>
The light emitting element drive device 1 of the present embodiment has a function of correcting the LED current ILED (coil current Icon) in the QR mode to improve the accuracy. Here, the timing chart shown in FIG. 4 describes this function. Will be described using.

When the switching element M1 is turned on, the coil current Icoil starts to increase from zero at the timing t0 shown in FIG. 4, and the current detection signal Vcs also starts to increase. After that, when the current detection signal Vcs reaches the current detection threshold voltage Vcsqr at the timing t1, the output signal CS_DET of the comparator 19 rises to High.

At the subsequent delayed timing t2, the gate output signal Gout output by the control logic unit 24 falls to Low. Here, due to the presence of the gate resistance Rg of the external component and the gate capacitance (not shown), the gate signal Gt drops to the timing t3 with a certain inclination.

At the timing t3, the drain voltage Vdr begins to rise due to the turn-off of the switching element M1, and at the timing t4, the drain voltage Vdr reaches the LED voltage VLED. At this timing t4, the coil current Icoil changes from an increase to a decrease. That is, the coil current Icon increases as the accumulation of the delay from timing t1 to t2 due to the internal circuit, the delay from timing t2 to t3 due to external components, and the delay from timing t3 to t4 due to the rise of the drain voltage Vdr. The delay of the turnaround timing that turns to decrease occurs by the delay time DTqr. As a result, the increase in the coil current Icoil is maintained for the period of the delay time DTqr. Therefore, the LED current ILED obtained by averaging the coil current Icoil shifts to a higher value, causing a problem in current accuracy.

Therefore, in the present embodiment, control is performed using the ZT voltage Vzz generated at the ZT terminal. As shown in FIG. 4, as the drain voltage Vdr increases from the timing t3, the ZT voltage Vzz also increases, and the ZT voltage Vzz reaches a predetermined threshold voltage ZTH1 at the timing t4. The threshold voltage ZTH1 is set as a reference voltage of the comparator CP3, and the output of the comparator CP3 rises to High at the timing t4. Therefore, in the present embodiment, the control logic unit 24 detects the delay time DTqr by starting counting from the timing t1 at which the output signal CS_DET of the comparator 19 rises and counting up to the timing t4 when the output of the comparator CP3 becomes High. To do.

Then, the control logic unit 24 adjusts the analog dimming signal Adim according to the delay time DTqr. As a result, the current detection threshold voltage Vcsqr can be adjusted to correct the coil current Icon and thus the LED current ILED. In addition to the method of feeding back to the analog dimming signal Adim as described above, the control logic unit 24 may adjust the on-duty of the gate output signal Gout. That is, the control logic unit 24 corresponds to an example of the coil current correction unit.

In this way, in the present embodiment, it is possible to detect the delay of the folding back timing of the coil current Icoil in the QR mode and improve the accuracy of the LED current ILED. In particular, the delay time DTqr can be detected by diverting the ZT voltage Vzz of the ZT terminal used for zero cross detection in the QR mode.

As shown in FIG. 4, at the timing t5 when the coil current Icoil decreases and reaches zero, the drain voltage Vdr drops sharply, and the ZT voltage Vzz also drops accordingly. At the timing t6 when the ZT voltage Vzz reaches the threshold voltage ZTH2, the output of the comparator CP2 rises to High, and zero crossing of the coil current Icon is detected. That is, the threshold voltage ZTH2 is set as the reference voltage of the comparator CP2.

Since ZTH2 is set to a value close to zero and ZTH1 is higher than ZTH2 and has a different voltage level from ZTH2, in the present embodiment, both the comparator CP2 and the comparator CP3 are provided. In this way, by providing the comparator CP3 for comparison with ZTH1, the delay time DTqr can be detected with high accuracy. However, the comparator CP2 for zero cross detection can also be used for delay time DTqr detection. In that case, the number of parts can be reduced.

<5. LED current correction in CCM mode>
Further, the light emitting element driving device of the present embodiment can be equipped with a function of correcting the LED current ILED (coil current Icon) to improve the accuracy in the CCM mode, and this function will be described here. ..

FIG. 5 is a diagram in which only the configuration related to the current feedback control in the CCM mode in the light emitting element driving device 1 shown in FIG. 1 is extracted. The switching control unit 1A shown in FIG. 5 is a functional unit including a comparator 21, an oscillator 22, a control logic unit 24, and a driver Dr1, and outputs a gate output signal Gout to an OUT terminal based on the output from the error amplifier 20. Output from. In the configuration shown in FIG. 5, the function of correcting the LED current in the CCM mode is not installed.

In the configuration of FIG. 5, the switching control unit 1A adjusts the on-duty of the gate output signal Gout so that the average value of the current detection signal Vcs matches the current feedback voltage Vcsccm.

FIG. 7 is a timing chart showing an example of various signal waveforms in the CCM mode in the configuration shown in FIG. 5 (FIG. 1). At the timing t10 shown in FIG. 7, the gate output signal Gout is High, the coil current Icon starts to increase due to the turn-on of the switching element M1, the current detection signal Vcs rises sharply from 0V, and then rises.

By adjusting the on-duty, the gate output signal Gout is switched to Low at the timing t11. Due to the presence of the external gate resistor Rg and the gate capacitance (not shown), the gate signal Gt is switched to Low at the delayed timing t12.

Due to the turn-off of the switching element M1, the drain voltage Vdr rises from the timing t12, and the drain voltage Vdr reaches the LED voltage VLED at the timing t13. At this timing t13, the coil current Icon changes from an increase to a decrease.

In the configuration shown in FIG. 5, the error amplifier 20 monitors the current detection signal Vcs only during the period when the gate output signal Gout is High. As a result, as shown in FIG. 7, the on-duty of the gate output signal Gout is adjusted so that the average value of the current detection signal Vcs matches the current feedback voltage Vcsccm. However, due to the occurrence of the delay time DTccm from the timings t11 to t13, the coil current Icoil continues to increase for the period of the delay time DTccm, and the average value of the coil current Icoil deviates higher than the desired value Iccm. Therefore, there is a problem with the accuracy of the LED current ILED. That is, even if the IC (light emitting element driving device) is supposed to be able to control accurately, the LED current ILED actually deviates.

Therefore, by making the configuration shown in FIG. 5 the configuration shown in FIG. 6, the correction control of the LED current ILED becomes possible. The light emitting element driving device 100 shown in FIG. 6 is a partially modified configuration of the light emitting element driving device 1 shown in FIG. 5 (FIG. 1).

In the light emitting element driving device 100 shown in FIG. 6, a sample hold portion 100A is inserted between the CS terminal and the inverting input end of the error amplifier 20 as a difference from the configuration of FIG. Further, in the configuration of FIG. 6, the ZT voltage Vzt of the ZT terminal is also used. The error amplifier 20 monitors the sampling output Vsmp output from the sample hold unit 100A. An example of a drive control unit or a coil current correction unit is configured from the sample hold unit 100A, the error amplifier 20, and the switching control unit 1A.

FIG. 8 is a timing chart showing an example of various signal waveforms in the CCM mode in the configuration shown in FIG. During the period when the gate output signal Gout at the timings t10 to t11 shown in FIG. 8 is High, the sample hold unit 100A outputs the current detection signal Vcs as it is as the sampling output Vsmp.

Then, when the gate output signal Gout is switched to Low at the timing t11, the sample hold unit 100A performs a hold operation for maintaining the sampling output Vsmp at that timing. At the timing t12 after the timing t11, the drain voltage Vdr starts to rise, and the ZT voltage Vzt of the ZT terminal also rises accordingly. Then, the ZT voltage Vzz reaches the threshold voltage Zth at the timing t13 when the drain voltage Vdr reaches the LED voltage VLED. The error amplifier 20 monitors the sampling output Vsmp only during the period from when the gate output signal Gout is switched to High until the ZT voltage Vzz reaches the threshold voltage Zth.

In the configuration shown in FIG. 6, the on-duty of the gate output signal Gout is adjusted so that the average value of the sampling output Vsmp matches the current feedback voltage Vcsccm, but as shown in FIG. 8, only the period corresponding to the delay time DTccm. Since the sampling output Vsmp held by the sample hold unit 100A is added and monitored, the average value of the sampling output Vsmp is corrected to a higher value. As a result, as shown by the arrow in FIG. 8, the sampling output Vsmp and the coil current Icon are corrected to be low. Therefore, the LED current ILED is corrected so as to approach a desired value, and the current accuracy can be improved.

Alternatively, as another method, a method similar to the method in the QR mode described above can be applied to the CCM mode. That is, the control logic unit 24 starts counting from the timing t11 when the gate output signal Gout shown in FIG. 8 switches from High to Low, and counts until the timing t13 when the ZT voltage Vzt reaches the threshold voltage Zth, so that the delay time DTccm is detected. In this case, in the configuration of FIG. 1, a comparator that compares the ZT voltage Vzz with the threshold voltage Zth may be provided. Then, the control logic unit 24 adjusts the analog dimming signal Adim according to the detected delay time DTccm. As a result, the current feedback voltage Vcsccm can be adjusted to correct the coil current Icon and thus the LED current ILED. In addition to the method of feeding back to the analog dimming signal Adim as described above, the control logic unit 24 may adjust the on-duty of the gate output signal Gout.

It should be noted that a modified embodiment in which control is performed using a comparator in the CCM mode as in the QR mode is also possible, and in that case, the error amplifier 20 and the FB terminal are unnecessary. As a first example of such a modified embodiment, the control logic unit 24 starts time measurement from the timing when the gate output signal Gout is switched from Low to High and the switching element M1 is turned on. Then, the control logic unit 24 monitors the output of the comparator to which the reference voltage and the current detection signal Vs are input, ends the time measurement at the timing when the current detection signal Vs becomes equal to or higher than the reference voltage, and from that timing, the above The gate output signal Gout is switched from High to Low at a timing equal to the measurement time from the start to the end of the time measurement. Thereby, the average value of the coil current Icoil can be controlled to a desired current value defined by the reference voltage.

Further, as a second example of the modified embodiment, the control logic unit 24 detects the difference between the current detection signal Vs and the reference voltage when the switching element M1 is turned on, and adds the detected difference to the reference voltage. The determined voltage is set as the current detection threshold voltage similar to that in the QR mode, and the output of the comparator is monitored to determine the timing at which the gate output signal Gout is switched from High to Low. Thereby, the average value of the coil current Icoil can be controlled to a desired current value defined by the reference voltage.

Then, in the case of the modified embodiment according to the first and second examples, the control logic unit 24 detects the delay time DTccm as described above, and adjusts the reference voltage or the on-time according to the detected delay time DTccm. Then, the coil current Icon can be corrected.

<6. IC package pin layout>
FIG. 9 is a top view of the light emitting element driving device 1 (or 100) according to the present embodiment as an IC package product. In FIG. 9, the arrangement (pin arrangement) of each external terminal is shown. The IC package shown in FIG. 9 is configured as a SOP (Small Outline Package). The lead frame, which is each external terminal, is connected to the electrode of the LSI chip by a bonding wire (Au wire or the like), and the LSI chip and the lead frame are sealed by a sealing material (epoxy resin or the like).

As shown in FIG. 9, the IC package has a rectangular encapsulant when viewed from above. The sealing material has a first side which is one long side and a second side which is a long side parallel to the first side. Along the first side, the VCS terminal, the UVLO terminal, the SEL terminal, the PWM terminal, the QRCOMP terminal, the ADIM terminal, the FAILB terminal, and the DUTYON terminal are arranged in this order. Further, along the second side, the REG90 terminal, the CS terminal, the OUT terminal, the GND terminal, the DGND terminal, the FB terminal, the ZT terminal, and the RT terminal are arranged in this order.

The VCS terminal and UVLO terminal of the input power supply system, the SEL terminal, PWM terminal, QRCOMP terminal, ADIM terminal, FAILB terminal, and DUTYON terminal, which are input / output relationships with a microcomputer (not shown), and the IC package are PCB (board). In consideration of the wiring when mounting in, they are arranged together on the same long side.

Further, the FB terminal is arranged between the DGND terminal and the ZT terminal. If a high voltage is applied to the FB terminal, the on-duty of PWM control becomes very large in the CCR mode, and the LED current may become overcurrent. However, even if the FB terminal is short-circuited with the adjacent DGND terminal or ZT terminal, there is no problem because the DGND terminal and the ZT terminal are terminals to which a low voltage is applied and a low voltage is applied to the FB terminal.

<7. Arrangement configuration on the chip>
FIG. 10 is a plan view showing the arrangement of electrode pads in the chip 101 provided in the light emitting element driving device 1 according to the present embodiment and the arrangement of each region in which each component shown in FIG. 1 is arranged.

In FIG. 10, the X-axis direction and the Y-axis direction orthogonal to the X-axis direction are shown, the X-axis direction is more specifically shown in the X1 direction and the X2 direction, and the Y-axis direction is more concrete. Is shown in the Y1 direction and the Y2 direction. The X2 direction and the Y2 direction are directions that approach each other.

The chip 101 shown in FIG. 10 has a rectangular shape as an outer shape. The rectangular shape has a first side S1 extending in the Y-axis direction on the X2 direction side, a second side S2 extending in the X-axis direction on the Y2 direction side, and a third side S3 extending in the Y-axis direction on the X1 direction side. It has a fourth side S4 extending in the X-axis direction on the Y1 direction side.

The chip 101 has two VCS pads, a UVLO pad, a SEL pad, a PWM pad, a QRCOMP pad, an ADIM pad, a FAILB pad, a DUTYON pad, an RT pad, a ZT pad, an FB pad, a DGND pad, and two GND pads as electrode pads. It has two OUT pads, a CS pad, and two REG90 pads. Each of these pads is provided corresponding to each terminal of the IC package shown in FIG.

Along the first side S1, the CS pad, the first REG90 pad, the second REG90 pad, the first VCS pad, the second VCS pad, and the UVLO pad are arranged in this order in the Y2 direction. Along the second side S2, the SEL pad, the PWM pad, the QRCOMP pad, the ADIM pad, and the FAILB pad are arranged in this order in the X1 direction. Along the third side S3, the DUTYON pad, the RT pad, and the ZT pad are arranged in this order in the Y1 direction. Along the fourth side S4, the FB pad, the DGND pad, the first GND pad, the second GND pad, the first OUT pad, and the second OUT pad are arranged in this order in the X2 direction.

The chip 101 has an A region to an M region as a region in which each component shown in FIG. 1 is arranged.

The A region, the B region, and the C region are arranged in the Y2 direction in this order in the X1 direction view. The A region overlaps the first OUT pad and the second OUT pad in the X-axis direction in the Y2 direction, and overlaps the CS pad in the Y-axis direction in the X1 direction. The B region overlaps the A region in the X-axis direction in the Y2 direction, and overlaps the first REG90 pad and the second REG90 pad in the Y-axis direction in the X1 direction. The B region does not overlap with the first VCS pad in the Y-axis direction in the X1 direction.

The first VCS pad and the second VCS pad are connected to the input end of the internal voltage generation unit 11 arranged in the B region via the top metal wiring. The internal voltage generation unit 11 includes a power transistor. The output end of the internal voltage generation unit 11 is connected to the power input end of the driver Dr1 arranged in the A region via the top metal wiring. The driver Dr1 includes a power transistor. As a result, the internal voltage Vreg generated by the internal voltage generation unit 11 based on the power supply voltage Vcc applied to the first VCC pad and the second VCS pad is supplied as the power supply voltage of the driver Dr1. The output end of the driver Dr1 is connected to the first OUT pad and the second OUT pad.

The A region does not overlap the first GND pad and the second GND pad in the X-axis direction in the Y2 direction. The ground end of the driver Dr1 is connected to the first GND pad and the second GND pad.

In this way, the 1st and 2nd REG90 pads and the 1st and 2nd VCS pads are arranged near the B area, and the A area is arranged near the 1st and 2nd OUT pads and the 1st and 2nd GND pads. ..

The C region does not overlap with the first VCS pad in the Y-axis direction in the X1 direction, but overlaps with the second VCS pad and the UVLO pad in the Y-axis direction in the X1 direction. The C region overlaps the B region in the X-axis direction in the Y2 direction. As a result, the C region is arranged near the UVLO pad. The UVLO unit 13 is arranged in the C region.

The C region to H region are arranged in the X1 direction in this order in the Y1 direction view. The D region is displaced from the SEL pad toward the X1 direction in the Y1 direction, and does not overlap with the SEL pad in the X-axis direction. Further, the D region overlaps the C region in the Y-axis direction in the X2 direction. As a result, the D region is arranged near the SEL pad. The comparator CP1 is arranged in the D region.

The E region overlaps the PWM pad and the QRCOMP pad in the X-axis direction in the Y1 direction. The E region overlaps the C region in the Y-axis direction in the X2 direction, but does not overlap the D region in the Y-axis direction. The ODP unit 17 is arranged in the E region. The distance in the Y-axis direction between the PWM pad and the E region in the X2 direction view is shorter than the distance in the X-axis direction between the DUTYON pad and the E region in the Y1 direction view. This is because the on / off setting signal applied to the DUTYON pad is constant at the High level or the Low level as compared with the PWM dimming signal applied to the PWM pad, and the tolerance of noise to the signal applied to the DUTYON pad. Is big.

The F region is displaced from the QRCOMP pad in the X1 direction in the Y1 direction, and does not overlap the QRCOMP pad in the X-axis direction, but overlaps the ADIM pad in the X-axis direction. The F region overlaps the D region and the E region in the Y-axis direction in the X2 direction. The amplifier 16 is arranged in the F region. The F region is located near the QRCOMP pad.

The G region overlaps the ADIM pad in the X-axis direction in the Y1 direction, and overlaps the F region in the Y-axis direction in the X2 direction. The comparison voltage generation unit 18 is arranged in the G region. The G region is located near the ADIM pad. Since an analog dimming signal, which is an analog voltage, is applied to the ADIM pad, noise is suppressed and the influence on dimming is suppressed.

The H region overlaps the FAILB pad in the X-axis direction in the Y1 direction, and overlaps the G region in the Y-axis direction in the X2 direction. The abnormality detection unit 23 is arranged in the H region. The H region is located near the FAILB pad.

The set consisting of the G and H regions, the I region, and the J region are arranged in the Y1 direction in this order in the X2 direction view. The I region is deviated from the DUTYON pad in the Y1 direction in the X2 direction, and does not overlap the DUTYON pad in the Y-axis direction, but overlaps the RT pad in the Y-axis direction. The oscillator 22 is arranged in the I region. Area I is located near the RT pad.

The J region is displaced from the RT pad toward the Y1 direction in the X2 direction, and does not overlap the RT pad in the Y-axis direction, but overlaps the ZT pad in the Y-axis direction. The comparators CP2 and CP3 are arranged in the J region. The J region is arranged near the ZT pad.

The J region, the K region, the L region, and the A region are arranged in the X2 direction in this order in the Y2 direction view. The K region is displaced from the FB pad in the X2 direction in the Y2 direction, does not overlap the FB pad in the X-axis direction, and overlaps the DGND pad in the X-axis direction. The K region overlaps the J region in the Y-axis direction in the X2 direction. The error amplifier 20 is arranged in the K region. The K region is located near the FB pad.

The L region overlaps the first and second GND pads in the X-axis direction in the Y2 direction. The L region overlaps the K region in the Y-axis direction in the X2 direction. The comparator 19 is arranged in the L region.

The M region is arranged in the central portion of the chip 101 which is surrounded on the outside by the A region to the L region. The control logic unit 24 is arranged in the M area.

<8. Application to liquid crystal display (LCD)>
A liquid crystal display device (an example of an electronic device) will be described as an example of an object to which the light emitting element driving device according to the above-described embodiment is applied. A configuration example of the liquid crystal display device is shown in FIG. The configuration shown in FIG. 11 is a so-called edge light system, and is not limited to this, and a direct system may be used.

The liquid crystal display device X shown in FIG. 11 includes a backlight 81 and a liquid crystal panel 82. The backlight 81 is a lighting device (an example of a light emitting device) that illuminates the liquid crystal panel 82 from the back surface. The backlight 81 includes an LED light source unit 811, a light guide plate 812, a reflector plate 813, and optical sheets 814.

The LED light source unit 811 includes an LED and a substrate on which the LED is mounted, and the above-described embodiment can be applied as the light emitting element driving device for driving the LED. The light emitted from the LED light source unit 811 enters the inside from the side surface of the light guide plate 812. For example, the light guide plate 812 made of an acrylic plate guides the light entering the inside to the entire inside while totally reflecting the light, and emits the light as planar light from the surface on the side where the optical sheets 814 are arranged. The reflector 813 reflects the light leaked from the light guide plate 812 and returns it to the inside of the light guide plate 812. The optical sheets 814 are made of a diffusion sheet, a lens sheet, or the like, and have an object of making the brightness of the light illuminating the liquid crystal panel 82 uniform or improving the brightness.

<9. Others>
Although the embodiments of the present invention have been described above, the embodiments can be changed in various ways within the scope of the gist of the present invention.

For example, in the present invention, the light emitting element driving device may include only one of the QR mode and the CCM mode. In particular, in the case of a light emitting element driving device having only a CCM mode in which the amplitude of the coil current Icon is relatively small, it is not always necessary to provide the capacitor C1 for averaging the coil current Icon. Even when both the QR mode and the CCM mode are provided, a configuration in which the capacitor C1 is not provided can be adopted.

The present invention can be used, for example, in a light emitting element driving device for driving an LED.

1 Light emitting element drive device 11 Internal voltage generator 12 IC power supply UVLO unit 13 UVLO unit 14 Internal voltage UVLO unit 15 Low pass filter 16 Amplifier 17 ODP (Over Duty Protection) unit 18 Comparison voltage generator 19 Comparator 20 Comparator 21 Comparator 22 Oscillator 23 Abnormality detection unit 24 Control logic unit 50 LED array CP1 to CP3 comparator Dr1 driver R1, R2 voltage division resistor D1 diode C1 capacitor L1 coil C2 capacitor R11, R12 voltage division resistor M1 switching element Rs current detection resistor Rg gate resistance Cfb capacitor 100 Light emitting element drive device 100A Sample hold unit 1A Switching control unit 101 Chip

Claims (25)

A light emitting part consisting of at least one light emitting element to which an input voltage is applied to one end,
A coil whose one end is connected to the other end of the light emitting portion,
A diode connected between the other end of the coil and one end of the light emitting portion,
A switching element having a first terminal connected to the other end of the coil,
A light emitting element driving device for driving the light emitting unit in an external configuration including the above.
A first external terminal connected to the control terminal of the switching element,
A drive control unit that generates a drive signal that drives the switching element on and off and outputs it from the first external terminal.
With
The drive control unit includes a coil current correction unit that corrects the coil current by adjusting the drive signal based on a delay in the turnaround timing at which the coil current flowing through the coil changes from an increase to a decrease.
Light emitting element drive device. The external configuration
A current detection resistor whose end is connected to the second terminal of the switching element
A first capacitor whose one end is connected to the other end of the coil,
The voltage dividing resistor connected to the other end of the first capacitor and
Including
The light emitting element driving device is
A second external terminal connected to a connection node between the second terminal and the current detection resistor,
With the third external terminal to which the connection node of the voltage dividing resistor is connected,
With more
The drive control unit
A first comparator that compares the current detection signal generated at the second external terminal with the current detection threshold voltage,
The ZT voltage generated in the third external terminal is input, and the second comparator used for zero-cross detection of the coil current and
Have,
In the coil current correction unit, after the first comparator detects that the current detection signal has increased and reached the current detection threshold voltage, the ZT voltage has increased to reach a predetermined ZT threshold voltage. The light emitting element driving device according to claim 1, wherein the time until the detection is detected is detected as the delay time of the return timing. The light emitting element driving device according to claim 2, further comprising a third comparator in which the ZT voltage and a reference voltage corresponding to the ZT threshold voltage are input. The light emitting element driving device according to claim 2, wherein it is detected by the second comparator that the ZT voltage has increased to reach a predetermined ZT threshold voltage. The current detection threshold voltage is generated based on an analog dimming signal.
The light emitting element driving device according to any one of claims 2 to 4, wherein the coil current correction unit adjusts the analog dimming signal based on the delay time. The light emitting element driving device according to any one of claims 2 to 4, wherein the coil current correction unit adjusts the on-time of the driving signal based on the delay time. The 4th external terminal to which the PWM dimming signal is input and
The 5th external terminal to which the on / off setting signal is input and
An ODP (Over Duty Protection) unit that switches on / off the function of limiting the duty of the PWM dimming signal according to the on / off setting signal, and
The 6th external terminal to which the analog dimming signal is input and
A comparative voltage generator that generates the current detection threshold voltage based on the analog dimming signal, and
With more
The light emitting element driving device according to any one of claims 2 to 6, wherein the comparative voltage generation unit generates the current detection threshold voltage based on the following equation.
When the function of the ODP part is on Vcsqr = Vadim × G1 (Vdim ≦ Vclp1)
Vcsqr = Vclp1 x G1 (Vadim> Vclp1)
When the function of the ODP part is off Vcsqr = Vadim × G1 (Vdim ≦ Vclp2)
Vcsqr = Vclp2 x G1 (Vadim> Vclp2)
Vclp1> Vclp2
However, Vcsqr: the current detection threshold voltage, Vadim: the analog dimming signal, G1: first gain magnification, Vclp1: first clamp voltage, Vclp2: second clamp voltage. The external configuration
A current detection resistor whose end is connected to the second terminal of the switching element
A second capacitor whose one end is connected to the other end of the coil,
The voltage dividing resistor connected to the other end of the second capacitor and
Including
The light emitting element driving device is
A seventh external terminal connected to a connection node between the second terminal and the current detection resistor,
The eighth external terminal to which the connection node of the voltage dividing resistor is connected and
The 9th external terminal to which the 3rd capacitor is connected and
With more
The drive control unit
A sample hold unit to which a current detection signal generated at the 7th external terminal is input, and
An error amplifier having an input end to which the output of the sample hold unit and the current feedback voltage are input and an output end to which the ninth external terminal is connected, and an error amplifier.
The fourth comparator to which the output of the error amplifier and the oscillation signal are input, and
Have,
The coil current correction unit
The sample hold unit that holds and outputs when the drive signal is switched from the on level to the off level, and
The error amplifier that monitors the output of the sample hold unit until the timing when the ZT voltage generated at the eighth external terminal rises and reaches a predetermined ZT threshold voltage, and the error amplifier.
The light emitting element driving device according to claim 1. The external configuration
A current detection resistor whose end is connected to the second terminal of the switching element
A second capacitor whose one end is connected to the other end of the coil,
The voltage dividing resistor connected to the other end of the second capacitor and
Including
The light emitting element driving device is
A seventh external terminal connected to a connection node between the second terminal and the current detection resistor,
The eighth external terminal to which the connection node of the voltage dividing resistor is connected and
With more
The drive control unit
The drive signal is generated so that the average value of the coil current is a desired value based on the voltage of the 7th external terminal and the reference voltage.
The coil current correction unit
With a detection unit that detects as the delay time of the turnaround timing the time from when the drive signal is switched from the on level to the off level until the ZT voltage generated at the eighth external terminal rises and reaches a predetermined ZT threshold voltage. ,
An adjusting unit that adjusts the reference voltage or the on-time of the drive signal based on the delay time.
The light emitting element driving device according to claim 1. The external configuration further comprises a ninth external terminal to which a third capacitor is connected.
The drive control unit
An error amplifier having an input terminal to which the voltage of the 7th external terminal and the current feedback voltage which is the reference voltage are input and an output terminal to which the 9th external terminal is connected.
The fourth comparator to which the output of the error amplifier and the oscillation signal are input, and
The light emitting element driving device according to claim 9. The drive control unit starts time measurement from the timing when the drive signal is switched from the off level to the on level, and monitors the output of the fifth comparator to which the reference voltage and the voltage of the seventh external terminal are input. The time measurement is finished at the timing when the voltage of the 7th external terminal becomes equal to or higher than the reference voltage, and the drive signal is turned from the on level to the off level at the timing when the time equal to the measurement time by the time measurement elapses from that timing. The light emitting element driving device according to claim 9, which switches to. The drive control unit detects the difference between the voltage of the seventh external terminal and the reference voltage when the switching element is turned on, and adds the detected difference to the reference voltage to determine the voltage and the first. 7. The light emitting element driving device according to claim 9, wherein the output of the sixth comparator to which the voltage of the external terminal is input is monitored to determine the timing of switching the drive signal from the on level to the off level. The 10th external terminal to which the PWM dimming signal is input and
The 11th external terminal to which the on / off setting signal is input and
An ODP (Over Duty Protection) unit that switches on / off the function of limiting the duty of the PWM dimming signal according to the on / off setting signal, and
The 12th external terminal to which the analog dimming signal is input and
A comparative voltage generator that generates the current feedback voltage based on the analog dimming signal,
With more
The light emitting element driving device according to claim 8 or 10, wherein the comparative voltage generation unit generates the current feedback voltage based on the following equation.
When the function of the ODP part is on Vcsccm = Vadim × G2 (Vadim ≤ Vclp1)
Vcsccm = Vclp1 x G2 (Vadim> Vclp1)
When the function of the ODP part is off Vcsccm = Vadim x G2 (Vadim ≤ Vclp2)
Vcsccm = Vclp2 x G2 (Vadim> Vclp2)
Vclp1> Vclp2
However, Vcsccm: the current feedback voltage, Vadim: the analog dimming signal, G2: the second gain magnification, Vclp1: the first clamp voltage, Vclp2: the second clamp voltage. Further equipped with a thirteenth external terminal to which a selection input signal is input,
The first aspect of the present invention, wherein the drive control unit operates by switching between a QR mode (quasi-resonant: pseudo-resonant method) and a CCM mode (continuous current mode) according to the selection input signal. Light emitting element drive device. The external configuration further includes a current detection resistor one end connected to the second terminal of the switching element.
The drive control unit
The current detection signal generated by the current detection resistor is input, and the seventh comparator used in the QR mode and
An error amplifier used in the CCM mode in which the current detection signal is input and a fourth capacitor is connected to the output end, and
Have,
The light emitting element driving device is
The 14th external terminal to which the analog dimming signal is input and
The analog dimming signal is multiplied by the first gain magnification to generate the current detection threshold voltage input to the seventh comparator, and the analog dimming signal is multiplied by the second gain magnification and input to the error amplifier. A comparison voltage generator that generates the current feedback voltage
With more
The light emitting element driving device according to claim 14, wherein the first gain magnification is twice the second gain magnification. A pull-down resistor connected to the 13th external terminal and
An eighth comparator having an input terminal connected to a connection node between the thirteenth external terminal and the pull-down resistor.
14. The light emitting element driving device according to claim 14 or 15. The light emitting element driving device according to claim 14, which is an IC package.
The external configuration
A current detection resistor whose end is connected to the second terminal of the switching element
A fifth capacitor, one end of which is connected to the other end of the coil,
The voltage dividing resistor connected to the other end of the fifth capacitor and
Including
The IC package is
A sealing material having a first side and a second side facing the first side,
The SEL terminal as the thirteenth external terminal and
The DGND terminal for taking the digital ground of the IC,
An FB terminal that is connected to the output end of the error amplifier used in the CCM mode and can be connected to an external sixth capacitor.
A ZT terminal that is used in the QR mode and can be connected to the connection node of the voltage dividing resistor.
Have,
The SEL terminal is arranged along the first side.
A light emitting element driving device in which the DGND terminal, the FB terminal, and the ZT terminal are arranged along the second side. The light emitting element driving device according to claim 17, wherein the FB terminal is arranged between the DGND terminal and the ZT terminal. The IC package is
The VCS terminal, which is the power supply terminal for the IC,
UVLO terminal for UVLO of the input voltage and
Have,
The light emitting element driving device according to claim 17 or 18, wherein the VCS terminal and the UVLO terminal are arranged along the first side. The first external terminal connected to the control terminal of the switching element,
A drive control unit that generates a drive signal that drives the switching element on and off and outputs it from the first external terminal.
With
The drive control unit includes a coil current correction unit that corrects the coil current by adjusting the drive signal based on a delay in the turnaround timing at which the coil current flowing through the coil changes from an increase to a decrease.
Light emitting element drive device. A light emitting part consisting of at least one light emitting element to which an input voltage is applied to one end,
A coil whose one end is connected to the other end of the light emitting portion,
A diode connected between the other end of the coil and one end of the light emitting portion,
A switching element having a first terminal connected to the other end of the coil,
A light emitting element driving device for driving the light emitting unit in an external configuration including the above.
A first external terminal connected to the control terminal of the switching element,
A drive control unit that generates a drive signal that drives the switching element on and off and outputs it from the first external terminal.
The second external terminal to which the selection input signal is input and
With
The drive control unit operates by switching between a QR mode (quasi-resonant: pseudo-resonant method) and a CCM mode (continuous current mode: continuous current mode) according to the selection input signal.
Light emitting element drive device. The external configuration further includes a current detection resistor one end connected to the second terminal of the switching element.
The drive control unit
The current detection signal generated by the current detection resistor is input, and the first comparator used in the QR mode and
The error amplifier used in the CCM mode in which the current detection signal is input and the first capacitor is connected to the output end, and
Have,
The light emitting element driving device is
The third external terminal to which the analog dimming signal is input and
The analog dimming signal is multiplied by the first gain magnification to generate the current detection threshold voltage input to the first comparator, and the analog dimming signal is multiplied by the second gain magnification and input to the error amplifier. A comparison voltage generator that generates the current feedback voltage
With more
The light emitting element driving device according to claim 21, wherein the first gain magnification is twice the second gain magnification. A pull-down resistor connected to the second external terminal and
A second comparator having an input terminal connected to a connection node between the second external terminal and the pull-down resistor, and
The light emitting element driving device according to claim 21 or 22, further comprising. The light emitting element driving device according to any one of claims 1 to 23,
A light emitting unit driven by the light emitting element driving device and
Light emitting device having. An electronic device having the light emitting device according to claim 24.

Images