JPWO2019230833A1 - Etching method of silicon semiconductor substrate, manufacturing method of semiconductor device and etching solution - Google Patents

Abstract

The etching method for a silicon semiconductor substrate of the present invention includes a step of forming a catalyst layer containing a noble metal layer on the surface of the silicon semiconductor substrate, and hydrofluoric acid and oxidation of the silicon semiconductor substrate on which the catalyst layer is formed on the surface. It includes a step of immersing the agent and an etching solution containing a surfactant of more than 0 ppm and less than 5 ppm.

Description

The present invention relates to an etching method for a silicon semiconductor substrate, a method for manufacturing a semiconductor device, and an etching solution.

In the manufacturing process of a semiconductor device, for the purpose of forming electrodes, for example, a silicon semiconductor substrate is deeply etched to form fine via holes. In the following, holes such as via holes formed by etching may be referred to as “etched holes”. As a method of deep digging etching, deep reactive ion etching (DRIE: Deep Reactive Ion Etching) can be mentioned. Deep reactive ion etching is a technology that can form cylindrical holes perpendicular to the surface of a silicon semiconductor substrate, but it is expensive because etching needs to be performed under vacuum and reactive gas must be used. Invite. Further, since it is necessary to repeat the etching step and the protection step of the etching portion, there is a problem that the productivity is low, that is, the throughput is low. Further, there is a problem that the side wall of the cylindrical hole obtained by etching becomes scalloped.

In recent years, a metal-assisted etching method has been developed as another method for deep-drilling etching. In the metal assist etching method, a catalyst pattern having a desired etching shape is formed on the surface of a silicon semiconductor substrate, and then the silicon semiconductor substrate on which the catalyst pattern is formed is etched containing hydrofluoric acid (HF) and an oxidizing agent. This is a method of immersing in a liquid. When immersed in the etching solution, the portion of the silicon semiconductor substrate in contact with the catalyst pattern is preferentially etched, and the catalyst moves downward as the etching progresses. As a result, via holes and the like can be formed in the depth direction of the silicon semiconductor substrate.

As the metal-assisted etching method, for example, in Patent Document 1, a catalyst layer made of a noble metal is formed on a structure made of a semiconductor, and the structure is made of hydrofluoric acid, an oxidizing agent, and an organic additive. An etching method including immersing in an etching solution containing the above-mentioned structure to remove a portion of the structure in contact with the catalyst layer is shown.

Japanese Unexamined Patent Publication No. 2016-58647

When producing penetrating or non-penetrating micropores having a high aspect ratio with respect to a silicon semiconductor substrate by the metal assist etching method, the etching is not performed perpendicularly to the surface of the silicon semiconductor substrate, and the central axis of the etching holes is , Sometimes deviated from the vertical direction. In particular, when a plurality of etching holes are formed at the same time, the above-mentioned problems may occur in some of the holes.

By the way, the metal assist etching method is also required to have a high etching rate and contribute to high productivity (high throughput) when it is adopted in a method for manufacturing a semiconductor device. The present invention has been made in view of such a situation, and an object of the present invention is an etching method capable of forming fine holes having a high aspect ratio in a productive manner perpendicular to the surface of a silicon semiconductor substrate. An object of the present invention is to provide an etching solution used in the etching method and a method for manufacturing a semiconductor device including the etching method.

In aspect 1 of the present invention, a step of forming a catalyst layer containing a noble metal layer on the surface of a silicon semiconductor substrate and a silicon semiconductor substrate having the catalyst layer formed on the surface thereof are subjected to hydrofluoric acid, an oxidizing agent, and 0 ppm. This is a method for etching a silicon semiconductor substrate, which comprises a step of immersing in an etching solution containing an ultra-5 ppm or less surfactant.

Aspect 2 of the present invention is the method for etching a silicon semiconductor substrate according to Aspect 1, wherein the surfactant is an ionic surfactant.

Aspect 3 of the present invention is the method for etching a silicon semiconductor substrate according to Aspect 1 or Aspect 2, wherein the etching solution contains 0.01 ppm or more of the surfactant.

Aspect 4 of the present invention is the method for etching a silicon semiconductor substrate according to any one of Aspects 1 to 3 in which the temperature of the etching solution is 0 ° C. or higher and 80 ° C. or lower.

In aspect 5 of the present invention, the catalyst layer is arranged on the surface of a silicon semiconductor substrate without one or a plurality of unit catalyst layers having one or more holes penetrating in the thickness direction contacting each other. The method for etching a silicon semiconductor substrate according to any one of aspects 1 to 4.

Aspect 6 of the present invention is the method for etching a silicon semiconductor substrate according to any one of aspects 1 to 5, wherein the unit catalyst layer has a circle-equivalent diameter of 1 micron or more and 10000 microns or less.

Aspect 7 of the present invention is the etching method for a silicon semiconductor substrate according to any one of aspects 1 to 6, wherein the holes penetrating in the thickness direction of the unit catalyst layer have a diameter equivalent to a circle of 5 nm or more and 10,000 nm or less.

Aspect 8 of the present invention is a method for manufacturing a semiconductor device including a step of etching a silicon semiconductor substrate by the etching method according to any one of aspects 1 to 7.

Aspect 9 of the present invention is an etching solution used for etching a silicon semiconductor substrate, which contains hydrofluoric acid, an oxidizing agent, and a surfactant of more than 0 ppm and not more than 5 ppm.

Aspect 10 of the present invention is the etching solution according to Aspect 9, wherein the surfactant is an ionic surfactant.

Aspect 11 of the present invention is the etching solution according to Aspect 9 or 10, which contains 0.01 ppm or more of the surfactant.

Aspect 12 of the present invention is the etching solution according to any one of aspects 9 to 11, wherein the surface active agent has a molecular weight of 100 or more and 20000 or less.

In aspect 13 of the present invention, the oxidizing agents are hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) _2. , Mg (NO ₃ ) ₂ , Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMnO ₄ , and K ₂ Cr ₂ O _7, which is one or more selected from the group consisting of 1 or more. The etching solution according to.

Aspect 14 of the present invention is the etching solution according to any one of Aspects 9 to 13, wherein the concentration of hydrofluoric acid is 0.1 mol / L or more and 20 mol / L or less.

Aspect 15 of the present invention is the etching solution according to any one of aspects 9 to 14, wherein the concentration of the oxidizing agent is 0.1 mol / L or more and 10 mol / L or less.

According to the etching method of the silicon semiconductor substrate of the present invention, micropores having a high aspect ratio can be formed with high productivity perpendicular to the plane of the silicon semiconductor substrate. Further, when the etching method of the silicon semiconductor substrate of the present invention is adopted in the manufacturing process of a semiconductor device such as an LSI, a semiconductor device having excellent characteristics can be manufactured with high throughput.

FIG. 1 is a schematic view of an etching method for a silicon semiconductor substrate of the present invention. FIG. 2 is an electron micrograph of Comparative Example 1, in which A is an electron micrograph of a cross section of an etching hole in the depth direction, B is an enlarged photograph of a broken line portion in A, and C is a plurality of etching holes. It is an electron micrograph of the surface of the silicon semiconductor substrate. FIG. 3 is an electron micrograph of a cross section of the etching hole in the depth direction in Example 1-1. FIG. 4 is an electron micrograph of a cross section of the etching hole of Comparative Example 2 in the depth direction. FIG. 5 is an electron micrograph of a cross section of the etching hole in the depth direction in Example 1-2. FIG. 6 is an electron micrograph of Example 1-3, where A is an electron micrograph of a cross section in the depth direction of the etching hole, and B is a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole. Electron micrograph, C is an electron micrograph showing cross sections of a plurality of etching holes. FIG. 7 is an electron micrograph of Example 2-1. A is an electron micrograph of a cross section of an etching hole in the depth direction, and B is an electron micrograph showing a cross section of a plurality of etching holes. .. FIG. 8 is an electron micrograph of a cross section of the etching hole in the depth direction in Example 2-2. FIG. 9 is an electron micrograph of Example 2-3, where A is an electron micrograph of a cross section in the depth direction of the etching hole, and B is a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole. An electron micrograph, C, is an electron micrograph of the surface of a silicon semiconductor substrate on which a plurality of etching holes are formed. FIG. 10 is an electron micrograph of Example 2-4, where A is an electron micrograph of a cross section in the depth direction of the etching hole, and B is a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole. It is an electron micrograph. FIG. 11 is an electron micrograph of Example 3, A is an electron micrograph of a cross section in the depth direction of the etching hole, and B is a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole. It is an electron micrograph, and C is an electron micrograph of the surface of a silicon semiconductor substrate in which a plurality of etching holes are formed.

The present inventors use a metal-assisted etching method to obtain fine holes having a high aspect ratio and being perpendicular to the plane of a silicon semiconductor substrate (hereinafter, this characteristic may be referred to as "high verticality"). , We made a diligent study to form it with good productivity without lowering the etching rate. As a result, the etching method for silicon semiconductor substrates has become
A process of forming a catalyst layer containing a precious metal layer on the surface of a silicon semiconductor substrate;
A step of immersing the silicon semiconductor substrate having the catalyst layer formed on the surface in an etching solution containing hydrofluoric acid, an oxidizing agent, and a surfactant containing more than 0 ppm and not more than 5 ppm;
I found that it should be included.

The method for etching a silicon semiconductor substrate of the present invention is particularly characterized in that an etching solution containing hydrofluoric acid, an oxidizing agent, and a surfactant containing more than 0 ppm and not more than 5 ppm is used. Hereinafter, the etching solution used for etching the silicon semiconductor substrate, the etching method for the silicon semiconductor substrate, and the manufacturing method for the semiconductor device will be described.

The etching solution of the present invention contains hydrofluoric acid, an oxidizing agent, and a surfactant of more than 0 ppm and not more than 5 ppm. In particular, it is characterized in that it contains a surfactant in a mass ratio of more than 0 ppm and 5 ppm or less with respect to the total amount of the etching solution.

By adding the trace amount of the surfactant to the etching solution, fine pores having a high aspect ratio and high verticality can be formed. On the other hand, when the present inventors examined the effect of the surfactant in the metal-assisted etching method, the surfactant has an etching suppressing effect, and if it is contained in a large amount, the etching is suppressed and the etching rate is lowered. I found that. Further, as shown in Examples described later, when the concentration of the surfactant was changed and the effect of the concentration on the etching rate was examined, when the concentration of the surfactant exceeded 5 ppm and was, for example, 10 ppm, the etching rate was high. We have found that it can drop sharply.

The concentration of the surfactant may not exceed 5 ppm, but is preferably 0.01 ppm or more from the viewpoint of more reliably exerting the effect of forming the highly vertical micropores. The concentration of the surfactant is more preferably 0.10 ppm or more, still more preferably 0.50 ppm or more.

Examples of the surfactant include nonionic surfactants and ionic surfactants. Examples of the ionic surfactant include anionic surfactant, cationic surfactant, and amphoteric surfactant. The surfactant may be a mixture thereof.

As the anionic surfactant, a sulfate ester type surfactant such as sodium laurylsulfate, sodium myristylsulfate, sodium pentadecylsulfate, sodium octylsulfate, sodium polyoxyethylene alkylphenol sulfonate, sodium laurylsulfate, ammonium laurylsulfate; dodecyl Sodium benzene sulfonate, sodium 1-hexane sulfonate, sodium 1-octane sulfonate, sodium 1-decane sulfonate, sodium 1-dodecyl sulfonate, perfluorobutane sulfonic acid, sodium linear alkylbenzene sulfonate, sodium toluene sulfonate, Sulphonic acid-type interfaces such as sodium cumylbenzene sulfonate, sodium octylbenzene sulfonate, sodium naphthalene sulfonate, disodium naphthalenedyl sulfonate, trisodium naphthalene trisulfonate, sodium butyl naphthalene sulfonate, and perfluorooctane sulfonic acid (PFOS). Activators; fatty acid salt-type surfactants such as sodium oleate, sodium laurate, sodium caprate, sodium caprylate, sodium caproate, potassium stearate, calcium oleate; lauryl phosphate, sodium lauryl phosphate, lauryl Phosphyl ester-type surfactants such as potassium phosphate; can be mentioned.

As the cationic surfactant, a quaternary ammonium salt type surfactant such as benzalkonium chloride, tetramethylammonium chloride, hexadecyltrimethylammonium bromide, benzethonium chloride; monomethylamine hydrochloride, dimethylamine hydrochloride , Alkylamine salt-type surfactants such as trimethylamine hydrochloride; pyridine-type surfactants containing butylpyridinium chloride, dodecylpyridinium chloride, and cetylpyridinium chloride;

Examples of the amphoteric surfactant include alkyl betaine-type surfactants such as lauryldimethylaminoacetate betaine and stearyldimethylaminoacetic acid betaine; and fatty acid amide betaine-type surfactants such as cocamidopropyl betaine and lauric acid amidopropyl betaine; Alkylimidazole-type surfactants such as 2-alkyl-N-carboxymethyl-N-hydroxyethyl imidazolinium betaine; amino acid-type surfactants such as sodium lauroyl glutamate and lauroyl methyl-β-alanine; lauryldimethylamine N-oxide, oleyl Examples thereof include alkylamine oxides such as dimethylamine N-oxide and sulfobetaine-type surfactants such as amidopropyl hydroxysulfobetaine laurate.

As the nonionic surfactant, polyoxyalkylene ether such as polyethylene glycol and polypropylene glycol, polyoxyethylene alkyl ether such as polyoxyethylene lauryl ether, polyoxyethylene alkylphenyl ether such as polyoxyethylene nonylphenyl ether, and poly Ether-type surfactants such as polyoxyethylene polyoxypropylene alkyl ethers such as oxyethylene polyoxypropylene lauryl ether; glycerin fatty acid esters such as glyceryl stearate, sorbitan fatty acid esters such as sorbitan laurate, sucrose lauric acid esters, etc. Esther-type surfactants such as sucrose fatty acid esters; Polyethylene glycol fatty acids such as polyethylene glycol stearate, ester ether-type surfactants such as polyoxyethylene sorbitan monolaurate; Examples include type surfactants.

Sodium lauryl sulfate, benzalkonium chloride, and polyethylene glycol are preferably used as the surfactant. More preferably, it is an ionic surfactant, and among them, one or more of sodium lauryl sulfate and benzalkonium chloride is further preferable.

The molecular weight of the surfactant is preferably in the range of 100 or more and 20000 or less. The molecular weight of the surfactant is more preferably 200 or more and 10000 or less. When the surfactant is a polymer compound, its molecular weight is the weight average molecular weight.

The concentration of hydrofluoric acid is preferably in the range of 0.1 mol / L or more and 20 mol / L or less, more preferably in the range of 0.1 mol / L or more and 10 mol / L or less, and further preferably in the range of 0.1 mol / L or more and 10 mol / L or less. It is in the range of 0.5 mol / L or more and 5 mol / L or less, more preferably 1.0 mol / L or more and 3 mol / L or less. When the concentration of hydrofluoric acid is low, it is difficult to achieve a high etching rate. If the concentration of hydrofluoric acid is high, peeling of the catalyst layer may occur.

Oxidizing agents are hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg (NO ₃ ) ₂ , It is preferably 1 or more selected from the group consisting of Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMn _{O 4} , and K ₂ Cr ₂ O _7. Among them, hydrogen peroxide is preferable.

The concentration of the oxidizing agent is preferably in the range of 0.1 mol / L or more and 10 mol / L or less, more preferably 0.5 mol / L or more and 10 mol / L or less, still more preferably 1.0 mol / L. It is in the range of 5 mol / L or less, more preferably 1.0 mol / L or more and 3 mol / L or less.

The etching solution of the present invention may contain the hydrofluoric acid, the oxidizing agent, and the surfactant of more than 0 ppm and not more than 5 ppm, and other additives are not particularly limited. Examples of the solvent include water, alcohol, acetone, toluene, chloroform and hexane. As described above, the etching solution of the present invention does not contain a surfactant exceeding 5 ppm. As the additive, for example, a pH buffer may be contained in order to reduce the pH fluctuation of the bath. As the pH buffer, phosphoric acid, boric acid, acetic acid, tartaric acid, citric acid, and one or more of these alkali metal salts can be used.

As an embodiment of the etching solution of the present invention, for example, the additive is an aqueous solution consisting of the hydrofluoric acid, the oxidizing agent, and a surfactant of more than 0 ppm and 5 ppm or less, or the hydrofluoric acid, the oxidizing agent, more than 0 ppm. Examples thereof include an aqueous solution composed of a surfactant of 5 ppm or less and the pH buffer.

The etching method for the silicon semiconductor substrate of the present invention is
The process of forming a catalyst layer made of precious metal on the surface of a silicon semiconductor substrate;
The step of immersing the semiconductor substrate having the catalyst layer formed on the surface in an etching solution containing hydrofluoric acid, an oxidizing agent, and a surfactant of more than 0 ppm and not more than 5 ppm;

The etching method of the silicon semiconductor substrate of the present invention using the above etching solution will be described below with reference to FIGS. 1A to 1F which are schematic views. However, the present invention is not limited to the embodiments shown in these drawings, and can be modified without departing from the object of the present invention.

For convenience of explanation, FIGS. 1A to 1F below show an embodiment in which one unit catalyst layer having a plurality of holes penetrating in the thickness direction is formed on the surface of a silicon semiconductor substrate as a catalyst layer. Further, in FIGS. 1A to 1F, a cross section including the diameter of the circular unit catalyst layer is shown so as to be easily understood.

First, a silicon semiconductor substrate 1 is prepared (FIG. 1A), a resist 2 is applied to the surface of the silicon semiconductor substrate 1 (FIG. 1B), and photolithography is performed so that the resist 2 remains in a portion other than the planned catalyst layer formation portion. (Fig. 1C). In FIG. 1C, a through-hole forming resist 2A is provided for forming a unit catalyst layer having a plurality of holes penetrating in the thickness direction.

Next, as shown in FIG. 1D, the noble metal for forming the catalyst layer is deposited by, for example, a sputtering method to form the noble metal layer 3. The method for depositing the noble metal is not limited to this, and a vapor deposition method can be used in addition to a plating method such as electrolytic plating and electroless plating. Then, as shown in FIG. 1E, the resist is removed (lifted off) to form the catalyst layer 4. The type of resist, the method of photolithography, the method of removing the resist, and the like are not particularly limited, and normally used conditions can be adopted.

In the present invention, the noble metal is composed of gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), osmium (Os), and iridium (Ir). One or more pure metals or alloys selected from the group.

In the present invention, the catalyst layer may include a noble metal layer. In FIG. 1D, only the noble metal layer is formed, but the present invention is not limited to this, and the noble metal layer 3 may be laminated with another metal layer as the catalyst layer. Examples of the metal constituting the other metal layer include Ti, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Hf, Ta, W, Re, Included is one or more pure metals or alloys selected from the group consisting of Sn, Sb, In.

The thickness of the catalyst layer 4 can be, for example, 3 nm or more and 500 nm or less, and further 10 nm or more and 200 nm or less. When the catalyst layer 4 is a laminate of a noble metal layer and another metal layer, the thickness means the total thickness.

The catalyst layer in the present invention is preferably one in which one or more unit catalyst layers having one or more holes penetrating in the thickness direction are arranged on the surface of the silicon semiconductor substrate without contacting each other. The holes penetrating in the thickness direction are holes for allowing the etching solution to permeate when immersed in the etching solution. Hereinafter, it is referred to as "etching liquid permeation hole".

The shape of the unit catalyst layer is not particularly limited, and examples thereof include a circular shape, a polygonal shape, and a rectangular shape. A circular film is preferable. The circle-equivalent diameter of the unit catalyst layer is preferably 1 micron or more and 10000 microns or less. The circle-equivalent diameter of the unit catalyst layer means the diameter of a circle having the same area as the unit catalyst layer having the shape.

When a plurality of unit catalyst layers are arranged on the surface of a silicon semiconductor substrate without contacting each other, the unit catalyst interlayer pitch is preferably in the range of, for example, 0.25 micron or more and 1000 microns or less.

The shape of the etching solution permeation hole provided in the unit catalyst layer is not particularly limited, and examples thereof include a circular shape, a polygonal shape, and a rectangular shape. It is preferably a circular hole. The equivalent circle diameter of the etching solution permeation hole is preferably 5 nm or more and 10000 nm or less. The circle-equivalent diameter of the etching solution permeation hole means the diameter of a circle having the same area as the etching solution permeation hole of the shape.

The density of the number of etching solution permeation holes provided in the unit catalyst layer can be, for example, 0.1 or more and 10,000 or less per 1 square micrometer, depending on the size of the holes.

When a plurality of holes for permeating the etching solution are provided in the unit catalyst layer, it is preferable that these are arranged without being in contact with each other as shown in FIG. 1E. In this case, the inter-hole pitch for permeating the etching solution is preferably in the range of, for example, 10 nm or more and 10000 nm or less.

By immersing the silicon semiconductor substrate 1 on which the catalyst layer 4 shown in FIG. 1E is formed on the surface in the etching solution of the present invention described above, the etching solution permeates through the etching solution permeation holes 5 and the silicon semiconductor substrate. It penetrates between 1 and the catalyst layer 4. As a result, as shown in FIG. 1F, the portion of the silicon semiconductor substrate 1 in contact with the catalyst layer 4 is preferentially etched, and the catalyst layer 4 moves downward as the etching progresses to the depth of the silicon semiconductor substrate 1. It can be etched in the longitudinal direction. Ultrasonic rocking may also be performed for the purpose of promoting the permeation. Since the etching solution permeation hole 5 is minute, the silicon semiconductor substrate 1 immediately below the hole is also etched, and a cylindrical etching hole 6 can be formed as illustrated in FIG. 1F.

The temperature of the etching solution is preferably 0 ° C. or higher, more preferably 20 ° C. or higher. Further, it is preferably 80 ° C. or lower, and more preferably 60 ° C. or lower.

The immersion time in the etching solution depends on the desired shape of the etching holes, but can be, for example, within the range of 1 hour or more and 100 hours or less.

Conditions other than the above in each step and steps other than the above are not particularly limited. After the immersion in the etching solution, a step such as cleaning can be provided. Examples of the method for removing the catalyst layer after etching include a method in which the catalyst layer is dissolved in an iodine or nitric acid-based solution and then washed with pure water or the like.

According to the method of the present invention, it is possible to obtain a silicon semiconductor substrate that is perpendicular to the plane of the silicon semiconductor substrate and has fine and high aspect ratio etching holes. The etching holes may or may not penetrate in the plate thickness direction of the silicon semiconductor substrate. As the etching hole
-The diameter equivalent to a circle is 0.1 micron or more and 10000 microns or less, further 1 micron or more, 1000 microns or less, and
-Depth is 1 micron or more, 1000 microns or less, especially depth is 10 microns or more, 500 microns or less, and
-It is possible to realize a shape having an aspect ratio of 0.1 or more, further 100 or more, and further 500 or more.

The present invention also includes a method for manufacturing a semiconductor device, which includes a step of etching a silicon semiconductor substrate by the etching method. A known method can be adopted as a method of embedding the electrode material in the etching holes after the etching step. When the etching hole is a through hole penetrating in the plate thickness direction of the silicon semiconductor substrate, an electrode material is embedded in the through hole to form a through silicon via (TSV), and for example, a three-dimensional LSI is manufactured. Can be mentioned.

According to the steps shown in FIGS. 1A to 1E, first, a sample for immersion in the etching solution was prepared. Specifically, the following catalyst layer was formed on the surface of a silicon semiconductor substrate having a size of 5 cm square. The catalyst layer is obtained by laminating Au (gold) with a thickness of 10 nm and Ti with a thickness of 10 nm. In this embodiment, as the catalyst layer, a plurality of unit catalyst layers having a plurality of holes (holes for permeating the etching solution) penetrating in the thickness direction are formed on the surface of the silicon semiconductor substrate without being in contact with each other. The sizes of the unit catalyst layer and the holes for permeating the etching solution provided in the unit catalyst layer are as follows.
Unit catalyst layer size: Circular shape with a diameter of about 10,000 nm Unit catalyst interlayer pitch: 100 to 200 microns Etching liquid penetration hole size: Circular shape with a diameter of about 2000 nm or less Etching liquid penetration hole pitch: Approximately 500 nm

Using the above-mentioned etching solution immersion sample, the etching solution was immersed in the etching solution shown in each of the following examples for each time to form etching holes. The temperature of the etching solutions was 40 ° C.

After cleaning after etching, processing was performed so that the cross section of the etching hole could be observed, and the cross section was photographed by SEM. Then, in the above photograph, the verticality of the etching holes was evaluated, and the etching rate was evaluated from the etching depth. In some examples, a photograph taken with the catalyst layer (unit catalyst layer) left on the bottom surface of the etching holes and a photograph in which a plurality of etching holes are observed are also shown.

(Comparative Example 1)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF) and 1.7 mol / L of hydrogen peroxide as an etching solution and not containing a surfactant. The results are shown in FIGS. 2A-2C. FIG. 2A is an electron micrograph of a cross section of the etching hole in the depth direction, and FIG. 2B is an enlarged photograph of a broken line portion in FIG. 2A. Further, FIG. 2C is an electron micrograph of the surface of the silicon semiconductor substrate in which a plurality of etching holes are formed. As shown in FIGS. 2A and 2C, when the surfactant specified in the present invention was not contained, the etching holes deviated from the direction perpendicular to the surface of the silicon semiconductor substrate, resulting in a shape having low verticality. Further, as shown in FIG. 2B, the unit catalyst layer after etching had a shrunk shape without maintaining a flat surface.

(Example 1-1)
Etching was performed for 30 minutes using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 1 ppm of sodium lauryl sulfate as an etching solution. As a result, FIG. 3 shows an electron micrograph of a cross section of the etching hole in the depth direction.

(Comparative Example 2)
Etching was performed for 30 minutes using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 10 ppm of sodium lauryl sulfate as an etching solution. As a result, FIG. 4 shows an electron micrograph of a cross section of the etching hole in the depth direction.

The concentration of sodium lauryl sulfate, which is a surfactant, is different between Example 1-1 and Comparative Example 2. From the comparison of these results, it can be seen that when the concentration of the surfactant is 10 ppm (Comparative Example 2), the etching rate is extremely slow and high throughput cannot be achieved.

(Example 1-2)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 0.1 ppm of sodium lauryl sulfate as an etching solution. As a result, FIG. 5 shows an electron micrograph of a cross section of the etching hole in the depth direction.

(Example 1-3)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 1.0 ppm of sodium lauryl sulfate as an etching solution. The results are shown in FIGS. 6A to 6C. FIG. 6A is an electron micrograph of a cross section in the depth direction of the etching hole, FIG. 6B is an electron micrograph of a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole, and FIG. 6C is a plurality of electron micrographs. It is an electron micrograph which showed the cross section of the etching hole.

(Example 2-1)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 0.1 ppm of benzalkonium chloride as the etching solution. The results are shown in FIGS. 7A and 7B. FIG. 7A is an electron micrograph of a cross section of the etching hole in the depth direction, and FIG. 7B is an electron micrograph showing a cross section of a plurality of etching holes.

(Example 2-2)
Etching was performed for 30 minutes using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 1.0 ppm of benzalkonium chloride as the etching solution. As a result, FIG. 8 shows an electron micrograph of a cross section of the etching hole in the depth direction.

(Example 2-3)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 1.0 ppm of benzalkonium chloride as the etching solution. The results are shown in FIGS. 9A-9C. FIG. 9A is an electron micrograph of a cross section in the depth direction of the etching hole, FIG. 9B is an electron micrograph of a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole, and FIG. 9C is a plurality of electron micrographs. It is an electron micrograph of the surface of a silicon semiconductor substrate in which etching holes are formed.

(Example 2-4)
Etching was performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 2.0 ppm of benzalkonium chloride as the etching solution. The results are shown in FIGS. 10A and 10B. FIG. 10A is an electron micrograph of a cross section in the depth direction of the etching hole, and FIG. 10B is an electron micrograph of a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole.

(Example 3)
Etching is performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 5.0 ppm of polyethylene glycol 1000 (molecular weight 1000) as an etching solution. went. The results are shown in FIGS. 11A to 11C. FIG. 11A is an electron micrograph of a cross section in the depth direction of the etching hole, FIG. 11B is an electron micrograph of a catalyst layer (unit catalyst layer) existing on the bottom surface of the etching hole, and FIG. 11C is a plurality of electron micrographs. It is an electron micrograph of the surface of a silicon semiconductor substrate in which etching holes are formed.

(Comparative Example 3)
Etching is performed for 2 hours using an aqueous solution containing 1.0 mol / L of hydrofluoric acid (HF), 1.7 mol / L of hydrogen peroxide, and 10.0 ppm of polyethylene glycol 1000 (molecular weight 1000) as an etching solution. went. As a result, the shape of the etching holes was almost the same as that of Example 3, but the etching rate was about 10% slower than that of Example 3.

As shown in the results of Examples 1-2 to 3, the silicon semiconductor substrate can be made of a silicon semiconductor substrate by using an etching solution containing the concentration of the surfactant within the range of 5 ppm or less regardless of the type of the surfactant. It was possible to form fine and high aspect ratio etching holes perpendicular to the plane with high productivity. Preferably, by using an ionic surfactant such as sodium lauryl sulfate or benzalkonium chloride, it is fine, has a high aspect ratio, has high verticality, and has an upper portion in the depth direction cross section of the etching hole. The widths of the etching holes at the bottom were almost equal, and it was possible to realize a shape in which the taper that could occur downward was sufficiently suppressed.

This application is accompanied by a priority claim based on Japanese Patent Application No. 2018-105387. Japanese Patent Application No. 2018-105387 is incorporated herein by reference.

1 Silicon semiconductor substrate 2 Resist 2A Resist for forming through holes 3 Noble metal 4 Catalyst layer 5 Etching liquid penetration hole 6 Etching hole

Claims (15)

The process of forming a catalyst layer containing a precious metal layer on the surface of a silicon semiconductor substrate, and
A step of immersing the silicon semiconductor substrate having the catalyst layer formed on the surface in an etching solution containing hydrofluoric acid, an oxidizing agent, and a surfactant containing more than 0 ppm and not more than 5 ppm.
Etching method for silicon semiconductor substrates including. The method for etching a silicon semiconductor substrate according to claim 1, wherein the surfactant is an ionic surfactant. The method for etching a silicon semiconductor substrate according to claim 1 or 2, wherein the etching solution contains 0.01 ppm or more of the surfactant. The method for etching a silicon semiconductor substrate according to any one of claims 1 to 3, wherein the temperature of the etching solution is 0 ° C. or higher and 80 ° C. or lower. Any of claims 1 to 4, wherein the catalyst layer is formed by arranging one or a plurality of unit catalyst layers having one or more holes penetrating in the thickness direction on the surface of a silicon semiconductor substrate without contacting each other. The method for etching a silicon semiconductor substrate according to the above. The method for etching a silicon semiconductor substrate according to any one of claims 1 to 5, wherein the unit catalyst layer has a circle-equivalent diameter of 1 micron or more and 10000 microns or less. The method for etching a silicon semiconductor substrate according to any one of claims 1 to 6, wherein the holes penetrating in the thickness direction of the unit catalyst layer have a circle-equivalent diameter of 5 nm or more and 10,000 nm or less. A method for manufacturing a semiconductor device, which comprises a step of etching a silicon semiconductor substrate by the etching method according to any one of claims 1 to 7. An etching solution used for etching silicon semiconductor substrates.
An etching solution containing hydrofluoric acid, an oxidizing agent, and a surfactant of more than 0 ppm and less than 5 ppm. The etching solution according to claim 9, wherein the surfactant is an ionic surfactant. The etching solution according to claim 9 or 10, which contains 0.01 ppm or more of the surfactant. The etching solution according to any one of claims 9 to 11, wherein the surface active agent has a molecular weight of 100 or more and 20000 or less. The oxidizing agents are hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg (NO ₃ ) _2. The etching solution according to any one of claims 9 to 12, which is one or more selected from the group consisting of, Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMnO ₄ , and K ₂ Cr ₂ O _7. The etching solution according to any one of claims 9 to 13, wherein the concentration of hydrofluoric acid is 0.1 mol / L or more and 20 mol / L or less. The etching solution according to any one of claims 9 to 14, wherein the concentration of the oxidizing agent is 0.1 mol / L or more and 10 mol / L or less.

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