WO2023153203A1 - Substrate processing method and substrate processing apparatus - Google Patents

Substrate processing method and substrate processing apparatus Download PDF

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Publication number
WO2023153203A1
WO2023153203A1 PCT/JP2023/002185 JP2023002185W WO2023153203A1 WO 2023153203 A1 WO2023153203 A1 WO 2023153203A1 JP 2023002185 W JP2023002185 W JP 2023002185W WO 2023153203 A1 WO2023153203 A1 WO 2023153203A1
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Prior art keywords
substrate
etchant
silicon oxide
etching
film
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PCT/JP2023/002185
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French (fr)
Japanese (ja)
Inventor
祐希 吉田
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東京エレクトロン株式会社
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Priority to KR1020247029536A priority Critical patent/KR20240141316A/en
Priority to JP2023580158A priority patent/JPWO2023153203A1/ja
Priority to CN202380019350.XA priority patent/CN118633144A/en
Publication of WO2023153203A1 publication Critical patent/WO2023153203A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02019Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67075Apparatus for fluid treatment for etching for wet etching
    • H01L21/67086Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/6773Conveying cassettes, containers or carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins

Definitions

  • the present disclosure relates to a substrate processing method and a substrate processing apparatus.
  • Patent Document 1 there is known a technique of etching a silicon oxide film formed on a substrate such as a semiconductor wafer with an etchant containing, for example, hydrofluoric acid (see Patent Document 1).
  • the present disclosure provides a technique for etching a laminated film including a plurality of silicon oxide films with different film thicknesses, which can reduce variations in etching rate for each silicon oxide film.
  • a substrate processing method includes a step of preparing a substrate and a step of etching the substrate.
  • the step of preparing a substrate prepares a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses.
  • the substrate is etched with an etchant to which hydrochloric acid is added.
  • FIG. 1 is an explanatory diagram of substrate processing according to the embodiment.
  • FIG. 2 is an explanatory diagram of substrate processing according to the embodiment.
  • FIG. 3 is a graph showing variations in etching rate for each silicon oxide film when using an etchant to which hydrochloric acid and a metal salt are added.
  • FIG. 4 is a graph showing variations in etching rate for each silicon oxide film when using an etchant to which hydrochloric acid and a metal salt are added.
  • FIG. 5 is a diagram for explaining the formation of water clusters.
  • FIG. 6 is a diagram for explaining the formation of spherical structures.
  • FIG. 7 is a diagram for explaining how the surface potential of a portion of the polysilicon film shifts from negative to positive.
  • FIG. 1 is an explanatory diagram of substrate processing according to the embodiment.
  • FIG. 2 is an explanatory diagram of substrate processing according to the embodiment.
  • FIG. 3 is a graph showing variations in etching rate for each silicon oxide film when using
  • FIG. 8 is a graph showing variations in etching rate for each silicon oxide film when using an etchant containing a surfactant.
  • FIG. 9 is a graph showing variations in etching rate for each silicon oxide film when using an etchant containing a surfactant.
  • FIG. 10 is a diagram showing the configuration of the substrate processing apparatus according to the embodiment.
  • FIG. 11 is a diagram showing the configuration of a processing bath according to the embodiment.
  • FIG. 12 is a flow chart showing the procedure of processing executed by the substrate processing apparatus according to the embodiment.
  • FIG. 13 is a diagram illustrating a configuration example of a processing unit according to a modification;
  • FIGS. 1 and 2 are explanatory diagrams of substrate processing according to the embodiment.
  • a semiconductor wafer (hereinafter referred to as wafer W) having the structure shown in FIG. 1 is prepared.
  • the wafer W is constructed by forming a plurality of silicon oxide films 11 and a plurality of polysilicon films 12 on a silicon substrate 10 .
  • a plurality of silicon oxide films 11 are formed on the silicon substrate 10 at intervals in the vertical direction.
  • the plurality of silicon oxide films 11 have different film thicknesses.
  • the film thickness of the plurality of silicon oxide films 11 is, for example, 1 nm or more and 30 nm or less.
  • the polysilicon film 12 is formed adjacent to each of the plurality of silicon oxide films 11 in the vertical direction. Since the plurality of silicon oxide films 11 have different film thicknesses, the polysilicon films 12 in contact with each of the plurality of silicon oxide films 11 are formed with different intervals therebetween.
  • the wafer W to be subjected to substrate processing has a laminated film in which the silicon oxide film 11 and the polysilicon film 12 are alternately laminated.
  • the wafer W may be a laminated film including at least a plurality of silicon oxide films 11 having different film thicknesses, and the structure of the laminated film is not particularly limited to the example shown in FIG.
  • a silicon film, a silicon nitride film, a metal-containing film, or the like can be used as other films formed adjacent to each of the plurality of silicon oxide films 11, in addition to the polysilicon film 12 described above. That is, the other film can be selected from at least one of a silicon film, a polysilicon film, a silicon nitride film and a metal-containing film.
  • the wafer W is formed with grooves 15 through which the etchant penetrates to etch the laminated silicon oxide film 11 .
  • the substrate processing according to the embodiment selectively etches the silicon oxide film 11 by an etching process using an etchant.
  • the end face of the silicon oxide film 11 facing the trench 15 recedes from the end face of the polysilicon film 12 facing the trench 15 in the width direction of the trench 15 , and the polysilicon film 12 is flattened. The upper and lower surfaces of the ends are exposed.
  • the variation in etching rate for each silicon oxide film 11 increases. Specifically, the silicon oxide film 11 having a smaller thickness is less likely to be etched than the silicon oxide film 11 having a larger thickness.
  • each silicon oxide film 11 is reduced by etching the wafer W using an etching solution to which at least one of hydrochloric acid, a metal salt, and a surfactant is added. It was found that variation can be suppressed.
  • 3 and 4 are graphs showing variations in etching rate for each silicon oxide film 11 when using an etchant containing hydrochloric acid (HCl) and metal salt (NaCl or CaCl 2 ).
  • the vertical axis represents an etching rate ratio (ER ratio), which is an index value for determining variations in etching rate for each silicon oxide film 11 .
  • the etching rate ratio is the ratio of the etching rate of the silicon oxide film 11 having the smallest thickness to the etching rate of the silicon oxide film 11 having the largest thickness among the plurality of laminated silicon oxide films.
  • the etching rate ratio indicates that the closer the value is to 1, the smaller the variation in the etching rate for each silicon oxide film 11 is.
  • w/o Additives indicates the etching rate ratio in the laminated film when using an etching solution to which hydrochloric acid and metal salt are not added.
  • HCl indicates the etching rate ratio in the laminated film when using an etching solution to which hydrochloric acid (HCl) is added.
  • NaCl indicates the etching rate ratio in the laminated film when using an etchant to which NaCl is added as a metal salt.
  • CaCl 2 indicates the etching rate ratio in the laminated film when using an etchant to which CaCl 2 is added as a metal salt.
  • FIG. 3 shows experimental results when the concentration of hydrochloric acid and metal salt in the etching solution is 0.05 wt %, and FIG. %.
  • the etching rate ratio when using the etching solution to which NaCl is added as a metal salt is higher than the etching rate ratio when using the etching solution to which neither hydrochloric acid nor metal salt is added. big in comparison.
  • the etching rate ratio when using an etching solution to which CaCl 2 is added as a metal salt is higher than the etching rate ratio when using an etching solution to which neither hydrochloric acid nor a metal salt is added. big in comparison.
  • FIG. 4 shows that the etching rate ratio when using an etching solution to which CaCl 2 is added as a metal salt is added.
  • the etching rate ratio in the case of using the etching solution to which hydrochloric acid (HCl) is added is compared to the etching rate ratio in the case of using the etching solution to which neither hydrochloric acid nor metal salt is added. big.
  • HCl hydrochloric acid
  • FIGS. 3 and 4 by etching the wafer W using the etchant to which NaCl is added as a metal salt, variations in the etching rate for each silicon oxide film 11 can be suppressed. It is understood that Further, from the experimental results shown in FIG.
  • the etching mechanism of the silicon oxide film 11 proceeds as follows. First, as shown in chemical reaction formula (1), silicon oxide (SiO 2 ) reacts with hydrofluoric acid (HF) contained in the etchant and dissolves in the etchant. In other words, silicon oxide film 11 is etched.
  • chemical reaction formula (1) silicon oxide (SiO 2 ) reacts with hydrofluoric acid (HF) contained in the etchant and dissolves in the etchant. In other words, silicon oxide film 11 is etched.
  • hydrogen difluoride ions (HF 2 ⁇ ) are generated by the reactions represented by the chemical reaction formulas (2) and (3).
  • the etching of the silicon oxide film 11 proceeds by promoting the reaction between silicon oxide (SiO 2 ) and hydrofluoric acid (HF) by the etchant hydrogen difluoride ions (HF 2 ⁇ ). . Therefore, in order for the etching of the silicon oxide film 11 to progress, it is important that the hydrogen difluoride ions (HF 2 ⁇ ) reach the silicon oxide film 11 .
  • FIG. 5 is a diagram for explaining the formation of water clusters. Water clusters 16p are formed more densely as the distance between polysilicon films 12 in contact with silicon oxide film 11 is narrower, in other words, as the film thickness of silicon oxide film 11 is smaller.
  • the water clusters 16p may prevent the hydrogen difluoride ions (HF 2 ⁇ ) from reaching the silicon oxide film 11 .
  • the etching rate of the silicon oxide film 11 with a smaller thickness is lower than the etching rate of the silicon oxide film 11 with a larger thickness.
  • the etching rate of each silicon oxide film 11 varies.
  • metal ions eg, Na +
  • anions eg, Cl ⁇
  • Anions for example, Cl ⁇
  • metal ions (eg, Na + ) generated from the metal salt in the etching solution combine with water molecules (that is, hydrate) on the surface of the polysilicon film 12, as shown in FIG.
  • FIG. 6 is a diagram for explaining the formation of spherical structures.
  • the spherical structures 16s are formed on the surface of the polysilicon film 12, even if the thickness of the silicon oxide film 11 is small, the space through which hydrogen difluoride ions (HF 2 ⁇ ) can pass increases. , the arrival of hydrogen difluoride ions (HF 2 ⁇ ) to the silicon oxide film 11 is not hindered. As a result, it is considered that the variation in the etching rate for each silicon oxide film 11 is reduced as compared with the case of using an etchant to which no metal salt is added.
  • FIG. 7 is a diagram for explaining how the surface potential of a portion of the polysilicon film shifts from negative to positive.
  • oxonium ions H 3 O +
  • the space through which the hydrogen difluoride ions (HF 2 ⁇ ) can pass increases, and the hydrogen difluoride ions (HF 2 ⁇ ) pass through the silicon oxide film. Reaching 11 is not hindered. As a result, it is considered that the variation in the etching rate for each silicon oxide film 11 is reduced as in the case of using an etchant to which a metal salt is added.
  • FIGS. 8 and 9 are graphs showing variations in etching rate for each silicon oxide film 11 when using an etchant to which a surfactant (OACl, OTMACl or SDBS) is added.
  • a surfactant OACl, OTMACl or SDBS
  • the processing conditions for the experimental results shown in FIGS. 8 and 9 are the same as the processing conditions for the experimental results shown in FIGS. 3 and 4, except for the following points.
  • Surfactants added to the etchant n-octylamine hydrochloride (OACl), n-octyltrimethylammonium chloride (OTMACl) or sodium dodecylbenzenesulfonate (SDBS)
  • the vertical axis represents an etching rate ratio (ER ratio), which is an index value for determining variations in etching rate for each silicon oxide film 11 .
  • the etching rate ratio is the ratio of the etching rate of the silicon oxide film 11 having the smallest thickness to the etching rate of the silicon oxide film 11 having the largest thickness among the plurality of laminated silicon oxide films.
  • the etching rate ratio indicates that the closer the value is to 1, the smaller the variation in the etching rate for each silicon oxide film 11 is.
  • w/o Additives indicates the etching rate ratio in the laminated film when using an etchant to which no surfactant is added.
  • OACl indicates the etching rate ratio in the laminated film when using an etchant to which OACl is added as a surfactant.
  • OTMACl indicates the etching rate ratio in the laminated film when using an etchant to which OTMACl is added as a surfactant.
  • SDBS indicates the etching rate ratio in the laminated film when using an etchant to which SDBS is added as a surfactant.
  • FIG. 8 shows the experimental results when the surfactant concentration in the etching solution is 0.05 wt %
  • FIG. 9 shows the experimental results when the surfactant concentration in the etching solution is 0.5 wt %. This is the result.
  • the etching rate ratio in the case of using the etchant to which OTMACl is added as a surfactant is higher than the etching rate ratio in the case of using the etchant to which no surfactant is added. big in comparison.
  • the etching rate ratio when using an etching solution to which OACl or SDBS is added as a surfactant is the etching rate ratio when using an etching solution to which no surfactant is added. large compared to As described above, from the experimental results shown in FIGS.
  • This experimental result is considered, for example, as follows. That is, when an etchant to which a surfactant is added is used, the surfactant in the etchant forms a hydration structure (that is, between water molecules) in the water clusters 16p (see FIG. 5) on the surface of the polysilicon film 12. bond).
  • the hydration structure in the water clusters 16p on the surface of the polysilicon film 12 is destroyed, even if the thickness of the silicon oxide film 11 is small, a space through which hydrogen difluoride ions (HF 2 ⁇ ) can pass. increases, and the arrival of hydrogen difluoride ions (HF 2 ⁇ ) to the silicon oxide film 11 is not hindered.
  • the variation in the etching rate for each silicon oxide film 11 is reduced as compared with the case of using an etchant to which no surfactant is added.
  • an etchant to which at least one of hydrochloric acid, a metal salt, and a surfactant is added is used to oxidize silicon. It was decided to perform an etching process for the film 11 .
  • the etchant according to the embodiment is a chemical solution containing hydrofluoric acid.
  • the concentration of hydrofluoric acid in the etchant is, for example, 0.1 wt % or more and 50 wt % or less.
  • an alkali metal halide or an alkaline earth metal halide can be used as the metal salt added to the etchant.
  • the alkali metal halide for example, NaCl mentioned above can be used.
  • the alkali metal halide may contain at least one of Li, Na, K, Rb and Cs.
  • the alkaline earth metal halide for example CaCl 2 as described above can be used.
  • the alkaline earth metal halide may contain at least one of Mg, Ca, Sr and Ba.
  • the concentration of each of hydrochloric acid and metal salt in the etching solution is preferably 0.5 wt % or more and 5 wt % or less. As is clear from the experimental results shown in FIGS. 3 and 4, this makes it possible to reduce variations in the etching rate for each silicon oxide film 11 regardless of the type of metal salt. Further, by setting the concentration of the metal salt in the etchant to 5 wt % or less, contamination of the wafer W with metal can be suppressed.
  • the concentration of hydrochloric acid before being added to the etching solution is preferably 35 wt % or more and 37 wt % or less, for example.
  • a cationic surfactant or an anionic surfactant can be used as the surfactant added to the etching solution.
  • a cationic surfactant for example, n-octylamine hydrochloride (OACl) or n-octyltrimethylammonium chloride (OTMACl) described above can be used.
  • an anionic surfactant for example, sodium dodecylbenzenesulfonate (SDBS) described above can be used.
  • the concentration of the surfactant in the etching liquid is preferably 0.5 wt % or more and 5 wt % or less. As is clear from the experimental results shown in FIGS. 8 and 9, this makes it possible to reduce variations in the etching rate for each silicon oxide film 11 regardless of the type of surfactant. Further, by setting the concentration of the surfactant in the etching liquid to 5 wt % or less, it is possible to suppress the organic matter (dirt) removed by the surfactant from remaining on the surface of the wafer W.
  • FIG. 10 is a diagram showing the configuration of the substrate processing apparatus according to the embodiment.
  • the substrate processing apparatus 1 includes a carrier loading/unloading unit 2, a lot forming unit 3, a lot placement unit 4, a lot transport unit 5, a lot processing unit 6, a control a part 7;
  • the carrier loading/unloading section 2 includes a carrier stage 20 , a carrier transport mechanism 21 , carrier stocks 22 and 23 , and a carrier table 24 .
  • the carrier stage 20 carries a plurality of carriers 9 transported from the outside.
  • the carrier 9 is a container that accommodates a plurality of (for example, 25) semiconductor wafers (hereinafter referred to as wafers W) arranged vertically in a horizontal posture.
  • the carrier transport mechanism 21 transports the carrier 9 among the carrier stage 20 , carrier stocks 22 and 23 and carrier table 24 .
  • a plurality of wafers W to be processed are unloaded to the lot processing section 6 by the substrate transport mechanism 30, which will be described later.
  • a plurality of processed wafers W are carried from the lot processing section 6 to the carrier 9 mounted on the carrier mounting table 24 by the substrate transfer mechanism 30 .
  • the lot formation unit 3 has a substrate transport mechanism 30 and forms lots.
  • a lot consists of a plurality of (for example, 50) wafers W that are processed simultaneously by combining wafers W housed in one or more carriers 9 .
  • a plurality of wafers W forming one lot are arranged at regular intervals with their plate surfaces facing each other.
  • the substrate transfer mechanism 30 transfers a plurality of wafers W between the carrier 9 mounted on the carrier mounting table 24 and the lot mounting section 4 .
  • the lot placing unit 4 has a lot transport table 40 and temporarily places (stands by) the lot transported between the lot forming unit 3 and the lot processing unit 6 by the lot transporting unit 5 .
  • the lot conveyance table 40 includes a loading-side lot mounting table 41 for mounting a lot formed by the lot forming section 3 before being processed, and an unloading-side lot mounting table for mounting a lot processed by the lot processing section 6. 42.
  • a plurality of wafers W for one lot are placed in a standing posture in front and behind on the load-in side lot table 41 and the carry-out side lot table 42 .
  • the lot transport unit 5 has a lot transport mechanism 50 and transports lots between the lot placement unit 4 and the lot processing unit 6 and inside the lot processing unit 6 .
  • the lot transport mechanism 50 has a rail 51 , a moving body 52 and a substrate holder 53 .
  • the rails 51 are arranged along the X-axis direction across the lot placement section 4 and the lot processing section 6 .
  • the moving body 52 is configured to be movable along the rails 51 while holding a plurality of wafers W. As shown in FIG.
  • the substrate holder 53 is provided on the moving body 52 and holds a plurality of wafers W arranged in front and back in an upright posture.
  • the lot processing unit 6 performs etching processing, cleaning processing, drying processing, etc. on a plurality of wafers W for one lot.
  • a plurality (here, two) of etching processing devices 60 , substrate holder cleaning processing devices 80 , and drying processing devices 90 are arranged side by side along rails 51 .
  • the etching processing apparatus 60 collectively performs etching processing on a plurality of wafers W for one lot.
  • the substrate holder cleaning apparatus 80 performs cleaning processing of the substrate holder 53 .
  • the drying processing apparatus 90 collectively performs drying processing on a plurality of wafers W for one lot.
  • the number of etching processing devices 60, substrate holder cleaning processing devices 80, and drying processing devices 90 is not limited to the example in FIG.
  • the etching processing apparatus 60 includes a processing bath 61 for etching processing, a processing bath 62 for rinsing processing, and substrate lifting mechanisms 63 and 64 .
  • the processing bath 61 and the processing bath 62 can accommodate one lot of wafers W, and store an etchant. An etchant is stored in the processing bath 61 . Details of the processing tank 61 will be described later.
  • a processing liquid (deionized water, etc.) for rinsing is stored in the processing tank 62 .
  • the substrate elevating mechanisms 63 and 64 hold a plurality of wafers W forming a lot in a state of being arranged back and forth in an upright posture.
  • the etching processing apparatus 60 holds the lot conveyed by the lot conveying unit 5 by the substrate lifting mechanism 63, immerses the lot in the etching solution in the processing bath 61, and performs etching processing.
  • the etching apparatus 60 holds the lot transported to the processing bath 62 by the lot transport unit 5 by the substrate lifting mechanism 64 and immerses the lot in the rinsing liquid of the processing bath 62 for rinsing.
  • the drying processing apparatus 90 has a processing bath 91 and a substrate lifting mechanism 92 .
  • a processing gas for drying is supplied to the processing bath 91 .
  • the substrate lifting mechanism 92 holds a plurality of wafers W for one lot side by side in the front-rear direction in an upright posture.
  • the drying processing device 90 holds the lot transported by the lot transporting unit 5 with the substrate lifting mechanism 92 and performs drying processing using the processing gas for drying processing supplied into the processing bath 91 .
  • the lot that has been dried in the processing tank 91 is transferred to the lot placement section 4 by the lot transfer section 5 .
  • the substrate holder cleaning processing apparatus 80 supplies cleaning processing liquid to the substrate holder 53 of the lot transport mechanism 50 and further supplies dry gas to perform cleaning processing of the substrate holder 53 .
  • the control unit 7 controls the operation of each unit of the substrate processing apparatus 1 (carrier loading/unloading unit 2, lot forming unit 3, lot placement unit 4, lot transport unit 5, lot processing unit 6, etc.).
  • the control section 7 controls the operation of each section of the substrate processing apparatus 1 based on signals from switches, various sensors, and the like.
  • the control unit 7 includes a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), input/output ports, and various circuits, and programs stored in a storage unit (not shown). is read and executed to control the operation of the substrate processing apparatus 1 .
  • the control unit 7 has a computer-readable storage medium 8 .
  • the storage medium 8 stores the above programs for controlling various processes executed in the substrate processing apparatus 1 .
  • the program may have been stored in the computer-readable storage medium 8 and installed in the storage medium 8 of the control unit 7 from another storage medium.
  • Examples of computer-readable storage media 8 include hard disks (HD), flexible disks (FD), compact disks (CD), magnet optical disks (MO), memory cards, and the like.
  • FIG. 11 is a diagram showing the configuration of the processing tank 61 according to the embodiment.
  • the processing tank 61 performs an etching process for etching the silicon oxide film 11 formed on the wafers W by immersing the wafers W for one lot in an etchant.
  • the processing bath 61 includes an inner bath 100 and an outer bath 110 .
  • the processing tank 61 also includes a circulation section 120 and an etchant supply section 130 .
  • the inner tank 100 is open at the top and stores an etchant inside. A lot (a plurality of wafers W) is immersed in such an inner bath 100 .
  • the outer tub 110 is open at the top and is arranged around the top of the inner tub 100 .
  • the etchant overflowing from the inner bath 100 flows into the outer bath 110 .
  • the circulation unit 120 circulates the etchant between the inner bath 100 and the outer bath 110 .
  • the circulation section 120 includes a circulation path 121 , a nozzle 122 , a pump 123 , a filter 124 and a temperature adjustment section 125 .
  • the circulation path 121 connects the outer tank 110 and the inner tank 100 .
  • One end of the circulation path 121 is connected to the outer bath 110 and the other end of the circulation path 121 is connected to a nozzle 122 arranged inside the inner bath 100 .
  • the pump 123 , the filter 124 and the temperature adjustment section 125 are provided in the circulation path 121 .
  • a pump 123 sends out the etchant in the outer bath 110 to the circulation path 121 .
  • Filter 124 removes impurities from the etchant flowing through circulation path 121 .
  • the temperature adjustment unit 125 is, for example, a heater, and adjusts the temperature of the etchant flowing through the circulation path 121 to a temperature suitable for the etching process. Pump 123 and temperature adjuster 125 are controlled by controller 7 .
  • the circulation unit 120 sends the etchant from the outer tank 110 to the inner tank 100 via the circulation path 121 .
  • the etchant sent into the inner bath 100 overflows the inner bath 100 and flows out to the outer bath 110 again.
  • the etchant circulates between the inner bath 100 and the outer bath 110 .
  • the etchant supply unit 130 supplies the etchant to the processing bath 61 .
  • the etchant supply unit 130 includes an etchant supply source 131 , a supply path 132 , a valve 133 and a switching unit 134 .
  • the etchant supply source 131 supplies an etchant to which at least one of hydrochloric acid, metal salt, and surfactant has been added in advance.
  • the supply path 132 is connected to the etchant supply source 131 and supplies the etchant supplied from the etchant supply source 131 to the inner bath 100 or the outer bath 110 .
  • the valve 133 is provided in the supply path 132 and opens and closes the supply path 132 .
  • the switching unit 134 is provided in the supply path 132 and switches the outflow destination of the etchant flowing through the supply path 132 between the inner tank 100 and the outer tank 110 .
  • the valve 133 and the switching section 134 are electrically connected to the control section 7 and controlled by the control section 7 .
  • the control unit 7 controls the valve 133 and the switching unit 134 to supply a new etchant from the etchant supply source 131 to the inner bath 100. supply.
  • the control section 7 controls the valve 133 and the switching section 134 to supply new etching liquid from the etching liquid supply source 131 to the outer tank 110. supply.
  • FIG. 12 is a flow chart showing the procedure of processing executed by the substrate processing apparatus 1 according to the embodiment.
  • the processing procedure shown in FIG. 12 is executed under the control of the control unit 7 .
  • the substrate processing apparatus 1 first performs a preparation process (step S101).
  • a preparation process as shown in FIG. 1, a plurality of wafers W each having a laminated film including a plurality of silicon oxide films 11 with different film thicknesses are prepared.
  • an etching process using an etchant is performed on a plurality of wafers W forming a lot (step S102).
  • the plurality of wafers W are lowered using the substrate lifting mechanism 63 to immerse the plurality of wafers W in the etchant stored in the inner bath 100 of the processing bath 61 .
  • This etching process is performed until the laminated film formed on the wafer W changes from the initial state shown in FIG. 1 to the laminated surface exposed state shown in FIG. That is, the etching process exposes the lamination surfaces (upper and lower surfaces) of the polysilicon film 12 by etching the silicon oxide film 11 in contact with the polysilicon film 12 .
  • the inventors of the present application have found that the etching solution to which at least one of hydrochloric acid, a metal salt, and a surfactant are added is more effective than an etching solution to which hydrochloric acid, a metal salt, and a surfactant are not added. It has been confirmed experimentally that the variation in etching rate between each step is reduced. Therefore, in the substrate processing apparatus 1, an etching process is performed using an etchant to which at least one of hydrochloric acid, a metal salt, and a surfactant is added. Thereby, variations in the etching rate for each silicon oxide film 11 can be reduced.
  • a rinse process is performed in the substrate processing apparatus 1 (step S103).
  • a plurality of wafers W that have undergone the etching process are transported to the processing tank 62 for the rinsing process and immersed in a rinse liquid (deionized water or the like) stored in the processing tank 62 .
  • a rinse liquid deionized water or the like
  • a drying process is performed in the substrate processing apparatus 1 (step S104).
  • a plurality of wafers W that have finished the rinsing process are transferred to the processing tank 91 for the drying process, and the rinsing liquid adhering to the surfaces of the plurality of wafers W is removed by the processing gas. Thereby, the plurality of wafers W are dried.
  • the plurality of wafers W that have undergone the drying process are housed in the carrier 9 placed on the carrier stage 20 .
  • substrate processing for one lot is completed.
  • FIG. 13 is a diagram illustrating a configuration example of a processing unit according to a modification
  • the processing unit 200 includes a chamber 220, a substrate holding mechanism 230, a nozzle 240, and a recovery cup 250.
  • the chamber 220 accommodates the substrate holding mechanism 230 , the nozzle 240 and the collection cup 250 .
  • An FFU (Fan Filter Unit) 221 is provided on the ceiling of the chamber 220 . FFU 221 creates a downflow within chamber 220 .
  • the substrate holding mechanism 230 includes a holding portion 231 , a support portion 232 and a driving portion 233 .
  • the holding part 231 holds the wafer W horizontally.
  • the column portion 232 is a member extending in the vertical direction, the base end portion of which is rotatably supported by the drive portion 233, and the tip portion of which supports the holding portion 231 horizontally.
  • the drive section 233 rotates the support section 232 around the vertical axis.
  • the substrate holding mechanism 230 rotates the supporting part 231 supported by the supporting part 232 by rotating the supporting part 232 using the driving part 233, thereby rotating the wafer W held by the supporting part 231. .
  • the nozzle 240 is arranged above the wafer W held by the holding part 231 and supplies various processing liquids to the wafer W.
  • the collection cup 250 is arranged to surround the holding portion 231 and collects the processing liquid scattered from the wafer W due to the rotation of the holding portion 231 .
  • a drain port 251 is formed at the bottom of the recovery cup 250 , and the processing liquid collected by the recovery cup 250 is discharged to the outside of the processing unit 200 through the drain port 251 .
  • An exhaust port 252 is formed at the bottom of the collection cup 250 to discharge the gas supplied from the FFU 221 to the outside of the processing unit 200 .
  • the processing unit 200 further includes an etchant supply section 260 and a rinse liquid supply section 270 .
  • the etchant supply unit 260 includes an etchant supply source 261 and a valve 262 and supplies the etchant supplied from the etchant supply source 261 to the nozzle 240 .
  • the rinse liquid supply unit 270 includes a rinse liquid supply source 271 and a valve 272 and supplies the rinse liquid (deionized water or the like) supplied from the rinse liquid supply source 271 to the nozzle 240 .
  • etching processing is first performed.
  • the valve 262 is opened for a predetermined time to supply the etchant to the wafer W held and rotated by the substrate holding mechanism 230 .
  • the processing unit 200 performs a rinse process.
  • the valve 272 is opened for a predetermined time to supply the rinsing liquid to the wafer W held and rotated by the substrate holding mechanism 230 .
  • a drying process is performed.
  • the wafer W is dried by increasing the rotation speed of the wafer W to shake off the rinse liquid from the wafer W.
  • FIG. When the drying process is completed, the substrate processing for one wafer W is completed.
  • the substrate processing according to the embodiment can also be applied to a single-wafer processing unit that processes wafers W one by one.
  • the polysilicon film 12 and each of the plurality of silicon oxide films 11 are formed adjacent to each other in the vertical direction. structure is not limited to this.
  • each of the plurality of silicon oxide films 11 and another film formed adjacent to each of the plurality of silicon oxide films 11 may be formed adjacent to each other in the horizontal direction.
  • the surface of the wafer W is coated with SC2 (mixed solution of hydrochloric acid and hydrogen peroxide).
  • a removal treatment may be performed to remove residual metal salts.
  • other films formed adjacent to each of the plurality of silicon oxide films 11 are preferably not metal-containing films.
  • the substrate processing method includes a step of preparing a substrate (for example, wafer W) and a step of etching the substrate.
  • the step of preparing a substrate prepares a substrate having a laminated film including a plurality of silicon oxide films (for example, silicon oxide film 11) with different film thicknesses.
  • the substrate is etched with an etchant to which at least one of hydrochloric acid, a metal salt and a surfactant is added. Therefore, according to the substrate processing method according to the embodiment, it is possible to reduce variations in the etching rate for each silicon oxide film in the technique of etching a laminated film including a plurality of silicon oxide films having different film thicknesses.
  • the concentration of each of hydrochloric acid and metal salt in the etching solution may be 0.5 wt% or more and 5 wt% or less. This makes it possible to reduce variations in etching rate for each silicon oxide film regardless of the type of metal salt. Further, by setting the concentration of the metal salt in the etching liquid to 5 wt % or less, contamination of the substrate with metal can be suppressed.
  • the concentration of the surfactant in the etchant may be 0.5 wt% or more and 5 wt% or less. This makes it possible to reduce variations in etching rate for each silicon oxide film regardless of the type of surfactant. Further, by setting the concentration of the surfactant in the etching liquid to 5 wt % or less, it is possible to suppress the organic matter (dirt) removed by the surfactant from remaining on the surface of the substrate.
  • the substrate processing method according to the embodiment may further include a step of removing metal salts remaining on the surface of the substrate in SC2 after the step of etching the substrate. As a result, contamination of the substrate with metal can be suppressed.
  • (Appendix 1) Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses; and etching the substrate with an etchant to which hydrochloric acid is added.
  • (Appendix 2) Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses; and a step of etching the substrate with an etchant to which a metal salt is added.
  • (Appendix 3) Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses; and a step of etching the substrate with an etchant to which a surfactant is added.
  • the laminated film is a laminated film further comprising another film formed adjacent to each of the plurality of silicon oxide films, 4.
  • Appendix 5 The substrate processing method according to appendix 4, wherein in the laminated film, the other film and each of the plurality of silicon oxide films are formed adjacent to each other in a vertical direction or a horizontal direction. (Appendix 6) 6.
  • Appendix 7 The substrate processing method according to any one of appendices 1 to 6, wherein the etchant contains hydrofluoric acid.
  • Appendix 8) 8. The substrate processing method according to appendix 7, wherein the concentration of the hydrofluoric acid in the etching liquid is 0.1 wt % or more and 50 wt % or less.
  • Appendix 9) The substrate processing method according to appendix 1, wherein the concentration of the hydrochloric acid before being added to the etching solution is 35 wt % or more and 37 wt % or less.
  • (Appendix 10) The substrate processing method according to appendix 2, wherein the metal salt is an alkali metal halide or an alkaline earth metal halide.
  • the alkali metal halide comprises at least one of Li, Na, K, Rb and Cs; 11.
  • Appendix 12 The substrate processing method according to appendix 1, wherein the concentration of each of the hydrochloric acid and the metal salt in the etching solution is 0.5 wt % or more and 5 wt % or less.
  • Appendix 16 The substrate processing method according to appendix 2, further comprising a step of removing the metal salt remaining on the surface of the substrate in SC2 after the step of etching the substrate.
  • Appendix 17 a processing tank for storing an etchant to which hydrochloric acid has been added; and a control unit that controls each part, The control unit A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
  • (Appendix 18) a processing tank for storing an etchant to which a metal salt has been added; and a control unit that controls each part,
  • the control unit A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
  • (Appendix 19) a processing tank for storing an etchant to which a surfactant is added; and a control unit that controls each part,
  • the control unit A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
  • control unit 10 silicon substrate 11 silicon oxide film 12 polysilicon film 15 groove 16p water cluster 16s spherical structure 60 etching processing unit 61 processing tank 100 inner tank 110 outer tank 120 circulation unit 130 etching liquid supply unit W wafer

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Abstract

A substrate processing method according to the present invention comprises a step for preparing a substrate and a step for etching the substrate. In the step for preparing a substrate, a substrate which has a multilayer film that comprises a plurality of silicon oxide films having different film thicknesses is prepared. In the step for etching the substrate, the substrate is etched with an etching liquid to which hydrochloric acid is added.

Description

基板処理方法および基板処理装置Substrate processing method and substrate processing apparatus
 本開示は、基板処理方法および基板処理装置に関する。 The present disclosure relates to a substrate processing method and a substrate processing apparatus.
 従来、半導体ウエハなどの基板に形成されたシリコン酸化膜を例えばフッ酸を含むエッチング液でエッチングする技術が知られている(特許文献1参照)。 Conventionally, there is known a technique of etching a silicon oxide film formed on a substrate such as a semiconductor wafer with an etchant containing, for example, hydrofluoric acid (see Patent Document 1).
特開平8-31794号公報JP-A-8-31794
 本開示は、膜厚が異なる複数のシリコン酸化膜を含む積層膜をエッチングする技術において、シリコン酸化膜ごとのエッチングレートのばらつきを低減することができる技術を提供する。 The present disclosure provides a technique for etching a laminated film including a plurality of silicon oxide films with different film thicknesses, which can reduce variations in etching rate for each silicon oxide film.
 本開示の一態様による基板処理方法は、基板を準備する工程と、基板のエッチング処理を行う工程とを含む。基板を準備する工程は、膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する。基板のエッチング処理を行う工程は、塩酸が添加されたエッチング液で基板のエッチング処理を行う。 A substrate processing method according to one aspect of the present disclosure includes a step of preparing a substrate and a step of etching the substrate. The step of preparing a substrate prepares a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses. In the step of etching the substrate, the substrate is etched with an etchant to which hydrochloric acid is added.
 本開示によれば、膜厚が異なる複数のシリコン酸化膜を含む積層膜をエッチングする技術において、シリコン酸化膜ごとのエッチングレートのばらつきを低減することができる。 According to the present disclosure, in a technique for etching a laminated film including a plurality of silicon oxide films with different film thicknesses, it is possible to reduce variations in etching rate for each silicon oxide film.
図1は、実施形態に係る基板処理の説明図である。FIG. 1 is an explanatory diagram of substrate processing according to the embodiment. 図2は、実施形態に係る基板処理の説明図である。FIG. 2 is an explanatory diagram of substrate processing according to the embodiment. 図3は、塩酸および金属塩が添加されたエッチング液を用いた場合における、シリコン酸化膜ごとのエッチングレートのばらつきの変化を示すグラフである。FIG. 3 is a graph showing variations in etching rate for each silicon oxide film when using an etchant to which hydrochloric acid and a metal salt are added. 図4は、塩酸および金属塩が添加されたエッチング液を用いた場合における、シリコン酸化膜ごとのエッチングレートのばらつきの変化を示すグラフである。FIG. 4 is a graph showing variations in etching rate for each silicon oxide film when using an etchant to which hydrochloric acid and a metal salt are added. 図5は、水クラスターの形成を説明するための図である。FIG. 5 is a diagram for explaining the formation of water clusters. 図6は、球状構造体の形成を説明するための図である。FIG. 6 is a diagram for explaining the formation of spherical structures. 図7は、ポリシリコン膜の一部の表面電位がマイナスからプラス側にシフトする様子を説明するための図である。FIG. 7 is a diagram for explaining how the surface potential of a portion of the polysilicon film shifts from negative to positive. 図8は、界面活性剤が添加されたエッチング液を用いた場合における、シリコン酸化膜ごとのエッチングレートのばらつきの変化を示すグラフである。FIG. 8 is a graph showing variations in etching rate for each silicon oxide film when using an etchant containing a surfactant. 図9は、界面活性剤が添加されたエッチング液を用いた場合における、シリコン酸化膜ごとのエッチングレートのばらつきの変化を示すグラフである。FIG. 9 is a graph showing variations in etching rate for each silicon oxide film when using an etchant containing a surfactant. 図10は、実施形態に係る基板処理装置の構成を示す図である。FIG. 10 is a diagram showing the configuration of the substrate processing apparatus according to the embodiment. 図11は、実施形態に係る処理槽の構成を示す図である。FIG. 11 is a diagram showing the configuration of a processing bath according to the embodiment. 図12は、実施形態に係る基板処理装置が実行する処理の手順を示すフローチャートである。FIG. 12 is a flow chart showing the procedure of processing executed by the substrate processing apparatus according to the embodiment. 図13は、変形例に係る処理ユニットの構成例を示す図である。FIG. 13 is a diagram illustrating a configuration example of a processing unit according to a modification;
 以下に、本開示によるノズル、基板処理方法および基板処理装置を実施するための形態(以下、「実施形態」と記載する)について図面を参照しつつ詳細に説明する。なお、この実施形態により本開示が限定されるものではない。また、各実施形態は、処理内容を矛盾させない範囲で適宜組み合わせることが可能である。また、以下の各実施形態において同一の部位には同一の符号を付し、重複する説明は省略される。 Hereinafter, embodiments for implementing the nozzle, substrate processing method, and substrate processing apparatus according to the present disclosure (hereinafter referred to as "embodiments") will be described in detail with reference to the drawings. Note that the present disclosure is not limited by this embodiment. Further, each embodiment can be appropriately combined within a range that does not contradict the processing contents. Also, in each of the following embodiments, the same parts are denoted by the same reference numerals, and overlapping descriptions are omitted.
 また、以下に示す実施形態では、「一定」、「直交」、「垂直」あるいは「平行」といった表現が用いられる場合があるが、これらの表現は、厳密に「一定」、「直交」、「垂直」あるいは「平行」であることを要しない。すなわち、上記した各表現は、例えば製造精度、設置精度などのずれを許容するものとする。 Further, in the embodiments described below, expressions such as "constant", "perpendicular", "perpendicular" or "parallel" may be used, but these expressions are strictly "constant", "perpendicular", " It does not have to be "perpendicular" or "parallel". That is, each of the expressions described above allows deviations in, for example, manufacturing accuracy and installation accuracy.
 また、以下参照する各図面では、説明を分かりやすくするために、互いに直交するX軸方向、Y軸方向およびZ軸方向を規定し、Z軸正方向を鉛直上向き方向とする直交座標系を示す場合がある。また、鉛直軸を回転中心とする回転方向をθ方向と呼ぶ場合がある。 In addition, in each drawing referred to below, in order to make the explanation easier to understand, an orthogonal coordinate system is shown in which the X-axis direction, the Y-axis direction and the Z-axis direction that are orthogonal to each other are defined, and the Z-axis positive direction is the vertically upward direction. Sometimes. Also, the direction of rotation about the vertical axis is sometimes called the θ direction.
<基板処理について>
 まず、実施形態に係る基板処理の内容について図1および図2を参照して説明する。図1および図2は、実施形態に係る基板処理の説明図である。
<About substrate processing>
First, details of substrate processing according to the embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 and 2 are explanatory diagrams of substrate processing according to the embodiment.
 実施形態に係る基板処理では、まず、図1に示す構造を有する半導体ウエハ(以下、ウエハWと記載する)が準備される。ウエハWは、シリコン基板10上に、複数のシリコン酸化膜11および複数のポリシリコン膜12が形成されて構成される。 In the substrate processing according to the embodiment, first, a semiconductor wafer (hereinafter referred to as wafer W) having the structure shown in FIG. 1 is prepared. The wafer W is constructed by forming a plurality of silicon oxide films 11 and a plurality of polysilicon films 12 on a silicon substrate 10 .
 複数のシリコン酸化膜11は、シリコン基板10上に鉛直方向に互いに間隔を空けて形成される。複数のシリコン酸化膜11は、互いに膜厚が異なる。複数のシリコン酸化膜11の膜厚は、例えば、1nm以上30nm以下である。 A plurality of silicon oxide films 11 are formed on the silicon substrate 10 at intervals in the vertical direction. The plurality of silicon oxide films 11 have different film thicknesses. The film thickness of the plurality of silicon oxide films 11 is, for example, 1 nm or more and 30 nm or less.
 ポリシリコン膜12は、これら複数のシリコン酸化膜11の各々と鉛直方向に隣接して形成される。複数のシリコン酸化膜11の膜厚が異なるため、複数のシリコン酸化膜11の各々と接するポリシリコン膜12同士は、互いに異なる間隔を空けて形成される。 The polysilicon film 12 is formed adjacent to each of the plurality of silicon oxide films 11 in the vertical direction. Since the plurality of silicon oxide films 11 have different film thicknesses, the polysilicon films 12 in contact with each of the plurality of silicon oxide films 11 are formed with different intervals therebetween.
 このように、基板処理の対象となるウエハWは、シリコン酸化膜11とポリシリコン膜12とが交互に積層された積層膜を有している。なお、ウエハWは、膜厚が異なる複数のシリコン酸化膜11を少なくとも含む積層膜であればよく、積層膜の構成は図1に示す例に特に限定されない。例えば、複数のシリコン酸化膜11の各々と隣接して形成される他の膜としては、上述したポリシリコン膜12の他、シリコン膜、シリコン窒化膜、金属含有膜等を用いることができる。すなわち、他の膜は、シリコン膜、ポリシリコン膜、シリコン窒化膜および金属含有膜の少なくとも1つから選択され得る。 Thus, the wafer W to be subjected to substrate processing has a laminated film in which the silicon oxide film 11 and the polysilicon film 12 are alternately laminated. Note that the wafer W may be a laminated film including at least a plurality of silicon oxide films 11 having different film thicknesses, and the structure of the laminated film is not particularly limited to the example shown in FIG. For example, as other films formed adjacent to each of the plurality of silicon oxide films 11, in addition to the polysilicon film 12 described above, a silicon film, a silicon nitride film, a metal-containing film, or the like can be used. That is, the other film can be selected from at least one of a silicon film, a polysilicon film, a silicon nitride film and a metal-containing film.
 また、ウエハWには、エッチング液が侵入し、積層されたシリコン酸化膜11をエッチングするための溝15が形成されている。 In addition, the wafer W is formed with grooves 15 through which the etchant penetrates to etch the laminated silicon oxide film 11 .
 実施形態に係る基板処理は、エッチング液を用いたエッチング処理によって、シリコン酸化膜11を選択的にエッチングする。これにより、図2に示すように、溝15に面するシリコン酸化膜11の端面が溝15に面するポリシリコン膜12の端面よりも溝15の幅方向に後退するとともに、ポリシリコン膜12の端部の上下面が露出する。 The substrate processing according to the embodiment selectively etches the silicon oxide film 11 by an etching process using an etchant. As a result, as shown in FIG. 2, the end face of the silicon oxide film 11 facing the trench 15 recedes from the end face of the polysilicon film 12 facing the trench 15 in the width direction of the trench 15 , and the polysilicon film 12 is flattened. The upper and lower surfaces of the ends are exposed.
 ここで、積層膜におけるシリコン酸化膜11の膜厚の差が大きくなるほど、シリコン酸化膜11ごとのエッチングレートのばらつきは大きくなる。具体的には、膜厚が大きいシリコン酸化膜11と比べて膜厚が小さいシリコン酸化膜11の方がエッチングされ難くなる。 Here, as the difference in film thickness of the silicon oxide films 11 in the laminated film increases, the variation in etching rate for each silicon oxide film 11 increases. Specifically, the silicon oxide film 11 having a smaller thickness is less likely to be etched than the silicon oxide film 11 having a larger thickness.
 これに対し、本願発明者は、塩酸、金属塩および界面活性剤の少なくともいずれか一つが添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることを見出した。図3および図4は、塩酸(HCl)および金属塩(NaClまたはCaCl)が添加されたエッチング液を用いた場合における、シリコン酸化膜11ごとのエッチングレートのばらつきの変化を示すグラフである。 On the other hand, the inventors of the present application have found that the etching rate of each silicon oxide film 11 is reduced by etching the wafer W using an etching solution to which at least one of hydrochloric acid, a metal salt, and a surfactant is added. It was found that variation can be suppressed. 3 and 4 are graphs showing variations in etching rate for each silicon oxide film 11 when using an etchant containing hydrochloric acid (HCl) and metal salt (NaCl or CaCl 2 ).
 図3および図4に示した実験結果の処理条件は、以下の通りである。
 積層膜中のシリコン酸化膜の積層数:3
 シリコン酸化膜の膜厚:最下層から順に、15nm、30nm、7.5nm
 処理工程:エッチング液への浸漬(エッチング処理)、その後、DIW(脱イオン水)への浸漬(リンス処理)、その後、乾燥気体を用いた乾燥処理
 エッチング液:フッ酸(HF)水溶液
 エッチング液に添加された添加物:塩酸(HCl)および金属塩(NaClまたはCaCl
The processing conditions for the experimental results shown in FIGS. 3 and 4 are as follows.
Lamination number of silicon oxide films in laminated film: 3
Thickness of silicon oxide film: 15 nm, 30 nm, 7.5 nm from the bottom layer
Treatment process: immersion in etching solution (etching treatment), then immersion in DIW (deionized water) (rinsing treatment), then drying treatment using dry gas Etching solution: hydrofluoric acid (HF) aqueous solution To etching solution Additives added: Hydrochloric acid (HCl) and metal salts (NaCl or CaCl 2 )
 図3および図4において、縦軸は、シリコン酸化膜11ごとのエッチングレートのばらつきの変化を判定するための指標値であるエッチングレート比(ER ratio)を示す。エッチングレート比は、積層された複数のシリコン酸化膜のうち膜厚が最も大きいシリコン酸化膜11のエッチングレートに対する膜厚が最も小さいシリコン酸化膜11のエッチングレートの比である。エッチングレート比は、その値が1に近づくほどシリコン酸化膜11ごとのエッチングレートのばらつきが小さくなることを示している。 In FIGS. 3 and 4, the vertical axis represents an etching rate ratio (ER ratio), which is an index value for determining variations in etching rate for each silicon oxide film 11 . The etching rate ratio is the ratio of the etching rate of the silicon oxide film 11 having the smallest thickness to the etching rate of the silicon oxide film 11 having the largest thickness among the plurality of laminated silicon oxide films. The etching rate ratio indicates that the closer the value is to 1, the smaller the variation in the etching rate for each silicon oxide film 11 is.
 また、図3および図4に示すグラフにおいて、「w/o Additives」は、塩酸および金属塩が添加されてないエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「HCl」は、塩酸(HCl)が添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「NaCl」は、金属塩としてNaClが添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「CaCl」は、金属塩としてCaClが添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。なお、図3は、エッチング液における塩酸および金属塩の各々の濃度が0.05wt%である場合の実験結果であり、図4は、エッチング液における塩酸および金属塩の各々の濃度が0.5wt%である場合の実験結果である。 Also, in the graphs shown in FIGS. 3 and 4, "w/o Additives" indicates the etching rate ratio in the laminated film when using an etching solution to which hydrochloric acid and metal salt are not added. "HCl" indicates the etching rate ratio in the laminated film when using an etching solution to which hydrochloric acid (HCl) is added. "NaCl" indicates the etching rate ratio in the laminated film when using an etchant to which NaCl is added as a metal salt. “CaCl 2 ” indicates the etching rate ratio in the laminated film when using an etchant to which CaCl 2 is added as a metal salt. FIG. 3 shows experimental results when the concentration of hydrochloric acid and metal salt in the etching solution is 0.05 wt %, and FIG. %.
 図3および図4に示すように、金属塩としてNaClが添加されたエッチング液を用いた場合のエッチングレート比は、塩酸および金属塩が添加されていないエッチング液を用いた場合のエッチングレート比と比べて大きい。また、図4に示すように、金属塩としてCaClが添加されたエッチング液を用いた場合のエッチングレート比は、塩酸および金属塩が添加されていないエッチング液を用いた場合のエッチングレート比と比べて大きい。また、図4に示すように、塩酸(HCl)が添加されたエッチング液を用いた場合のエッチングレート比は、塩酸および金属塩が添加されていないエッチング液を用いた場合のエッチングレート比と比べて大きい。このように、図3および図4に示す実験結果から、金属塩としてNaClが添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることが分かる。また、図4に示す実験結果から、金属塩としてCaClが添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることが分かる。また、図4に示す実験結果から、塩酸(HCl)が添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることが分かる。 As shown in FIGS. 3 and 4, the etching rate ratio when using the etching solution to which NaCl is added as a metal salt is higher than the etching rate ratio when using the etching solution to which neither hydrochloric acid nor metal salt is added. big in comparison. Also, as shown in FIG. 4, the etching rate ratio when using an etching solution to which CaCl 2 is added as a metal salt is higher than the etching rate ratio when using an etching solution to which neither hydrochloric acid nor a metal salt is added. big in comparison. Further, as shown in FIG. 4, the etching rate ratio in the case of using the etching solution to which hydrochloric acid (HCl) is added is compared to the etching rate ratio in the case of using the etching solution to which neither hydrochloric acid nor metal salt is added. big. As described above, from the experimental results shown in FIGS. 3 and 4, by etching the wafer W using the etchant to which NaCl is added as a metal salt, variations in the etching rate for each silicon oxide film 11 can be suppressed. It is understood that Further, from the experimental results shown in FIG. 4, it can be seen that the variation in the etching rate for each silicon oxide film 11 can be suppressed by etching the wafer W using the etchant to which CaCl 2 is added as a metal salt. . Further, from the experimental results shown in FIG. 4, it can be seen that the variation in the etching rate for each silicon oxide film 11 can be suppressed by etching the wafer W using an etchant to which hydrochloric acid (HCl) is added.
 この実験結果は、例えば以下のように考察される。すなわち、シリコン酸化膜11のエッチングのメカニズムは、次のように進行する。まず、化学反応式(1)に示すように、酸化シリコン(SiO)は、エッチング液に含まれるフッ酸(HF)と反応してエッチング液に溶解する。言い換えれば、シリコン酸化膜11がエッチングされる。 This experimental result is considered, for example, as follows. That is, the etching mechanism of the silicon oxide film 11 proceeds as follows. First, as shown in chemical reaction formula (1), silicon oxide (SiO 2 ) reacts with hydrofluoric acid (HF) contained in the etchant and dissolves in the etchant. In other words, silicon oxide film 11 is etched.
 SiO+6HF→HSiF+2HO ・・・ (1) SiO2 +6HF-> H2SiF6 + 2H2O (1 )
 また、エッチング液中においては、化学反応式(2)、(3)で示す反応が起こることによって、二フッ化水素イオン(HF )が生じる。 Further, in the etchant, hydrogen difluoride ions (HF 2 ) are generated by the reactions represented by the chemical reaction formulas (2) and (3).
 HF⇔H+F ・・・ (2)
 HF+F⇔HF  ・・・ (3)
HF⇔H + +F - (2)
HF+F - ⇔ HF 2 - (3)
 そして、化学反応式(2)、(3)で示す反応で生じる二フッ化水素イオン(HF )は、酸化シリコン(SiO)に対するエッチャントとして機能し、上記の化学反応式(1)で示した反応をさらに促進させる。 Hydrogen difluoride ions (HF 2 ) generated by the reactions represented by the chemical reaction formulas (2) and (3) function as an etchant for silicon oxide (SiO 2 ), and the above chemical reaction formula (1) It further accelerates the indicated reaction.
 このように、シリコン酸化膜11のエッチングは、酸化シリコン(SiO)とフッ酸(HF)との反応がエッチャントである二フッ化水素イオン(HF )によって促進されることによって、進行する。したがって、シリコン酸化膜11のエッチングが進行するためには、二フッ化水素イオン(HF )がシリコン酸化膜11まで到達することが重要となる。 In this manner, the etching of the silicon oxide film 11 proceeds by promoting the reaction between silicon oxide (SiO 2 ) and hydrofluoric acid (HF) by the etchant hydrogen difluoride ions (HF 2 ). . Therefore, in order for the etching of the silicon oxide film 11 to progress, it is important that the hydrogen difluoride ions (HF 2 ) reach the silicon oxide film 11 .
 シリコン酸化膜11のエッチングが進行すると、エッチング液中において、化学反応式(2)、(3)で示す反応が進行することによって、水素イオン(H)が増加する。水素イオン(H)は、エッチング液中において安定に存在することができず、水分子と結合して(つまり、水和して)オキソニウムイオン(H)となる。オキソニウムイオン(H)は、シリコン酸化膜11に接するポリシリコン膜12が負に帯電しているため、ポリシリコン膜12の表面に引き寄せられる。そして、オキソニウムイオン(H)は、図5に示すように、ポリシリコン膜12の表面において、水分子と結合して(つまり、水和して)、複数の水分子を平面状に配列した水クラスター16pを形成する。図5は、水クラスターの形成を説明するための図である。水クラスター16pは、シリコン酸化膜11に接するポリシリコン膜12同士の間隔が狭いほど、言い換えると、シリコン酸化膜11の膜厚が小さいほど、密に形成される。 As the etching of the silicon oxide film 11 progresses, hydrogen ions (H + ) increase in the etchant due to the progress of reactions represented by chemical reaction formulas (2) and (3). Hydrogen ions (H + ) cannot exist stably in the etchant, and combine with water molecules (that is, hydrate) to form oxonium ions (H 3 O + ). Oxonium ions (H 3 O + ) are attracted to the surface of polysilicon film 12 because polysilicon film 12 in contact with silicon oxide film 11 is negatively charged. Then, as shown in FIG. 5, the oxonium ions (H 3 O + ) combine with water molecules (that is, hydrate) on the surface of the polysilicon film 12 to form a plurality of water molecules into a planar shape. to form water clusters 16p arranged in a row. FIG. 5 is a diagram for explaining the formation of water clusters. Water clusters 16p are formed more densely as the distance between polysilicon films 12 in contact with silicon oxide film 11 is narrower, in other words, as the film thickness of silicon oxide film 11 is smaller.
 したがって、シリコン酸化膜11の膜厚が小さい場合、水クラスター16pによって二フッ化水素イオン(HF )のシリコン酸化膜11への到達が阻害されるおそれがある。これにより、膜厚が小さいシリコン酸化膜11のエッチングレートが、膜厚が大きいシリコン酸化膜11のエッチングレートと比べて小さくなる。この結果、シリコン酸化膜11ごとのエッチングレートのばらつきが生じることとなる。 Therefore, if the thickness of the silicon oxide film 11 is small, the water clusters 16p may prevent the hydrogen difluoride ions (HF 2 ) from reaching the silicon oxide film 11 . As a result, the etching rate of the silicon oxide film 11 with a smaller thickness is lower than the etching rate of the silicon oxide film 11 with a larger thickness. As a result, the etching rate of each silicon oxide film 11 varies.
 これに対し、金属塩(例えば、NaCl)が添加されたエッチング液を用いると、エッチング液中の金属塩が電離することによって金属イオン(例えば、Na)および陰イオン(例えば、Cl)が生じる。エッチング液中の金属塩から生じた陰イオン(例えば、Cl)は、ポリシリコン膜12の表面において、水クラスター16pにおける水和構造(つまり、水分子同士の結合)を破壊する。また、エッチング液中の金属塩から生じた金属イオン(例えば、Na)は、図6に示すように、ポリシリコン膜12の表面において、水分子と結合して(つまり、水和して)、複数の水分子を球状に配列した球状構造体16sを形成する。図6は、球状構造体の形成を説明するための図である。ポリシリコン膜12の表面において球状構造体16sが形成されると、シリコン酸化膜11の膜厚が小さい場合であっても、二フッ化水素イオン(HF )が通過可能な空間が増大し、二フッ化水素イオン(HF )のシリコン酸化膜11への到達が阻害されない。この結果、シリコン酸化膜11ごとのエッチングレートのばらつきは、金属塩が添加されてないエッチング液を用いた場合と比較して少なくなると考えられる。 On the other hand, when an etchant to which a metal salt (eg, NaCl) is added is used, metal ions (eg, Na + ) and anions (eg, Cl ) are generated by ionizing the metal salt in the etchant. occur. Anions (for example, Cl ) generated from the metal salt in the etchant destroy the hydration structure (that is, bonds between water molecules) in the water clusters 16 p on the surface of the polysilicon film 12 . In addition, metal ions (eg, Na + ) generated from the metal salt in the etching solution combine with water molecules (that is, hydrate) on the surface of the polysilicon film 12, as shown in FIG. , to form a spherical structure 16s in which a plurality of water molecules are arranged in a spherical shape. FIG. 6 is a diagram for explaining the formation of spherical structures. When the spherical structures 16s are formed on the surface of the polysilicon film 12, even if the thickness of the silicon oxide film 11 is small, the space through which hydrogen difluoride ions (HF 2 ) can pass increases. , the arrival of hydrogen difluoride ions (HF 2 ) to the silicon oxide film 11 is not hindered. As a result, it is considered that the variation in the etching rate for each silicon oxide film 11 is reduced as compared with the case of using an etchant to which no metal salt is added.
 また、塩酸が添加されたエッチング液を用いると、エッチング液のpHがより酸性側(例えばpHが1未満)になることで、図7に示すように、ポリシリコン膜12の一部の表面電位がマイナスからプラス側にシフトし易くなる。図7は、ポリシリコン膜の一部の表面電位がマイナスからプラス側にシフトする様子を説明するための図である。ポリシリコン膜12の一部の表面電位がマイナスからプラス側にシフトすることにより、ポリシリコン膜12の表面において、オキソニウムイオン(H)が反発して水クラスター16pが形成されにくくなる。そのため、シリコン酸化膜11の膜厚が小さい場合であっても、二フッ化水素イオン(HF )が通過可能な空間が増大し、二フッ化水素イオン(HF )のシリコン酸化膜11への到達が阻害されない。この結果、シリコン酸化膜11ごとのエッチングレートのばらつきは、金属塩が添加されたエッチング液を用いた場合と同様に少なくなると考えられる。 Further, when an etching solution to which hydrochloric acid is added is used, the pH of the etching solution becomes more acidic (for example, the pH is less than 1), and as shown in FIG. becomes easier to shift from negative to positive. FIG. 7 is a diagram for explaining how the surface potential of a portion of the polysilicon film shifts from negative to positive. When the surface potential of a portion of polysilicon film 12 shifts from negative to positive, oxonium ions (H 3 O + ) are repulsed on the surface of polysilicon film 12, making it difficult for water clusters 16p to form. . Therefore, even if the thickness of the silicon oxide film 11 is small, the space through which the hydrogen difluoride ions (HF 2 ) can pass increases, and the hydrogen difluoride ions (HF 2 ) pass through the silicon oxide film. Reaching 11 is not hindered. As a result, it is considered that the variation in the etching rate for each silicon oxide film 11 is reduced as in the case of using an etchant to which a metal salt is added.
 図8および図9は、界面活性剤(OACl、OTMAClまたはSDBS)が添加されたエッチング液を用いた場合における、シリコン酸化膜11ごとのエッチングレートのばらつきの変化を示すグラフである。 FIGS. 8 and 9 are graphs showing variations in etching rate for each silicon oxide film 11 when using an etchant to which a surfactant (OACl, OTMACl or SDBS) is added.
 図8および図9に示した実験結果の処理条件は、以下の点を除き、図3および図4に示した実験結果の処理条件と同様である。
 エッチング液に添加された界面活性剤:n-オクチルアミン塩酸塩(OACl)、n-オクチルトリメチルアンモニウムクロリド(OTMACl)またはドデシルベンゼンスルホン酸ナトリウム(SDBS)
The processing conditions for the experimental results shown in FIGS. 8 and 9 are the same as the processing conditions for the experimental results shown in FIGS. 3 and 4, except for the following points.
Surfactants added to the etchant: n-octylamine hydrochloride (OACl), n-octyltrimethylammonium chloride (OTMACl) or sodium dodecylbenzenesulfonate (SDBS)
 図8および図9において、縦軸は、シリコン酸化膜11ごとのエッチングレートのばらつきの変化を判定するための指標値であるエッチングレート比(ER ratio)を示す。エッチングレート比は、積層された複数のシリコン酸化膜のうち膜厚が最も大きいシリコン酸化膜11のエッチングレートに対する膜厚が最も小さいシリコン酸化膜11のエッチングレートの比である。エッチングレート比は、その値が1に近づくほどシリコン酸化膜11ごとのエッチングレートのばらつきが小さくなることを示している。 In FIGS. 8 and 9, the vertical axis represents an etching rate ratio (ER ratio), which is an index value for determining variations in etching rate for each silicon oxide film 11 . The etching rate ratio is the ratio of the etching rate of the silicon oxide film 11 having the smallest thickness to the etching rate of the silicon oxide film 11 having the largest thickness among the plurality of laminated silicon oxide films. The etching rate ratio indicates that the closer the value is to 1, the smaller the variation in the etching rate for each silicon oxide film 11 is.
 また、図8および図9に示すグラフにおいて、「w/o Additives」は、界面活性剤が添加されてないエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「OACl」は、界面活性剤としてOAClが添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「OTMACl」は、界面活性剤としてOTMAClが添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。また、「SDBS」は、界面活性剤としてSDBSが添加されたエッチング液を用いた場合の積層膜におけるエッチングレート比を示す。なお、図8は、エッチング液における界面活性剤の濃度が0.05wt%である場合の実験結果であり、図9は、エッチング液における界面活性剤の濃度が0.5wt%である場合の実験結果である。 Also, in the graphs shown in FIGS. 8 and 9, "w/o Additives" indicates the etching rate ratio in the laminated film when using an etchant to which no surfactant is added. Further, "OACl" indicates the etching rate ratio in the laminated film when using an etchant to which OACl is added as a surfactant. Also, "OTMACl" indicates the etching rate ratio in the laminated film when using an etchant to which OTMACl is added as a surfactant. "SDBS" indicates the etching rate ratio in the laminated film when using an etchant to which SDBS is added as a surfactant. FIG. 8 shows the experimental results when the surfactant concentration in the etching solution is 0.05 wt %, and FIG. 9 shows the experimental results when the surfactant concentration in the etching solution is 0.5 wt %. This is the result.
 図8および図9に示すように、界面活性剤としてOTMAClが添加されたエッチング液を用いた場合のエッチングレート比は、界面活性剤が添加されていないエッチング液を用いた場合のエッチングレート比と比べて大きい。また、図9に示すように、界面活性剤としてOAClまたはSDBSが添加されたエッチング液を用いた場合のエッチングレート比は、界面活性剤が添加されていないエッチング液を用いた場合のエッチングレート比と比べて大きい。このように、図8および図9に示す実験結果から、界面活性剤としてOTMAClが添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることが分かる。また、図9に示す実験結果から、界面活性剤としてOAClまたはSDBSが添加されたエッチング液を用いてウエハWのエッチング処理を行うことで、シリコン酸化膜11ごとのエッチングレートのばらつきが抑えられることが分かる。 As shown in FIGS. 8 and 9, the etching rate ratio in the case of using the etchant to which OTMACl is added as a surfactant is higher than the etching rate ratio in the case of using the etchant to which no surfactant is added. big in comparison. Further, as shown in FIG. 9, the etching rate ratio when using an etching solution to which OACl or SDBS is added as a surfactant is the etching rate ratio when using an etching solution to which no surfactant is added. large compared to As described above, from the experimental results shown in FIGS. 8 and 9, by performing the etching process of the wafer W using the etchant to which OTMACl is added as a surfactant, the variation in the etching rate for each silicon oxide film 11 can be reduced. I know it can be suppressed. Further, from the experimental results shown in FIG. 9, it is found that etching the wafer W using an etchant to which OACl or SDBS is added as a surfactant suppresses variations in the etching rate for each silicon oxide film 11 . I understand.
 この実験結果は、例えば以下のように考察される。すなわち、界面活性剤が添加されたエッチング液を用いると、エッチング液中の界面活性剤は、ポリシリコン膜12の表面において、水クラスター16p(図5参照)における水和構造(つまり、水分子同士の結合)を破壊する。ポリシリコン膜12の表面において水クラスター16pにおける水和構造が破壊されると、シリコン酸化膜11の膜厚が小さい場合であっても、二フッ化水素イオン(HF )が通過可能な空間が増大し、二フッ化水素イオン(HF )のシリコン酸化膜11への到達が阻害されない。この結果、シリコン酸化膜11ごとのエッチングレートのばらつきは、界面活性剤が添加されてないエッチング液を用いた場合と比較して少なくなると考えられる。 This experimental result is considered, for example, as follows. That is, when an etchant to which a surfactant is added is used, the surfactant in the etchant forms a hydration structure (that is, between water molecules) in the water clusters 16p (see FIG. 5) on the surface of the polysilicon film 12. bond). When the hydration structure in the water clusters 16p on the surface of the polysilicon film 12 is destroyed, even if the thickness of the silicon oxide film 11 is small, a space through which hydrogen difluoride ions (HF 2 ) can pass. increases, and the arrival of hydrogen difluoride ions (HF 2 ) to the silicon oxide film 11 is not hindered. As a result, it is considered that the variation in the etching rate for each silicon oxide film 11 is reduced as compared with the case of using an etchant to which no surfactant is added.
 そこで、図3、図4、図8および図9の結果を踏まえ、実施形態に係る基板処理では、塩酸、金属塩および界面活性剤の少なくともいずれか一つが添加されたエッチング液を用いてシリコン酸化膜11のエッチング処理を行うこととした。 Therefore, based on the results of FIGS. 3, 4, 8, and 9, in the substrate processing according to the embodiment, an etchant to which at least one of hydrochloric acid, a metal salt, and a surfactant is added is used to oxidize silicon. It was decided to perform an etching process for the film 11 .
 実施形態に係るエッチング液は、フッ酸を含む薬液である。エッチング液におけるフッ酸の濃度は、例えば0.1wt%以上50wt%以下である。 The etchant according to the embodiment is a chemical solution containing hydrofluoric acid. The concentration of hydrofluoric acid in the etchant is, for example, 0.1 wt % or more and 50 wt % or less.
 エッチング液に添加される金属塩としては、例えば、ハロゲン化アルカリ金属またはハロゲン化アルカリ土類金属を用いることができる。ハロゲン化アルカリ金属としては、例えば上述したNaClを用いることができる。また、ハロゲン化アルカリ金属は、Li、Na、K、RbおよびCsのうち少なくとも1つを含んでもよい。ハロゲン化アルカリ土類金属としては、例えば上述したCaClを用いることができる。また、ハロゲン化アルカリ土類金属は、Mg、Ca、SrおよびBaのうち少なくとも1つを含んでもよい。 As the metal salt added to the etchant, for example, an alkali metal halide or an alkaline earth metal halide can be used. As the alkali metal halide, for example, NaCl mentioned above can be used. Also, the alkali metal halide may contain at least one of Li, Na, K, Rb and Cs. As the alkaline earth metal halide, for example CaCl 2 as described above can be used. Also, the alkaline earth metal halide may contain at least one of Mg, Ca, Sr and Ba.
 また、エッチング液における塩酸および金属塩の各々の濃度は、0.5wt%以上5wt%以下であることが好ましい。これにより、図3および図4に示す実験結果から明らかなように、金属塩の種類に関わらず、シリコン酸化膜11ごとのエッチングレートのばらつきを低減することができる。また、エッチング液における金属塩の濃度が5wt%以下であることにより、金属によるウエハWの汚染を抑制することができる。 Also, the concentration of each of hydrochloric acid and metal salt in the etching solution is preferably 0.5 wt % or more and 5 wt % or less. As is clear from the experimental results shown in FIGS. 3 and 4, this makes it possible to reduce variations in the etching rate for each silicon oxide film 11 regardless of the type of metal salt. Further, by setting the concentration of the metal salt in the etchant to 5 wt % or less, contamination of the wafer W with metal can be suppressed.
 また、エッチング液に添加される前の塩酸の濃度は、例えば35wt%以上37wt%以下であることが好ましい。 Also, the concentration of hydrochloric acid before being added to the etching solution is preferably 35 wt % or more and 37 wt % or less, for example.
 エッチング液に添加される界面活性剤としては、例えば、陽イオン性界面活性剤または陰イオン性界面活性剤を用いることができる。陽イオン性界面活性剤としては、例えば上述したn-オクチルアミン塩酸塩(OACl)またはn-オクチルトリメチルアンモニウムクロリド(OTMACl)を用いることができる。陰イオン性界面活性剤としては、例えば上述したドデシルベンゼンスルホン酸ナトリウム(SDBS)を用いることができる。 As the surfactant added to the etching solution, for example, a cationic surfactant or an anionic surfactant can be used. As a cationic surfactant, for example, n-octylamine hydrochloride (OACl) or n-octyltrimethylammonium chloride (OTMACl) described above can be used. As an anionic surfactant, for example, sodium dodecylbenzenesulfonate (SDBS) described above can be used.
 また、エッチング液における界面活性剤の濃度は、0.5wt%以上5wt%以下であることが好ましい。これにより、図8および図9に示す実験結果から明らかなように、界面活性剤の種類に関わらず、シリコン酸化膜11ごとのエッチングレートのばらつきを低減することができる。また、エッチング液における界面活性剤の濃度が5wt%以下であることにより、界面活性剤により除去された有機物(汚れ)がウエハWの表面上に残留することを抑制することができる。 Also, the concentration of the surfactant in the etching liquid is preferably 0.5 wt % or more and 5 wt % or less. As is clear from the experimental results shown in FIGS. 8 and 9, this makes it possible to reduce variations in the etching rate for each silicon oxide film 11 regardless of the type of surfactant. Further, by setting the concentration of the surfactant in the etching liquid to 5 wt % or less, it is possible to suppress the organic matter (dirt) removed by the surfactant from remaining on the surface of the wafer W. FIG.
[基板処理装置の構成]
 次に、上述した基板処理を行う基板処理装置の構成について図10を参照して説明する。図10は、実施形態に係る基板処理装置の構成を示す図である。
[Configuration of substrate processing apparatus]
Next, the configuration of the substrate processing apparatus that performs the substrate processing described above will be described with reference to FIG. FIG. 10 is a diagram showing the configuration of the substrate processing apparatus according to the embodiment.
 図10に示すように、実施形態に係る基板処理装置1は、キャリア搬入出部2と、ロット形成部3と、ロット載置部4と、ロット搬送部5と、ロット処理部6と、制御部7とを備える。 As shown in FIG. 10, the substrate processing apparatus 1 according to the embodiment includes a carrier loading/unloading unit 2, a lot forming unit 3, a lot placement unit 4, a lot transport unit 5, a lot processing unit 6, a control a part 7;
 キャリア搬入出部2は、キャリアステージ20と、キャリア搬送機構21と、キャリアストック22、23と、キャリア載置台24とを備える。 The carrier loading/unloading section 2 includes a carrier stage 20 , a carrier transport mechanism 21 , carrier stocks 22 and 23 , and a carrier table 24 .
 キャリアステージ20は、外部から搬送された複数のキャリア9を載置する。キャリア9は、複数(たとえば、25枚)の半導体ウエハ(以下、ウエハWと記載する)を水平姿勢で上下に並べて収容する容器である。キャリア搬送機構21は、キャリアステージ20、キャリアストック22、23およびキャリア載置台24間でキャリア9の搬送を行う。 The carrier stage 20 carries a plurality of carriers 9 transported from the outside. The carrier 9 is a container that accommodates a plurality of (for example, 25) semiconductor wafers (hereinafter referred to as wafers W) arranged vertically in a horizontal posture. The carrier transport mechanism 21 transports the carrier 9 among the carrier stage 20 , carrier stocks 22 and 23 and carrier table 24 .
 キャリア載置台24に載置されたキャリア9からは、処理される前の複数のウエハWが後述する基板搬送機構30によりロット処理部6に搬出される。また、キャリア載置台24に載置されたキャリア9には、処理された複数のウエハWが基板搬送機構30によりロット処理部6から搬入される。 From the carrier 9 mounted on the carrier mounting table 24, a plurality of wafers W to be processed are unloaded to the lot processing section 6 by the substrate transport mechanism 30, which will be described later. A plurality of processed wafers W are carried from the lot processing section 6 to the carrier 9 mounted on the carrier mounting table 24 by the substrate transfer mechanism 30 .
 ロット形成部3は、基板搬送機構30を有し、ロットを形成する。ロットは、1または複数のキャリア9に収容されたウエハWを組合せて同時に処理される複数(たとえば、50枚)のウエハWで構成される。1つのロットを形成する複数のウエハWは、互いの板面を対向させた状態で一定の間隔をあけて配列される。 The lot formation unit 3 has a substrate transport mechanism 30 and forms lots. A lot consists of a plurality of (for example, 50) wafers W that are processed simultaneously by combining wafers W housed in one or more carriers 9 . A plurality of wafers W forming one lot are arranged at regular intervals with their plate surfaces facing each other.
 基板搬送機構30は、キャリア載置台24に載置されたキャリア9とロット載置部4との間で複数のウエハWを搬送する。 The substrate transfer mechanism 30 transfers a plurality of wafers W between the carrier 9 mounted on the carrier mounting table 24 and the lot mounting section 4 .
 ロット載置部4は、ロット搬送台40を有し、ロット搬送部5によってロット形成部3とロット処理部6との間で搬送されるロットを一時的に載置(待機)する。ロット搬送台40は、ロット形成部3で形成された処理される前のロットを載置する搬入側ロット載置台41と、ロット処理部6で処理されたロットを載置する搬出側ロット載置台42とを有する。搬入側ロット載置台41および搬出側ロット載置台42には、1ロット分の複数のウエハWが起立姿勢で前後に並んで載置される。 The lot placing unit 4 has a lot transport table 40 and temporarily places (stands by) the lot transported between the lot forming unit 3 and the lot processing unit 6 by the lot transporting unit 5 . The lot conveyance table 40 includes a loading-side lot mounting table 41 for mounting a lot formed by the lot forming section 3 before being processed, and an unloading-side lot mounting table for mounting a lot processed by the lot processing section 6. 42. A plurality of wafers W for one lot are placed in a standing posture in front and behind on the load-in side lot table 41 and the carry-out side lot table 42 .
 ロット搬送部5は、ロット搬送機構50を有し、ロット載置部4とロット処理部6との間やロット処理部6の内部でロットの搬送を行う。ロット搬送機構50は、レール51と、移動体52と、基板保持体53とを有する。 The lot transport unit 5 has a lot transport mechanism 50 and transports lots between the lot placement unit 4 and the lot processing unit 6 and inside the lot processing unit 6 . The lot transport mechanism 50 has a rail 51 , a moving body 52 and a substrate holder 53 .
 レール51は、ロット載置部4およびロット処理部6に渡って、X軸方向に沿って配置される。移動体52は、複数のウエハWを保持しながらレール51に沿って移動可能に構成される。基板保持体53は、移動体52に設けられ、起立姿勢で前後に並んだ複数のウエハWを保持する。 The rails 51 are arranged along the X-axis direction across the lot placement section 4 and the lot processing section 6 . The moving body 52 is configured to be movable along the rails 51 while holding a plurality of wafers W. As shown in FIG. The substrate holder 53 is provided on the moving body 52 and holds a plurality of wafers W arranged in front and back in an upright posture.
 ロット処理部6は、1ロット分の複数のウエハWに対し、エッチング処理や洗浄処理、乾燥処理などを行う。ロット処理部6には、複数(ここでは、2つ)のエッチング処理装置60と、基板保持体洗浄処理装置80と、乾燥処理装置90とが、レール51に沿って並んで設けられる。 The lot processing unit 6 performs etching processing, cleaning processing, drying processing, etc. on a plurality of wafers W for one lot. In the lot processing section 6 , a plurality (here, two) of etching processing devices 60 , substrate holder cleaning processing devices 80 , and drying processing devices 90 are arranged side by side along rails 51 .
 エッチング処理装置60は、1ロット分の複数のウエハWに対してエッチング処理を一括で行う。基板保持体洗浄処理装置80は、基板保持体53の洗浄処理を行う。乾燥処理装置90は、1ロット分の複数のウエハWに対して乾燥処理を一括で行う。エッチング処理装置60、基板保持体洗浄処理装置80および乾燥処理装置90の台数は、図10の例に限られない。 The etching processing apparatus 60 collectively performs etching processing on a plurality of wafers W for one lot. The substrate holder cleaning apparatus 80 performs cleaning processing of the substrate holder 53 . The drying processing apparatus 90 collectively performs drying processing on a plurality of wafers W for one lot. The number of etching processing devices 60, substrate holder cleaning processing devices 80, and drying processing devices 90 is not limited to the example in FIG.
 エッチング処理装置60は、エッチング処理用の処理槽61と、リンス処理用の処理槽62と、基板昇降機構63,64とを備える。 The etching processing apparatus 60 includes a processing bath 61 for etching processing, a processing bath 62 for rinsing processing, and substrate lifting mechanisms 63 and 64 .
 処理槽61および処理槽62は、1ロット分のウエハWを収容可能であり、エッチング液が貯留される。処理槽61には、エッチング液が貯留される。処理槽61の詳細については後述する。 The processing bath 61 and the processing bath 62 can accommodate one lot of wafers W, and store an etchant. An etchant is stored in the processing bath 61 . Details of the processing tank 61 will be described later.
 処理槽62には、リンス処理用の処理液(脱イオン水等)が貯留される。基板昇降機構63,64は、ロットを形成する複数のウエハWを起立姿勢で前後に並べた状態で保持する。 A processing liquid (deionized water, etc.) for rinsing is stored in the processing tank 62 . The substrate elevating mechanisms 63 and 64 hold a plurality of wafers W forming a lot in a state of being arranged back and forth in an upright posture.
 エッチング処理装置60は、ロット搬送部5で搬送されたロットを基板昇降機構63で保持し、処理槽61のエッチング液に浸漬させてエッチング処理を行う。また、エッチング処理装置60は、ロット搬送部5によって処理槽62に搬送されたロットを基板昇降機構64にて保持し、処理槽62のリンス液に浸漬させることによってリンス処理を行う。 The etching processing apparatus 60 holds the lot conveyed by the lot conveying unit 5 by the substrate lifting mechanism 63, immerses the lot in the etching solution in the processing bath 61, and performs etching processing. The etching apparatus 60 holds the lot transported to the processing bath 62 by the lot transport unit 5 by the substrate lifting mechanism 64 and immerses the lot in the rinsing liquid of the processing bath 62 for rinsing.
 乾燥処理装置90は、処理槽91と、基板昇降機構92とを有する。処理槽91には、乾燥処理用の処理ガスが供給される。基板昇降機構92には、1ロット分の複数のウエハWが起立姿勢で前後に並んで保持される。 The drying processing apparatus 90 has a processing bath 91 and a substrate lifting mechanism 92 . A processing gas for drying is supplied to the processing bath 91 . The substrate lifting mechanism 92 holds a plurality of wafers W for one lot side by side in the front-rear direction in an upright posture.
 乾燥処理装置90は、ロット搬送部5で搬送されたロットを基板昇降機構92で保持し、処理槽91内に供給される乾燥処理用の処理ガスを用いて乾燥処理を行う。処理槽91で乾燥処理されたロットは、ロット搬送部5でロット載置部4に搬送される。 The drying processing device 90 holds the lot transported by the lot transporting unit 5 with the substrate lifting mechanism 92 and performs drying processing using the processing gas for drying processing supplied into the processing bath 91 . The lot that has been dried in the processing tank 91 is transferred to the lot placement section 4 by the lot transfer section 5 .
 基板保持体洗浄処理装置80は、ロット搬送機構50の基板保持体53に洗浄用の処理液を供給し、さらに乾燥ガスを供給することで、基板保持体53の洗浄処理を行う。 The substrate holder cleaning processing apparatus 80 supplies cleaning processing liquid to the substrate holder 53 of the lot transport mechanism 50 and further supplies dry gas to perform cleaning processing of the substrate holder 53 .
 制御部7は、基板処理装置1の各部(キャリア搬入出部2、ロット形成部3、ロット載置部4、ロット搬送部5、ロット処理部6など)の動作を制御する。制御部7は、スイッチや各種センサなどからの信号に基づいて、基板処理装置1の各部の動作を制御する。 The control unit 7 controls the operation of each unit of the substrate processing apparatus 1 (carrier loading/unloading unit 2, lot forming unit 3, lot placement unit 4, lot transport unit 5, lot processing unit 6, etc.). The control section 7 controls the operation of each section of the substrate processing apparatus 1 based on signals from switches, various sensors, and the like.
 制御部7は、CPU(Central Processing Unit)、ROM(Read Only Memory)、RAM(Random Access Memory)、入出力ポートなどを有するマイクロコンピュータや各種の回路を含み、図示しない記憶部に記憶されたプログラムを読み出して実行することによって基板処理装置1の動作を制御する。制御部7は、コンピュータで読み取り可能な記憶媒体8を有する。記憶媒体8には、基板処理装置1において実行される各種の処理を制御する上記プログラムが格納される。プログラムは、コンピュータによって読み取り可能な記憶媒体8に記憶されていたものであって、他の記憶媒体から制御部7の記憶媒体8にインストールされたものであってもよい。 The control unit 7 includes a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), input/output ports, and various circuits, and programs stored in a storage unit (not shown). is read and executed to control the operation of the substrate processing apparatus 1 . The control unit 7 has a computer-readable storage medium 8 . The storage medium 8 stores the above programs for controlling various processes executed in the substrate processing apparatus 1 . The program may have been stored in the computer-readable storage medium 8 and installed in the storage medium 8 of the control unit 7 from another storage medium.
 コンピュータによって読み取り可能な記憶媒体8としては、たとえばハードディスク(HD)、フレキシブルディスク(FD)、コンパクトディスク(CD)、マグネットオプティカルディスク(MO)、メモリカードなどがある。 Examples of computer-readable storage media 8 include hard disks (HD), flexible disks (FD), compact disks (CD), magnet optical disks (MO), memory cards, and the like.
[処理槽の構成]
 次に、実施形態に係るエッチング処理に用いられる処理槽61の構成について図11を参照し説明する。図11は、実施形態に係る処理槽61の構成を示す図である。
[Structure of processing tank]
Next, the configuration of the processing tank 61 used for etching according to the embodiment will be described with reference to FIG. FIG. 11 is a diagram showing the configuration of the processing tank 61 according to the embodiment.
 図11に示すように、処理槽61は、1ロット分のウエハWをエッチング液に浸漬させることにより、ウエハW上に形成されたシリコン酸化膜11をエッチングするエッチング処理を行う。 As shown in FIG. 11, the processing tank 61 performs an etching process for etching the silicon oxide film 11 formed on the wafers W by immersing the wafers W for one lot in an etchant.
 処理槽61は、内槽100と、外槽110とを備える。また、処理槽61は、循環部120と、エッチング液供給部130とを備える。 The processing bath 61 includes an inner bath 100 and an outer bath 110 . The processing tank 61 also includes a circulation section 120 and an etchant supply section 130 .
 内槽100は、上方が開放されており、内部にエッチング液を貯留する。ロット(複数のウエハW)は、かかる内槽100に浸漬される。 The inner tank 100 is open at the top and stores an etchant inside. A lot (a plurality of wafers W) is immersed in such an inner bath 100 .
 外槽110は、上方が開放されており、内槽100の上部周囲に配置される。外槽110には、内槽100からオーバーフローしたエッチング液が流入する。 The outer tub 110 is open at the top and is arranged around the top of the inner tub 100 . The etchant overflowing from the inner bath 100 flows into the outer bath 110 .
 循環部120は、内槽100と外槽110との間でエッチング液を循環させる。循環部120は、循環路121と、ノズル122と、ポンプ123と、フィルタ124と、温度調整部125とを備える。 The circulation unit 120 circulates the etchant between the inner bath 100 and the outer bath 110 . The circulation section 120 includes a circulation path 121 , a nozzle 122 , a pump 123 , a filter 124 and a temperature adjustment section 125 .
 循環路121は、外槽110と内槽100とを接続する。循環路121の一端は、外槽110に接続され、循環路121の他端は、内槽100の内部に配置されたノズル122に接続される。 The circulation path 121 connects the outer tank 110 and the inner tank 100 . One end of the circulation path 121 is connected to the outer bath 110 and the other end of the circulation path 121 is connected to a nozzle 122 arranged inside the inner bath 100 .
 ポンプ123、フィルタ124および温度調整部125は、循環路121に設けられる。ポンプ123は、外槽110内のエッチング液を循環路121に送り出す。フィルタ124は、循環路121を流れるエッチング液から不純物を除去する。温度調整部125は、たとえばヒータであり、循環路121を流れるエッチング液の温度を、エッチング処理に適した温度に調整する。ポンプ123および温度調整部125は、制御部7によって制御される。 The pump 123 , the filter 124 and the temperature adjustment section 125 are provided in the circulation path 121 . A pump 123 sends out the etchant in the outer bath 110 to the circulation path 121 . Filter 124 removes impurities from the etchant flowing through circulation path 121 . The temperature adjustment unit 125 is, for example, a heater, and adjusts the temperature of the etchant flowing through the circulation path 121 to a temperature suitable for the etching process. Pump 123 and temperature adjuster 125 are controlled by controller 7 .
 循環部120は、エッチング液を外槽110から循環路121経由で内槽100内へ送る。内槽100内に送られたエッチング液は、内槽100からオーバーフローすることで、再び外槽110へと流出する。このようにして、エッチング液は、内槽100と外槽110との間を循環する。 The circulation unit 120 sends the etchant from the outer tank 110 to the inner tank 100 via the circulation path 121 . The etchant sent into the inner bath 100 overflows the inner bath 100 and flows out to the outer bath 110 again. Thus, the etchant circulates between the inner bath 100 and the outer bath 110 .
 エッチング液供給部130は、処理槽61に対してエッチング液を供給する。エッチング液供給部130は、エッチング液供給源131と、供給路132と、バルブ133と、切替部134とを備える。 The etchant supply unit 130 supplies the etchant to the processing bath 61 . The etchant supply unit 130 includes an etchant supply source 131 , a supply path 132 , a valve 133 and a switching unit 134 .
 エッチング液供給源131は、塩酸、金属塩および界面活性剤の少なくともいずれか一つが予め添加されたエッチング液を供給する。供給路132は、エッチング液供給源131に接続され、エッチング液供給源131から供給されるエッチング液を内槽100または外槽110に供給する。バルブ133は、供給路132に設けられ、供給路132を開閉する。切替部134は、供給路132に設けられ、供給路132を流れるエッチング液の流出先を内槽100と外槽110との間で切り替える。 The etchant supply source 131 supplies an etchant to which at least one of hydrochloric acid, metal salt, and surfactant has been added in advance. The supply path 132 is connected to the etchant supply source 131 and supplies the etchant supplied from the etchant supply source 131 to the inner bath 100 or the outer bath 110 . The valve 133 is provided in the supply path 132 and opens and closes the supply path 132 . The switching unit 134 is provided in the supply path 132 and switches the outflow destination of the etchant flowing through the supply path 132 between the inner tank 100 and the outer tank 110 .
 バルブ133および切替部134は、制御部7に電気的に接続されており、制御部7によって制御される。たとえば、制御部7は、空の状態の処理槽61にエッチング液を貯める場合には、バルブ133および切替部134を制御して、エッチング液供給源131から内槽100にエッチング液の新液を供給する。また、制御部7は、処理槽61に対してエッチング液の補充を行う場合には、バルブ133および切替部134を制御して、エッチング液供給源131から外槽110にエッチング液の新液を供給する。 The valve 133 and the switching section 134 are electrically connected to the control section 7 and controlled by the control section 7 . For example, when the etchant is stored in the empty processing bath 61, the control unit 7 controls the valve 133 and the switching unit 134 to supply a new etchant from the etchant supply source 131 to the inner bath 100. supply. Further, when the etching liquid is to be replenished to the processing tank 61, the control section 7 controls the valve 133 and the switching section 134 to supply new etching liquid from the etching liquid supply source 131 to the outer tank 110. supply.
[基板処理装置の具体的動作]
 次に、実施形態に係る基板処理装置1の具体的動作について図12を参照して説明する。図12は、実施形態に係る基板処理装置1が実行する処理の手順を示すフローチャートである。図12に示す処理手順は、制御部7による制御に従って実行される。
[Specific Operation of Substrate Processing Apparatus]
Next, specific operations of the substrate processing apparatus 1 according to the embodiment will be described with reference to FIG. 12 . FIG. 12 is a flow chart showing the procedure of processing executed by the substrate processing apparatus 1 according to the embodiment. The processing procedure shown in FIG. 12 is executed under the control of the control unit 7 .
 図12に示すように、基板処理装置1では、まず、準備処理が行われる(ステップS101)。準備処理では、図1に示したように、膜厚が異なる複数のシリコン酸化膜11を含む積層膜を有するウエハWが複数準備される。 As shown in FIG. 12, the substrate processing apparatus 1 first performs a preparation process (step S101). In the preparation process, as shown in FIG. 1, a plurality of wafers W each having a laminated film including a plurality of silicon oxide films 11 with different film thicknesses are prepared.
 つづいて、基板処理装置1では、ロットを形成する複数のウエハWに対し、エッチング液を用いたエッチング処理が行われる(ステップS102)。エッチング処理では、複数のウエハWを基板昇降機構63を用いて降下させることにより、処理槽61の内槽100に貯留されたエッチング液に複数のウエハWが浸漬される。 Subsequently, in the substrate processing apparatus 1, an etching process using an etchant is performed on a plurality of wafers W forming a lot (step S102). In the etching process, the plurality of wafers W are lowered using the substrate lifting mechanism 63 to immerse the plurality of wafers W in the etchant stored in the inner bath 100 of the processing bath 61 .
 このエッチング処理は、ウエハW上に形成された積層膜が、図1に示す初期状態から図2に示す積層面露出状態となるまで行われる。すなわち、エッチング処理は、ポリシリコン膜12に接するシリコン酸化膜11をエッチングすることによって、ポリシリコン膜12の積層面(上下面)を露出させる。 This etching process is performed until the laminated film formed on the wafer W changes from the initial state shown in FIG. 1 to the laminated surface exposed state shown in FIG. That is, the etching process exposes the lamination surfaces (upper and lower surfaces) of the polysilicon film 12 by etching the silicon oxide film 11 in contact with the polysilicon film 12 .
 本願発明者は、塩酸、金属塩および界面活性剤が添加されていないエッチング液と比較して、塩酸、金属塩および界面活性剤の少なくともいずれか一つが添加されたエッチング液は、シリコン酸化膜11ごとのエッチングレートのばらつきを低減することを実験により確認している。そこで、基板処理装置1では、塩酸、金属塩および界面活性剤の少なくともいずれか一つが添加されたエッチング液を用いてエッチング処理を行うこととした。これにより、シリコン酸化膜11ごとのエッチングレートのばらつきを低減することができる。 The inventors of the present application have found that the etching solution to which at least one of hydrochloric acid, a metal salt, and a surfactant are added is more effective than an etching solution to which hydrochloric acid, a metal salt, and a surfactant are not added. It has been confirmed experimentally that the variation in etching rate between each step is reduced. Therefore, in the substrate processing apparatus 1, an etching process is performed using an etchant to which at least one of hydrochloric acid, a metal salt, and a surfactant is added. Thereby, variations in the etching rate for each silicon oxide film 11 can be reduced.
 つづいて、基板処理装置1では、リンス処理が行われる(ステップS103)。リンス処理では、エッチング処理を終えた複数のウエハWがリンス処理用の処理槽62に搬送されて、処理槽62に貯留されたリンス液(脱イオン水等)に浸漬される。これにより、複数のウエハWからエッチング液が洗い流される。 Subsequently, a rinse process is performed in the substrate processing apparatus 1 (step S103). In the rinsing process, a plurality of wafers W that have undergone the etching process are transported to the processing tank 62 for the rinsing process and immersed in a rinse liquid (deionized water or the like) stored in the processing tank 62 . Thereby, the etchant is washed away from the plurality of wafers W. FIG.
 つづいて、基板処理装置1では、乾燥処理が行われる(ステップS104)。乾燥処理では、リンス処理を終えた複数のウエハWが乾燥処理用の処理槽91に搬送され、複数のウエハWの表面に付着したリンス液が処理ガスにより除去される。これにより、複数のウエハWが乾燥する。 Subsequently, a drying process is performed in the substrate processing apparatus 1 (step S104). In the drying process, a plurality of wafers W that have finished the rinsing process are transferred to the processing tank 91 for the drying process, and the rinsing liquid adhering to the surfaces of the plurality of wafers W is removed by the processing gas. Thereby, the plurality of wafers W are dried.
 その後、乾燥処理を終えた複数のウエハWは、キャリアステージ20に載置されたキャリア9に収容される。これにより、1ロット分の基板処理が終了する。 After that, the plurality of wafers W that have undergone the drying process are housed in the carrier 9 placed on the carrier stage 20 . Thus, substrate processing for one lot is completed.
 [変形例]
 実施形態に係る基板処理は、ウエハWを1枚ずつ処理する枚葉式の処理ユニットにも適用可能である。図13は、変形例に係る処理ユニットの構成例を示す図である。
[Variation]
The substrate processing according to the embodiment can also be applied to a single-wafer processing unit that processes wafers W one by one. FIG. 13 is a diagram illustrating a configuration example of a processing unit according to a modification;
 図13に示すように、変形例に係る処理ユニット200は、チャンバ220と、基板保持機構230と、ノズル240と、回収カップ250とを備える。 As shown in FIG. 13, the processing unit 200 according to the modification includes a chamber 220, a substrate holding mechanism 230, a nozzle 240, and a recovery cup 250.
 チャンバ220は、基板保持機構230とノズル240と回収カップ250とを収容する。チャンバ220の天井部には、FFU(Fan Filter Unit)221が設けられる。FFU221は、チャンバ220内にダウンフローを形成する。 The chamber 220 accommodates the substrate holding mechanism 230 , the nozzle 240 and the collection cup 250 . An FFU (Fan Filter Unit) 221 is provided on the ceiling of the chamber 220 . FFU 221 creates a downflow within chamber 220 .
 基板保持機構230は、保持部231と、支柱部232と、駆動部233とを備える。保持部231は、ウエハWを水平に保持する。支柱部232は、鉛直方向に延在する部材であり、基端部が駆動部233によって回転可能に支持され、先端部において保持部231を水平に支持する。駆動部233は、支柱部232を鉛直軸まわりに回転させる。かかる基板保持機構230は、駆動部233を用いて支柱部232を回転させることによって支柱部232に支持された保持部231を回転させ、これにより、保持部231に保持されたウエハWを回転させる。 The substrate holding mechanism 230 includes a holding portion 231 , a support portion 232 and a driving portion 233 . The holding part 231 holds the wafer W horizontally. The column portion 232 is a member extending in the vertical direction, the base end portion of which is rotatably supported by the drive portion 233, and the tip portion of which supports the holding portion 231 horizontally. The drive section 233 rotates the support section 232 around the vertical axis. The substrate holding mechanism 230 rotates the supporting part 231 supported by the supporting part 232 by rotating the supporting part 232 using the driving part 233, thereby rotating the wafer W held by the supporting part 231. .
 ノズル240は、保持部231に保持されたウエハWの上方に配置され、かかるウエハWに対して各種の処理液を供給する。 The nozzle 240 is arranged above the wafer W held by the holding part 231 and supplies various processing liquids to the wafer W.
 回収カップ250は、保持部231を取り囲むように配置され、保持部231の回転によってウエハWから飛散する処理液を捕集する。回収カップ250の底部には、排液口251が形成されており、回収カップ250によって捕集された処理液は、かかる排液口251から処理ユニット200の外部へ排出される。また、回収カップ250の底部には、FFU221から供給される気体を処理ユニット200の外部へ排出する排気口252が形成される。 The collection cup 250 is arranged to surround the holding portion 231 and collects the processing liquid scattered from the wafer W due to the rotation of the holding portion 231 . A drain port 251 is formed at the bottom of the recovery cup 250 , and the processing liquid collected by the recovery cup 250 is discharged to the outside of the processing unit 200 through the drain port 251 . An exhaust port 252 is formed at the bottom of the collection cup 250 to discharge the gas supplied from the FFU 221 to the outside of the processing unit 200 .
 処理ユニット200は、さらに、エッチング液供給部260と、リンス液供給部270とを備える。 The processing unit 200 further includes an etchant supply section 260 and a rinse liquid supply section 270 .
 エッチング液供給部260は、エッチング液供給源261と、バルブ262とを備え、エッチング液供給源261から供給されるエッチング液をノズル240に供給する。リンス液供給部270は、リンス液供給源271と、バルブ272とを備え、リンス液供給源271から供給されるリンス液(脱イオン水等)をノズル240に供給する。 The etchant supply unit 260 includes an etchant supply source 261 and a valve 262 and supplies the etchant supplied from the etchant supply source 261 to the nozzle 240 . The rinse liquid supply unit 270 includes a rinse liquid supply source 271 and a valve 272 and supplies the rinse liquid (deionized water or the like) supplied from the rinse liquid supply source 271 to the nozzle 240 .
 かかる処理ユニット200では、まず、エッチング処理が行われる。エッチング処理では、バルブ262が所定時間開かれることにより、基板保持機構230に保持されて回転するウエハWに対してエッチング液が供給される。 In such a processing unit 200, etching processing is first performed. In the etching process, the valve 262 is opened for a predetermined time to supply the etchant to the wafer W held and rotated by the substrate holding mechanism 230 .
 つづいて、処理ユニット200では、リンス処理が行われる。リンス処理では、バルブ272が所定時間開かれることにより、基板保持機構230に保持されて回転するウエハWに対してリンス液が供給される。その後、処理ユニット200では、乾燥処理が行われる。乾燥処理では、ウエハWの回転速度を増加させてウエハWからリンス液を振り切ることによってウエハWを乾燥させる。乾燥処理を終えると、1枚のウエハWに対する基板処理が終了する。 Subsequently, the processing unit 200 performs a rinse process. In the rinsing process, the valve 272 is opened for a predetermined time to supply the rinsing liquid to the wafer W held and rotated by the substrate holding mechanism 230 . After that, in the processing unit 200, a drying process is performed. In the drying process, the wafer W is dried by increasing the rotation speed of the wafer W to shake off the rinse liquid from the wafer W. FIG. When the drying process is completed, the substrate processing for one wafer W is completed.
 このように、実施形態に係る基板処理は、ウエハWを1枚ずつ処理する枚葉式の処理ユニットにも適用可能である。 Thus, the substrate processing according to the embodiment can also be applied to a single-wafer processing unit that processes wafers W one by one.
[その他の変形例]
 上記の実施形態では、ウエハW上に形成された積層膜において、ポリシリコン膜12と複数のシリコン酸化膜11の各々とが鉛直方向に互いに隣接して形成される例を示したが、積層膜の構造はこれに限られない。例えば、積層膜において、複数のシリコン酸化膜11の各々と、複数のシリコン酸化膜11の各々と隣接して形成される他の膜とは、水平方向に互いに隣接して形成されてもよい。
[Other variations]
In the above-described embodiment, in the laminated film formed on the wafer W, the polysilicon film 12 and each of the plurality of silicon oxide films 11 are formed adjacent to each other in the vertical direction. structure is not limited to this. For example, in the laminated film, each of the plurality of silicon oxide films 11 and another film formed adjacent to each of the plurality of silicon oxide films 11 may be formed adjacent to each other in the horizontal direction.
 また、上記の実施形態において、金属塩が添加されたエッチング液を用いてウエハWのエッチング処理(ステップS101)を行った後に、SC2(塩酸と過酸化水素の混合液)でウエハWの表面に残留する金属塩を除去する除去処理を行ってもよい。また、かかる場合、複数のシリコン酸化膜11の各々と隣接して形成される他の膜は、金属含有膜ではないことが好ましい。 Further, in the above embodiment, after performing the etching process (step S101) of the wafer W using the etchant to which the metal salt is added, the surface of the wafer W is coated with SC2 (mixed solution of hydrochloric acid and hydrogen peroxide). A removal treatment may be performed to remove residual metal salts. Further, in such a case, other films formed adjacent to each of the plurality of silicon oxide films 11 are preferably not metal-containing films.
 上述してきたように、実施形態に係る基板処理方法は、基板(例えば、ウエハW)を準備する工程と、基板のエッチング処理を行う工程とを含む。基板を準備する工程は、膜厚が異なる複数のシリコン酸化膜(例えば、シリコン酸化膜11)を含む積層膜を有する基板を準備する。基板のエッチング処理を行う工程は、塩酸、金属塩および界面活性剤の少なくともいずれか一つ添加されたエッチング液で基板のエッチング処理を行う。したがって、実施形態に係る基板処理方法によれば、膜厚が異なる複数のシリコン酸化膜を含む積層膜をエッチングする技術において、シリコン酸化膜ごとのエッチングレートのばらつきを低減することができる。 As described above, the substrate processing method according to the embodiment includes a step of preparing a substrate (for example, wafer W) and a step of etching the substrate. The step of preparing a substrate prepares a substrate having a laminated film including a plurality of silicon oxide films (for example, silicon oxide film 11) with different film thicknesses. In the step of etching the substrate, the substrate is etched with an etchant to which at least one of hydrochloric acid, a metal salt and a surfactant is added. Therefore, according to the substrate processing method according to the embodiment, it is possible to reduce variations in the etching rate for each silicon oxide film in the technique of etching a laminated film including a plurality of silicon oxide films having different film thicknesses.
 エッチング液における塩酸および金属塩の各々の濃度は、0.5wt%以上5wt%以下であってもよい。これにより、金属塩の種類に関わらず、シリコン酸化膜ごとのエッチングレートのばらつきを低減することができる。また、エッチング液における金属塩の濃度が5wt%以下であることにより、金属による基板の汚染を抑制することができる。 The concentration of each of hydrochloric acid and metal salt in the etching solution may be 0.5 wt% or more and 5 wt% or less. This makes it possible to reduce variations in etching rate for each silicon oxide film regardless of the type of metal salt. Further, by setting the concentration of the metal salt in the etching liquid to 5 wt % or less, contamination of the substrate with metal can be suppressed.
 エッチング液における界面活性剤の濃度は、0.5wt%以上5wt%以下であってもよい。これにより、界面活性剤の種類に関わらず、シリコン酸化膜ごとのエッチングレートのばらつきを低減することができる。また、エッチング液における界面活性剤の濃度が5wt%以下であることにより、界面活性剤により除去された有機物(汚れ)が基板の表面上に残留することを抑制することができる。 The concentration of the surfactant in the etchant may be 0.5 wt% or more and 5 wt% or less. This makes it possible to reduce variations in etching rate for each silicon oxide film regardless of the type of surfactant. Further, by setting the concentration of the surfactant in the etching liquid to 5 wt % or less, it is possible to suppress the organic matter (dirt) removed by the surfactant from remaining on the surface of the substrate.
 実施形態に係る基板処理方法は、基板のエッチング処理を行う工程の後に、SC2で基板の表面に残留する金属塩を除去する工程をさらに含んでもよい。これにより、金属による基板の汚染を抑制することができる。 The substrate processing method according to the embodiment may further include a step of removing metal salts remaining on the surface of the substrate in SC2 after the step of etching the substrate. As a result, contamination of the substrate with metal can be suppressed.
 今回開示された実施形態は全ての点で例示であって制限的なものではないと考えられるべきである。実に、上記した実施形態は多様な形態で具現され得る。また、上記の実施形態は、添付の請求の範囲およびその趣旨を逸脱することなく、様々な形態で省略、置換、変更されてもよい。 The embodiments disclosed this time should be considered illustrative in all respects and not restrictive. Indeed, the above-described embodiments may be embodied in many different forms. Also, the above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.
 なお、以上の実施形態に関し、さらに以下の付記を開示する。
(付記1)
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
 塩酸が添加されたエッチング液で前記基板のエッチング処理を行う工程と
 を含む、基板処理方法。
(付記2)
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
 金属塩が添加されたエッチング液で前記基板のエッチング処理を行う工程と
 を含む、基板処理方法。
(付記3)
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
 界面活性剤が添加されたエッチング液で前記基板のエッチング処理を行う工程と
 を含む、基板処理方法。
(付記4)
 前記積層膜は、さらに、前記複数のシリコン酸化膜の各々と隣接して形成される他の膜を含む積層膜であり、
 前記他の膜は、シリコン膜、ポリシリコン膜、シリコン窒化膜および金属含有膜の少なくとも1つから選択される、付記1~3のいずれか一つに記載の基板処理方法。
(付記5)
 前記積層膜において、前記他の膜と前記複数のシリコン酸化膜の各々とは、鉛直方向または水平方向に互いに隣接して形成される、付記4に記載の基板処理方法。
(付記6)
 前記複数のシリコン酸化膜の膜厚は、1nm以上30nm以下である、付記1~5のいずれか一つに記載の基板処理方法。
(付記7)
 前記エッチング液は、フッ酸を含む、付記1~6のいずれか一つに記載の基板処理方法。
(付記8)
 前記エッチング液における前記フッ酸の濃度は、0.1wt%以上50wt%以下である、付記7に記載の基板処理方法。
(付記9)
 前記エッチング液に添加される前の前記塩酸の濃度は、35wt%以上37wt%以下である、付記1に記載の基板処理方法。
(付記10)
 前記金属塩は、ハロゲン化アルカリ金属またはハロゲン化アルカリ土類金属である、付記2に記載の基板処理方法。
(付記11)
 前記ハロゲン化アルカリ金属は、Li、Na、K、RbおよびCsのうち少なくとも1つを含み、
 前記ハロゲン化アルカリ土類金属は、Mg、Ca、SrおよびBaのうち少なくとも1つを含む、付記10に記載の基板処理方法。
(付記12)
 前記エッチング液における前記塩酸および前記金属塩の各々の濃度は、0.5wt%以上5wt%以下である、付記1に記載の基板処理方法。
(付記13)
 前記界面活性剤は、陽イオン性界面活性剤または陰イオン性界面活性剤である、付記3に記載の基板処理方法。
(付記14)
 前記陽イオン性界面活性剤は、n-オクチルアミン塩酸塩(OACl)またはn-オクチルトリメチルアンモニウムクロリド(OTMACl)であり、
 前記陰イオン性界面活性剤は、ドデシルベンゼンスルホン酸ナトリウム(SDBS)である、付記13に記載の基板処理方法。
(付記15)
 前記エッチング液における前記界面活性剤の濃度は、0.5wt%以上5wt%以下である、付記3、13、14のいずれか一つに記載の基板処理方法。
(付記16)
 前記基板のエッチング処理を行う工程の後に、SC2で前記基板の表面に残留する前記金属塩を除去する工程をさらに含む、付記2に記載の基板処理方法。
(付記17)
 塩酸が添加されたエッチング液を貯留する処理槽と、
 各部を制御する制御部と
 を備え、
 前記制御部は、
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
 基板処理装置。
(付記18)
 金属塩が添加されたエッチング液を貯留する処理槽と、
 各部を制御する制御部と
 を備え、
 前記制御部は、
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
 基板処理装置。
(付記19)
 界面活性剤が添加されたエッチング液を貯留する処理槽と、
 各部を制御する制御部と
 を備え、
 前記制御部は、
 膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
 基板処理装置。
In addition, the following additional remarks are disclosed regarding the above embodiment.
(Appendix 1)
Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
and etching the substrate with an etchant to which hydrochloric acid is added.
(Appendix 2)
Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
and a step of etching the substrate with an etchant to which a metal salt is added.
(Appendix 3)
Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
and a step of etching the substrate with an etchant to which a surfactant is added.
(Appendix 4)
The laminated film is a laminated film further comprising another film formed adjacent to each of the plurality of silicon oxide films,
4. The substrate processing method according to any one of Appendices 1 to 3, wherein the other film is selected from at least one of a silicon film, a polysilicon film, a silicon nitride film and a metal-containing film.
(Appendix 5)
5. The substrate processing method according to appendix 4, wherein in the laminated film, the other film and each of the plurality of silicon oxide films are formed adjacent to each other in a vertical direction or a horizontal direction.
(Appendix 6)
6. The substrate processing method according to any one of appendices 1 to 5, wherein the film thickness of the plurality of silicon oxide films is 1 nm or more and 30 nm or less.
(Appendix 7)
7. The substrate processing method according to any one of appendices 1 to 6, wherein the etchant contains hydrofluoric acid.
(Appendix 8)
8. The substrate processing method according to appendix 7, wherein the concentration of the hydrofluoric acid in the etching liquid is 0.1 wt % or more and 50 wt % or less.
(Appendix 9)
The substrate processing method according to appendix 1, wherein the concentration of the hydrochloric acid before being added to the etching solution is 35 wt % or more and 37 wt % or less.
(Appendix 10)
The substrate processing method according to appendix 2, wherein the metal salt is an alkali metal halide or an alkaline earth metal halide.
(Appendix 11)
the alkali metal halide comprises at least one of Li, Na, K, Rb and Cs;
11. The substrate processing method according to Appendix 10, wherein the alkaline earth metal halide contains at least one of Mg, Ca, Sr and Ba.
(Appendix 12)
The substrate processing method according to appendix 1, wherein the concentration of each of the hydrochloric acid and the metal salt in the etching solution is 0.5 wt % or more and 5 wt % or less.
(Appendix 13)
The substrate processing method according to Appendix 3, wherein the surfactant is a cationic surfactant or an anionic surfactant.
(Appendix 14)
the cationic surfactant is n-octylamine hydrochloride (OACl) or n-octyltrimethylammonium chloride (OTMACl);
14. The substrate processing method according to Appendix 13, wherein the anionic surfactant is sodium dodecylbenzenesulfonate (SDBS).
(Appendix 15)
15. The substrate processing method according to any one of appendices 3, 13, and 14, wherein the concentration of the surfactant in the etching solution is 0.5 wt % or more and 5 wt % or less.
(Appendix 16)
The substrate processing method according to appendix 2, further comprising a step of removing the metal salt remaining on the surface of the substrate in SC2 after the step of etching the substrate.
(Appendix 17)
a processing tank for storing an etchant to which hydrochloric acid has been added;
and a control unit that controls each part,
The control unit
A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
(Appendix 18)
a processing tank for storing an etchant to which a metal salt has been added;
and a control unit that controls each part,
The control unit
A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
(Appendix 19)
a processing tank for storing an etchant to which a surfactant is added;
and a control unit that controls each part,
The control unit
A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
1 基板処理装置
7 制御部
10 シリコン基板
11 シリコン酸化膜
12 ポリシリコン膜
15 溝
16p 水クラスター
16s 球状構造体
60 エッチング処理装置
61 処理槽
100 内槽
110 外槽
120 循環部
130 エッチング液供給部
W ウエハ
1 substrate processing apparatus 7 control unit 10 silicon substrate 11 silicon oxide film 12 polysilicon film 15 groove 16p water cluster 16s spherical structure 60 etching processing unit 61 processing tank 100 inner tank 110 outer tank 120 circulation unit 130 etching liquid supply unit W wafer

Claims (19)

  1.  膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
     塩酸が添加されたエッチング液で前記基板のエッチング処理を行う工程と
     を含む、基板処理方法。
    Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
    and etching the substrate with an etchant to which hydrochloric acid is added.
  2.  膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
     金属塩が添加されたエッチング液で前記基板のエッチング処理を行う工程と
     を含む、基板処理方法。
    Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
    and a step of etching the substrate with an etchant to which a metal salt is added.
  3.  膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を準備する工程と、
     界面活性剤が添加されたエッチング液で前記基板のエッチング処理を行う工程と
     を含む、基板処理方法。
    Preparing a substrate having a laminated film containing a plurality of silicon oxide films with different film thicknesses;
    and a step of etching the substrate with an etchant to which a surfactant is added.
  4.  前記積層膜は、さらに、前記複数のシリコン酸化膜の各々と隣接して形成される他の膜を含む積層膜であり、
     前記他の膜は、シリコン膜、ポリシリコン膜、シリコン窒化膜および金属含有膜の少なくとも1つから選択される、請求項1~3のいずれか一つに記載の基板処理方法。
    The laminated film is a laminated film further comprising another film formed adjacent to each of the plurality of silicon oxide films,
    4. The substrate processing method according to claim 1, wherein said other film is selected from at least one of a silicon film, a polysilicon film, a silicon nitride film and a metal-containing film.
  5.  前記積層膜において、前記他の膜と前記複数のシリコン酸化膜の各々とは、鉛直方向または水平方向に互いに隣接して形成される、請求項4に記載の基板処理方法。 5. The substrate processing method according to claim 4, wherein in said laminated film, said another film and each of said plurality of silicon oxide films are formed adjacent to each other in a vertical direction or a horizontal direction.
  6.  前記複数のシリコン酸化膜の膜厚は、1nm以上30nm以下である、請求項1~3のいずれか一つに記載の基板処理方法。 The substrate processing method according to any one of claims 1 to 3, wherein the film thickness of the plurality of silicon oxide films is 1 nm or more and 30 nm or less.
  7.  前記エッチング液は、フッ酸を含む、請求項1~3のいずれか一つに記載の基板処理方法。 The substrate processing method according to any one of claims 1 to 3, wherein the etchant contains hydrofluoric acid.
  8.  前記エッチング液における前記フッ酸の濃度は、0.1wt%以上50wt%以下である、請求項7に記載の基板処理方法。 The substrate processing method according to claim 7, wherein the concentration of said hydrofluoric acid in said etching liquid is 0.1 wt% or more and 50 wt% or less.
  9.  前記エッチング液に添加される前の前記塩酸の濃度は、35wt%以上37wt%以下である、請求項1に記載の基板処理方法。 The substrate processing method according to claim 1, wherein the concentration of said hydrochloric acid before being added to said etching liquid is 35 wt% or more and 37 wt% or less.
  10.  前記金属塩は、ハロゲン化アルカリ金属またはハロゲン化アルカリ土類金属である、請求項2に記載の基板処理方法。 The substrate processing method according to claim 2, wherein the metal salt is an alkali metal halide or an alkaline earth metal halide.
  11.  前記ハロゲン化アルカリ金属は、Li、Na、K、RbおよびCsのうち少なくとも1つを含み、
     前記ハロゲン化アルカリ土類金属は、Mg、Ca、SrおよびBaのうち少なくとも1つを含む、請求項10に記載の基板処理方法。
    the alkali metal halide comprises at least one of Li, Na, K, Rb and Cs;
    11. The substrate processing method of claim 10, wherein the alkaline earth metal halide includes at least one of Mg, Ca, Sr and Ba.
  12.  前記エッチング液における前記塩酸の濃度は、0.5wt%以上5wt%以下である、請求項1に記載の基板処理方法。 The substrate processing method according to claim 1, wherein the concentration of said hydrochloric acid in said etchant is 0.5 wt% or more and 5 wt% or less.
  13.  前記界面活性剤は、陽イオン性界面活性剤または陰イオン性界面活性剤である、請求項3に記載の基板処理方法。 The substrate processing method according to claim 3, wherein the surfactant is a cationic surfactant or an anionic surfactant.
  14.  前記陽イオン性界面活性剤は、n-オクチルアミン塩酸塩(OACl)またはn-オクチルトリメチルアンモニウムクロリド(OTMACl)であり、
     前記陰イオン性界面活性剤は、ドデシルベンゼンスルホン酸ナトリウム(SDBS)である、請求項13に記載の基板処理方法。
    the cationic surfactant is n-octylamine hydrochloride (OACl) or n-octyltrimethylammonium chloride (OTMACl);
    14. The substrate processing method of claim 13, wherein the anionic surfactant is sodium dodecylbenzenesulfonate (SDBS).
  15.  前記エッチング液における前記界面活性剤の濃度は、0.5wt%以上5wt%以下である、請求項3、13、14のいずれか一つに記載の基板処理方法。 The substrate processing method according to any one of claims 3, 13 and 14, wherein the concentration of said surfactant in said etching liquid is 0.5 wt% or more and 5 wt% or less.
  16.  前記基板のエッチング処理を行う工程の後に、SC2で前記基板の表面に残留する前記金属塩を除去する工程をさらに含む、請求項2に記載の基板処理方法。 The substrate processing method according to claim 2, further comprising a step of removing the metal salt remaining on the surface of the substrate in SC2 after the step of etching the substrate.
  17.  塩酸が添加されたエッチング液を貯留する処理槽と、
     各部を制御する制御部と
     を備え、
     前記制御部は、
     膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
     基板処理装置。
    a processing tank for storing an etchant to which hydrochloric acid has been added;
    and a control unit that controls each part,
    The control unit
    A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing tank.
  18.  金属塩が添加されたエッチング液を貯留する処理槽と、
     各部を制御する制御部と
     を備え、
     前記制御部は、
     膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
     基板処理装置。
    a processing tank for storing an etchant to which a metal salt has been added;
    and a control unit that controls each part,
    The control unit
    A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
  19.  界面活性剤が添加されたエッチング液を貯留する処理槽と、
     各部を制御する制御部と
     を備え、
     前記制御部は、
     膜厚が異なる複数のシリコン酸化膜を含む積層膜を有する基板を前記処理槽に貯留される前記エッチング液に浸漬させることによって、前記基板のエッチング処理を行う
     基板処理装置。
    a processing tank for storing an etchant to which a surfactant is added;
    and a control unit that controls each part,
    The control unit
    A substrate processing apparatus for etching a substrate by immersing a substrate having a laminated film including a plurality of silicon oxide films with different film thicknesses in the etchant stored in the processing bath.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181094A (en) * 1994-12-26 1996-07-12 Nippondenso Co Ltd Surface flattening method of semiconductor substrate
JPH10177998A (en) * 1996-12-18 1998-06-30 Sutera Chemiphar Kk Etchant
JP2012227558A (en) * 2012-08-22 2012-11-15 Stella Chemifa Corp Microfabrication processing agent and microfabrication processing method
JP2013541831A (en) * 2010-09-06 2013-11-14 ユ−ジーン テクノロジー カンパニー.リミテッド Manufacturing method of semiconductor device
JP2014500608A (en) * 2010-10-14 2014-01-09 ユ−ジーン テクノロジー カンパニー.リミテッド Method and apparatus for manufacturing a three-dimensional memory device
JP2014057039A (en) * 2012-08-10 2014-03-27 Fujifilm Corp Process of manufacturing semiconductor substrate product and etchant
WO2019230833A1 (en) * 2018-05-31 2019-12-05 学校法人 関西大学 Method for etching silicon semiconductor substrate, method for manufacturing semiconductor device, and etching solution

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831794A (en) 1994-07-12 1996-02-02 Nippon Steel Corp Processing apparatus for semiconductor wafer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181094A (en) * 1994-12-26 1996-07-12 Nippondenso Co Ltd Surface flattening method of semiconductor substrate
JPH10177998A (en) * 1996-12-18 1998-06-30 Sutera Chemiphar Kk Etchant
JP2013541831A (en) * 2010-09-06 2013-11-14 ユ−ジーン テクノロジー カンパニー.リミテッド Manufacturing method of semiconductor device
JP2014500608A (en) * 2010-10-14 2014-01-09 ユ−ジーン テクノロジー カンパニー.リミテッド Method and apparatus for manufacturing a three-dimensional memory device
JP2014057039A (en) * 2012-08-10 2014-03-27 Fujifilm Corp Process of manufacturing semiconductor substrate product and etchant
JP2012227558A (en) * 2012-08-22 2012-11-15 Stella Chemifa Corp Microfabrication processing agent and microfabrication processing method
WO2019230833A1 (en) * 2018-05-31 2019-12-05 学校法人 関西大学 Method for etching silicon semiconductor substrate, method for manufacturing semiconductor device, and etching solution

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