JPWO2019003313A1 - Debug device - Google Patents

Abstract

A debugging device (100) according to the invention includes a program execution unit (12) for executing an instruction included in a verification target sequence program (16), an instruction executed by the program execution unit (12), and an instruction executed. Operation verification status determination unit (14) that determines the execution type and the execution type that represents the relationship between the execution result of the instruction immediately before the executed instruction and the execution type determined by the operation verification status determination unit (14) Operation verification status storage unit (15) that stores the execution status of each instruction, execution type, and identification information that identifies the executed instruction, and the instruction executed by the program execution unit (12) And an operation verification status display unit (21) for displaying the execution type of the executed instruction in a format that can be visually recognized according to the execution status of the instruction.

Description

  The present invention relates to a debugging apparatus used for debugging a sequence program.

  In general, in program development, operation verification is performed to determine whether the created program performs a desired operation, and debugging is performed such that if a defect is found by operation verification, the program is corrected to eliminate the defect.

  The coverage rate of program operation verification is called coverage, and the program used for operation verification and debugging can be considered to have no defects, so coverage is used as a program quality indicator. There are several types of coverage, and representatively, there is C0 coverage which indicates the ratio of processing executed one or more times to all processing constituting a program. In addition, coverage can also be used as an indicator that indicates the progress of operation verification in program development.

  Sequence programs are used in the FA (Factory Automation) field that realizes automation of work at production sites such as factories. The sequence program is configured by combining a plurality of instructions, which is the minimum unit for performing a certain process. An instruction has an attribute called an execution condition, and the execution necessity of the instruction is determined based on the execution condition and the result of a logical expression (hereinafter referred to as a pre-condition) that performs some calculation on the immediately preceding instruction. The case where the pre-condition is satisfied is called true, and the case where it is not satisfied is called false.

  There are multiple types of execution conditions, and the instruction is executed only when the precondition is true, not executed when the precondition is false, ON when executed, and the instruction is executed only when the precondition changes from false to true There is a rising execution that is performed and a constant execution in which an instruction is always executed regardless of the truth or falseness of the pre-condition. The instruction for constant execution has two types of execution types of ON execution and OFF execution, and the execution results of ON execution and OFF execution are different. That is, the instruction to be always executed differs in the contents to be executed depending on whether the pre-condition is true or false. ON execution is performed when the precondition is true, and OFF execution is performed when the precondition is false.

  As described above, since instructions constituting a sequence program have execution conditions that are not available in commonly used programming languages such as C, such as constant execution, operation verification necessary to obtain coverage is also possible. It is different from the commonly used programming language. For example, consider the case where the C0 coverage is set to 100%. The C0 coverage is an index indicating the ratio of executed processing to all executable processing. In a general program, if the condition under which the process is executed is false, the process is skipped. Therefore, among the instructions of the operation verification target, only the process executed when the condition under which the process is executed is true is evaluated. C0 coverage would then be 100%. On the other hand, in a sequence program, it is necessary to consider the execution conditions of each instruction. In the case where the instruction subject to operation verification includes an instruction for constant execution, in order to make the C0 coverage 100%, it is necessary to verify both ON execution and OFF execution of constant execution.

  Patent Document 1 discloses a sequence control system which collates a definition file of a sequence control circuit diagram with a change state of a register, calculates an operation coverage percentage which is coverage from the comparison result, and displays the operation coverage percentage. .

JP, 2000-293208, A

  Techniques for visually representing coverage of a general programming language and techniques for quantitatively representing by percentage are implemented only for instructions executed when the precondition is true. On the other hand, even in the case of a sequence program, even in the case of the same instruction, the type of execution may differ depending on the pre-condition, and coverage can not be measured accurately only by verification when the pre-condition is true. For this reason, there is a problem that visual representation of coverage is difficult in the sequence program, and progress management and confirmation of operation verification are difficult.

  Patent Document 1 discloses a technique for calculating coverage of a sequence control circuit diagram and a test pattern. However, the coverage is calculated from the presence or absence of the change of the register, and the execution types of the instruction such as ON execution and OFF execution are not distinguished. Therefore, there is a problem that it is difficult for the user to confirm the execution type of the executed instruction and to determine whether the verification of the constantly executed instruction is completed or not, which makes it difficult to efficiently perform the debugging.

  The present invention has been made in view of the above, and it is an object of the present invention to obtain a debugging device that improves the efficiency of debugging work.

  In order to solve the problems described above and achieve the object, the debugging device according to the present invention includes an execution unit that executes instructions included in a sequence program, an instruction executed by the execution unit, and an execution of the executed instructions. A determination unit that determines an execution type representing a relation between contents and an execution result of an instruction immediately before the executed instruction; Also, the debugging device executes the execution by the storage unit that stores the execution status of the instruction for each execution type determined by the determination unit, the execution type, and the identification information that identifies the executed instruction, and the execution unit And a display unit for displaying the executed instruction and the execution type of the executed instruction in a viewable form according to the execution or non-execution of the instruction.

  The debugging device according to the present invention has an effect that the work efficiency of debugging can be improved.

FIG. 1 is a diagram showing an example of the configuration of a debugging device according to a first embodiment. A diagram showing an example of an operation verification setting dialog box displayed when the operation verification setting input unit according to the first embodiment receives an operation verification setting. A diagram showing an example of a sequence program executed by a PLC (Programmable Logic Controller) according to a first embodiment and an instruction constituting the sequence program FIG. 6 is a diagram showing an example of a format for storing the operation verification status collected by the operation verification status determination unit according to the first embodiment. A diagram showing a display example in the case where the operation verification status display unit according to the first embodiment notifies the user of the operation verification status by changing the display background of the sequence program. The figure which shows another display example in the case where the operation verification condition display part concerning Embodiment 1 notifies a user of the condition of operation verification by changing the display background of a sequence program. A diagram showing a display example in the case where the operation verification status display unit according to the first embodiment notifies the user by changing the mark displayed by associating the operation verification status with each command of the sequence program. A diagram showing a display example when the operation verification status display unit according to the first embodiment represents the operation verification status by changing the display of the program. The flowchart which shows the operation where the debug device which depends on the form 1 of execution displays operational verification circumstance The flowchart which shows the operation | movement which the operation verification condition display part concerning Embodiment 1 performs a display based on the one or more operation verification condition which was selected out of several operation verification conditions A diagram showing an example of an operation verification status selection screen displayed on a display device by the operation verification status display unit according to the first embodiment. The figure which shows the hardware constitutions of PLC of the debugging apparatus concerning Embodiment 1 A diagram showing an example of configuration of a debugging device according to a second embodiment

  Hereinafter, a debugging device according to an embodiment of the present invention will be described in detail based on the drawings. The present invention is not limited by the embodiment.

Embodiment 1
FIG. 1 is a diagram showing a configuration example of a debugging device according to a first embodiment of the present invention. The debugging device 100 according to the first embodiment includes a programmable logic controller (PLC: Programmable Logic Controller) 1 and an engineering tool 20 in the computer 2. The engineering tool 20 is realized by the computer 2 executing a program for operating as the engineering tool 20. The computer 2 includes various hardwares such as a processor that executes a program for operating as the engineering tool 20, a memory that holds the program and various data, a display that is a display, an input device that is a mouse and a keyboard, and a communication interface. The PLC 1 and the computer 2 are connected via the network cable 3. Note that wireless connection may be used for the connection path.

  The PLC 1 includes a program memory 11, a program execution unit 12, and an operation verification result management unit 13. The operation verification result management unit 13 includes an operation verification status determination unit 14 and an operation verification status storage unit 15. The PLC 1 has two operation modes, specifically, a normal mode for controlling the controlled device and a debug mode for debugging the sequence program, and the user operates the switching means such as a switch (not shown). Is configured to be able to select the operation mode. The operation verification result management unit 13 operates when the debug mode is selected.

  The program memory 11 is a memory for storing a sequence program for controlling the controlled device, and holds a verification target sequence program 16. The verification target sequence program 16 is a program to be debugged using the debugging device 100. The program execution unit 12 is an execution unit that executes the sequence program held in the program memory 11. The program execution unit 12 executes the verification target sequence program 16 when the debug mode is selected. The verification target sequence program 16 is a sequence program designated by the user from among the sequence programs held in the program memory 11. The program execution unit 12 also has a device memory 17. The device memory 17 is a memory that holds various device values whose values are updated according to the execution content when the program execution unit 12 executes the sequence program. The device value indicates the value of control information that the PLC 1 uses to control the control target device. In the FA field, information identifying control information is called a device, and the device value indicates the state of the control target device.

  When the program execution unit 12 is executing the verification target sequence program 16 in the debug mode, the operation verification status determination unit 14 of the operation verification result management unit 13 determines the combination of instruction execution type, instruction execution availability, and instruction, The operation verification status is acquired and stored in the operation verification status storage unit 15. That is, the operation verification status determination unit 14 is a determination unit that determines the execution type of the instruction in the verification target sequence program 16 executed by the program execution unit 12 and the executed instruction, and the instruction for which the determination result has been executed , And stored in the operation verification status storage unit 15 in association with the above. The execution type of the instruction is information such as ON execution and OFF execution described above, and represents the relationship between the content to be executed by the instruction and the execution result of the instruction immediately before this instruction. The operation verification status determination unit 14 analyzes the device value read out from the device memory 17 of the program execution unit 12 to acquire the operation verification status. The operation verification status determination unit 14 can know whether or not an instruction corresponding to a specific device value has been executed by monitoring whether or not the specific device value in the device memory 17 has been updated. The operation verification status determination unit 14 can also know which instruction in the sequence program the program execution unit 12 intends to execute by monitoring the device value in the device memory 17. The execution type and the pre-condition of each instruction can be known by analyzing the sequence program. The operation verification status storage unit 15 of the operation verification result management unit 13 is a storage unit that receives and stores the operation verification status acquired by the operation verification status determination unit 14.

  The engineering tool 20 includes an operation verification status display unit 21, an operation verification setting input unit 22, and an operation verification setting writing unit 23.

  The operation verification status display unit 21 displays the progress status of the operation verification of the verification target sequence program 16 based on the operation verification status stored in the operation verification status storage unit 15 in a format that allows the user to view it. It is a display part displayed on (not shown). The operation verification status display unit 21 also has a function of displaying a sequence program on a display device.

  The operation verification setting input unit 22 receives the setting of the sequence program to be operation verified, the setting of the number of executions of the sequence program to be operation verified, and the setting of the execution type to be verified from the user as the operation verification setting. FIG. 2 is a diagram showing an example of the operation verification setting dialog box displayed by the display device when the operation verification setting input unit 22 according to the first embodiment receives the operation verification setting. The operation verification setting dialog box shown in FIG. 2 is configured such that the verification target program name and the verification target execution type can be set by pull-down, and the verification target execution frequency can be set by numerical input to the text box. When the OK button is pressed in the state of the content shown in FIG. 2, the operation verification setting input unit 22 verifies a total of 10 times for the ON execution instruction included in the sequence program whose name is MAIN. Accept the operation verification settings of the content to be performed. In the verification target execution type, ON execution and OFF execution can be individually designated, and both ON execution and OFF execution can be selected as verification targets. The operation verification setting is not limited to the verification target program name, the verification target execution frequency, and the verification target execution type shown in FIG. Other information may be included in the operation verification setting. In the present embodiment, the operation verification setting input unit 22 receives the input of the operation verification setting from the user. However, when the file described in the prescribed format is input, the information of the operation verification setting of the engineering tool 20 is It is also possible to get

  The operation verification setting writing unit 23 writes information indicating the operation verification setting received by the operation verification setting input unit 22 in the operation verification state determination unit 14 of the operation verification result management unit 13 and operates according to the written information. The operation verification status determination unit 14 is set. If the operation verification setting input unit 22 receives the operation verification setting of the content shown in FIG. 2 and the information corresponding to this is written in the operation verification state determination unit 14, the operation is performed. When the sequence program whose name is MAIN is executed by the program execution unit 12, the verification status determination unit 14 monitors whether an instruction for ON execution is executed until the sequence program is executed ten times. Do. In this case, the operation verification status determination unit 14 writes the monitoring result until the sequence program is executed ten times in the operation verification status storage unit 15 as the operation verification status.

  FIG. 3 is a diagram showing an example of a sequence program executed by the PLC 1 according to the first embodiment and instructions constituting the sequence program. The sequence program shown in FIG. 3 is created by a program creation unit whose illustration of the engineering tool 20 is omitted. The sequence program is converted from the PLC1 into an executable code, transmitted from the engineering tool 20 to the PLC1, and written to the program memory 11 of the PLC1. FIG. 3 shows an example of a sequence program created in ladder language. “(0)”, “(2)”, “(4)” and “(6)” described in FIG. 3 are step numbers.

  FIG. 4 is a diagram illustrating an example of a format in which the operation verification status determination unit 14 according to the first embodiment stores the operation verification status collected from the program execution unit 12 in the operation verification status storage unit 15. As shown in FIG. 4, the operation verification status includes a step number representing an instruction, a run type representing an execution condition of the instruction, an ON execution completion flag, and an OFF execution completion flag. The step number is identification information of the instruction. The identification information is information for specifying which instruction has been executed among the executed sequence programs. If the run type is '0', it indicates constant execution, and if '1' indicates an execution condition that is not constant execution. The operation verification status determination unit 14 reads the device value stored in the device memory 17 of the program execution unit 12 to confirm which step number an instruction has been executed and the pre-conditions for executing the instruction. Check the ON execution completion flag or the OFF execution completion flag according to the confirmation result. In the operation verification status shown in FIG. 4, the ON execution of the instruction corresponding to the step number '0' has been executed, the OFF execution of the instruction corresponding to the step number '2' has been executed, and the operation verification status corresponds to the step number '4' It shows that the ON execution and the OFF execution of the instruction have been executed, and the ON execution and the OFF execution of the instruction corresponding to the step number “8” have been executed. The storage format of the operation verification status is not limited to that shown in FIG. If it is known which instruction has been executed under which execution condition, it may be stored in the form of binary data or text data.

  Subsequently, a format in which the operation verification status display unit 21 of the engineering tool 20 displays the operation verification status on the display device will be described using FIGS. 5 to 8.

  FIG. 5 is a diagram showing a display example in the case where the operation verification status display unit 21 according to the first embodiment notifies the user of the operation verification status by changing the display background of the sequence program. FIG. 5 shows an example in which the display background of the sequence program shown in FIG. 3 is changed according to the execution status of each instruction included in the sequence program. A representative example of the method of changing the display background is the change of color. For example, if both ON execution and OFF execution have been executed, then blue, if only ON execution has been performed, the background color is orange, and if only OFF execution has been performed, the background color is yellow, ON execution and OFF execution The background color is white if both are not running.

  FIG. 6 is a diagram showing another display example in the case where the operation verification status display unit 21 according to the first embodiment notifies the user of the operation verification status by changing the display background of the sequence program. In the example shown in FIG. 6, in addition to the change of the background color, both the ON execution and the OFF execution are prevented from displaying the executed instruction. By not displaying the executed instruction for both the ON execution and the OFF execution, the user can easily know how much the instruction whose operation verification is not completed remains. In the example shown in FIG. 6, since the ON execution and the OFF execution have already been executed for the instruction with the step number 4, the instruction with the step number 4 is not displayed.

  FIG. 7 shows a display example in the case where the operation verification status display unit 21 according to the first embodiment notifies the user by changing the mark displayed by associating the operation verification status with each instruction of the sequence program. FIG. FIG. 7 shows an example in which the execution status of each instruction included in the sequence program shown in FIG. 3 is represented by a black circle (●), an open circle (○) and a double circle (◎). . Specifically, '●' is given to an instruction that has been ON-executed only, and '○' is given to an instruction that has only OFF-execution, and both ON and OFF executions are instructions that have been executed. Is given '' '.

  FIG. 8 is a diagram showing a display example in the case where the operation verification status display unit 21 according to the first embodiment represents the status of the operation verification by changing the display of the program. FIG. 8 shows an example showing the state of operation verification by changing the display of a path and an instruction that has been turned ON even once. As a method of changing the display of the ON-executed path and the instruction, a method may be considered in which it is represented by a broken line in a state where the ON is not performed and is changed to a solid line when the ON is performed. In addition, it is conceivable to change the display color between the state in which the ON state is not executed and the state in which the ON state is performed. The display change method may be any method as long as it is known that the ON execution has been performed.

  Although the coverage rate of the coverage is displayed by color coding or the like in FIGS. 5 to 8, the coverage rate may simply be displayed on the display screen as “performing ○%”. Such a display may be displayed together on the ladder program of FIGS. In addition, display by color coding or the like and display by numerical values may be performed together. The coverage rate of the coverage is calculated by the operation verification status display unit 21 based on the operation verification status stored in the operation verification status storage unit 15. Note that the operation verification status display unit 21 calculates coverage coverage assuming that the operation verification of the instruction is completed when both the ON execution and the OFF execution have already been executed for the instruction whose execution condition is always execution. Do.

  Subsequently, an operation in which the debug device 100 displays the operation verification status will be described with reference to FIG. FIG. 9 is a flowchart showing an operation of the debugging device 100 according to the first embodiment to display the operation verification status.

  In the operation in which the debug device 100 displays the operation verification status, the operation verification status determination unit 14 outputs the device value from the device memory 17 for each step while the program execution unit 12 is executing the verification target sequence program 16. Based on the collected and collected device values, it is determined whether or not an instruction has been executed (step S11). In addition, the monitor technique of the existing sequence program can be used for determination of the execution presence or absence of an instruction. Further, the execution type of the instruction can be determined from the type of the execution condition of the corresponding instruction and the pre-condition. The operation verification status determination unit 14 determines the presence or absence of the execution of the instruction and the execution type based on the collected device values.

  Next, the operation verification status determination unit 14 stores the determination result, that is, the presence or absence of the execution of the instruction and the execution type in the operation verification status storage unit 15 in association with the step number (step S12). It is the operation verification status shown in FIG. 4 in which the presence or absence of the execution of the instruction and the execution type and the step number are associated with each other.

  Next, the operation verification status display unit 21 displays the execution status and execution type of each instruction of the verification target sequence program 16 on the display device based on the operation verification status stored in the operation verification status storage unit 15 ( Step S13).

  In step S13 shown in FIG. 9, the operation verification status display unit 21 displays the screen of the content example shown in FIG. 5 to FIG. When a plurality of operation verification states are stored in the operation verification state storage unit 15, the operation verification state display unit 21 is based on one or more operation verification states selected by the user from the plurality of operation verification states. Generate a display screen. Generally, in the program debugging operation, while changing the setting of the operating condition of the program, the program is executed under a plurality of operating conditions to confirm the presence or absence of a defect. Therefore, operation verification results corresponding to each of a plurality of operation conditions are obtained. In the case of the debugging device 100 according to the present embodiment, the operation verification setting described using FIG. 2 corresponds to the operation condition of the program, and the operation verification state described using FIG. 4 corresponds to the operation verification result of the program. . That is, the operation verification status storage unit 15 stores a plurality of operation verification statuses.

  FIG. 10 is a flowchart showing an operation of the operation verification status display unit 21 according to the first embodiment to perform display based on one or more operation verification statuses selected from among a plurality of operation verification statuses.

  When performing the display in step S13 shown in FIG. 9, the operation verification status display unit 21 first displays a screen for selecting the operation verification status on the display device (step S21). The display in this step S21 can be the screen shown in FIG. FIG. 11 is a diagram showing an example of the operation verification status selection screen displayed on the display device by the operation verification status display unit 21 according to the first embodiment. In the screen display example shown in FIG. 11, a list of file names of the operation verification status (operation verification status _001, operation verification status 002, ...) stored in the operation verification status storage unit 15 and each file are selected. And a display start button and a cancel button. The user selects the operation verification status to be displayed by putting a check in the check box, and starts displaying the operation verification status by pressing the display start button. That is, after the operation verification status display unit 21 executes step S21 to display the screen shown in FIG. 11 on the display device, one or more files of the operation verification status are selected, and the display start button is pressed. Wait for

  If one or more operation verification states are selected and the display start button is pressed, operation verification state display unit 21 selects one of the states shown in FIGS. 5 to 8 based on the selected operation verification state. The screen of any one content example is displayed on the display device (step S22). When step S22 is executed in a state where a plurality of operation verification states are selected, the operation verification state display unit 21 merges the contents of the selected operation verification states, and performs display according to the operation verification states after merging.

  As an example, consider that the operation verification status _ 001 and the operation verification status _ 002 are selected, and the operation verification status _ 001 is the result of executing only ON execution, and the operation verification status _ 002 is the result of executing only OFF execution. In this case, by analyzing the operation verification status _ 001 and the operation verification status _ 002, the operation verification status display unit 21 determines whether both the ON execution and the OFF execution of a certain instruction have been executed. Figure out which of the two is not already executed or which is not already executed, and the screen shows the execution status of each instruction ON and OFF (see Figure 5) The screen of any one of the content examples shown in FIG. 8 is displayed on the display device.

  Also, as another example, operation verification status _ 001 and operation verification status _ 002 are selected, and in operation verification status _ 001, ON execution of an instruction for continuous execution of step number XX (hereinafter referred to as instruction A) is executed Consider a case where information indicating that OFF execution is not executed is included, and information indicating that ON execution of instruction A is not executed but information indicating that OFF execution is executed is included in operation verification status _002. . In this case, the operation verification status display unit 21 analyzes the operation verification status _ 001 and the operation verification status _ 002 to find that both the ON execution and the OFF execution of the instruction A have been executed, ie, verified. Therefore, the operation verification status display unit 21 displays, on the display device, a screen with contents that allow visual confirmation that the ON execution and the OFF execution of the instruction A have been verified.

  Subsequently, the hardware configuration of the PLC 1 constituting the debugging device 100 according to the first embodiment will be described. The PLC 1 shown in FIG. 1 can be realized by the processor 201, the memory 202 and the communication interface 203 shown in FIG. The processor 201 may be a processing device, an arithmetic device, a microprocessor, a microcomputer, a central processing unit (CPU), a digital signal processor (DSP), or the like. The memory 202 is a nonvolatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), or EEPROM (Electrically EPROM), or a magnetic disk. , Flexible disks, optical disks, compact disks, mini disks, or DVDs (Digital Versatile Disc). The memory 202 may be a combination of two or more types of storage devices.

  The program memory 11 of the PLC 1 is realized by the memory 202. The program execution unit 12 of the PLC 1 is realized by the processor 201 and the memory 202. The operation verification result management unit 13 of the PLC 1 is realized by the processor 201 and the memory 202. That is, the operation verification status determination unit 14 is realized by the memory 202 holding a program for operating as the operation verification status determination unit 14 and the processor 201 reading out the program from the memory 202 and executing the program. The operation verification status storage unit 15 is realized by the memory 202. The communication interface 203 shown in FIG. 12 is used when communicating with the computer 2 that realizes the engineering tool 20. As described above, the engineering tool 20 is realized by the computer 2 executing a program for operating as the engineering tool 20.

  As described above, the debugging device 100 according to the present embodiment includes the program execution unit 12 for executing the sequence program, the instruction executed by the program execution unit 12, the execution type and the pre-condition of the executed instruction as device memory The operation verification status determination unit 14 based on the device value stored in 17 and the operation verification status storage unit 15 that stores the determination result by the operation verification status determination unit 14 as an operation verification status. This eliminates the need for the user to confirm the execution type of the executed instruction, thereby reducing the user's workload. Therefore, the work efficiency of debugging a sequence program can be improved. The operation verification status display unit 21 displays the progress status of the operation verification of the sequence program in a format that can be visually recognized by the user. As a result, the user can easily know the progress of the operation verification, and the debugging operation efficiency can be further improved.

  In the present embodiment, ON execution and OFF execution are used as execution types. However, the execution types are not limited to this, and any execution types of programs may be defined.

Second Embodiment
In the first embodiment, although the debugging apparatus having the configuration in which the PLC 1 includes the operation verification result management unit 13 has been described, the computer 2 including the engineering tool 20 may be configured to include the operation verification result management unit 13.

  FIG. 13 is a diagram of a configuration example of the debugging device according to the second embodiment. The debugging device 100a according to the second embodiment includes the PLC 1a, the operation verification result management unit 13 described in the first embodiment, and a computer 2a for realizing the engineering tool 20. The PLC 1 a is a PLC having a configuration in which the operation verification result management unit 13 is deleted from the PLC 1 described in the first embodiment. In addition to the engineering tool 20 described in the first embodiment, the computer 2 determines the instruction executed by the program execution unit 12 and the execution type described in the first embodiment, and stores the result thereof. A unit 13 is provided. The program memory 11 and the program execution unit 12 of the PLC 1a are the same as the program memory 11 and the program execution unit 12 of the PLC 1 described in the first embodiment, and therefore the description thereof is omitted. The engineering tool 20 and the operation verification result management unit 13 of the computer 2a are the same as the engineering tool 20 of the computer 2 and the operation verification result management unit 13 of the PLC 1 described in the first embodiment, and therefore the description thereof is omitted.

  Although the engineering tool 20 and the operation verification result management unit 13 are separately configured, the engineering tool 20 may be configured to include the operation verification result management unit 13.

  The configuration shown in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and one of the configurations is possible within the scope of the present invention. Parts can be omitted or changed.

  1, 1a PLC, 2, 2a computer, 3 network cable, 11 program memory, 12 program execution unit, 13 operation verification result management unit, 14 operation verification status determination unit, 15 operation verification status storage unit, 16 verification target sequence program, 17 device memory, 20 engineering tools, 21 operation verification status display unit, 22 operation verification setting input unit, 23 operation verification setting writing unit, 100, 100a debug device.

In order to solve the problems described above and achieve the object, the debugging device according to the present invention includes an execution unit that executes instructions included in a sequence program, an instruction executed by the execution unit, and an execution of the executed instructions. A determination unit that determines an execution type representing a relation between contents and an execution result of an instruction immediately before the executed instruction; Also, the debugging device executes the execution by the storage unit that stores the execution status of the instruction for each execution type determined by the determination unit, the execution type, and the identification information that identifies the executed instruction, and the execution unit And a display unit configured to display the executed instruction and the execution type of the executed instruction in a form that can be viewed according to whether the instruction is executed. The execution type includes ON execution to be executed when the execution result of the immediately preceding instruction is true and OFF execution to be executed when the execution result of the immediately preceding instruction is false.

Claims (6)

An execution unit that executes instructions included in the sequence program;
A determination unit that determines an instruction executed by the execution unit, and an execution type representing a relationship between an execution content of the executed instruction and an execution result of an instruction immediately before the executed instruction;
A storage unit that stores the execution status of an instruction for each execution type determined by the determination unit, the execution type, and identification information for identifying the executed instruction in association with each other;
A display unit that displays an instruction executed by the execution unit and an execution type of the executed instruction in a viewable format according to whether or not the instruction is executed;
A debugging apparatus comprising:   The debugging device according to claim 1, wherein the display unit displays the executed instruction and the execution type in contrast to the sequence program executed by the execution unit.   The debugging device according to claim 1 or 2, wherein the display unit displays a ratio of the instruction executed by the execution unit to all the instructions included in the sequence program. The determination unit is configured to be able to determine the instruction executed by the execution unit and the execution type of the executed instruction according to a plurality of operation verification settings, and performs the determination according to different operation verification settings. Generate a judgment result,
The debugging apparatus according to claim 1, wherein the display unit displays the plurality of determination results on one screen.   5. The debugging apparatus according to claim 4, wherein the display unit displays the determination result designated by the user among the plurality of determination results on one screen.   The execution type includes ON execution which is executed when the execution result of the immediately preceding instruction is true, and OFF execution which is executed when the execution result of the immediately preceding instruction is false. The debugging device according to any one of 5.

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