JPWO2018159437A1 - DC-DC converter - Google Patents

Abstract

It has a first full bridge circuit (10) and a second full bridge circuit (20) insulated by a transformer (T1). The first full bridge circuit (10) has switching elements (Q1 to Q8), a first floating capacitor (Cf1) and a second floating capacitor (Cf2). The first full bridge circuit (10) operates in at least one of a full bridge operation mode and a half bridge operation mode. Then, when switching the operation mode, the switching phase of the first full bridge circuit (10) is shifted in two times within one cycle of the driving frequency, and the output of the first full bridge circuit is output before and after the operation mode is switched. The amount of phase shift is determined so that the voltage is balanced in positive and negative.

Description

  The present invention relates to a DAB (Dual Active Bridge) type DC-DC converter.

  Patent Document 1 discloses a DAB converter. In the converter described in Patent Document 1, a full bridge circuit is connected to each of a primary winding and a secondary winding of a transformer, and power transmission is performed by appropriately controlling a switching phase difference between the two full bridge circuits. To do.

US Pat. No. 5,355,294

  In the converter described in Patent Document 1, switching loss is reduced by performing zero voltage switching (ZVS) by utilizing the leakage inductance of the transformer and the parasitic capacitance of the semiconductor device. However, the ZVS range is limited and the reactive current increases in proportion to the difference between the input / output voltage ratio and the transformer winding number ratio, which may lead to a decrease in efficiency. In particular, for example, when the input / output voltage ratio is large and the load connected to the output terminal is a light load, the reactive current that does not contribute to the transmission power increases and the efficiency may deteriorate.

  Further, in the DAB DC-DC converter, a DC component may be superimposed on the inductor current and the exciting current of the transformer due to a transient change in the supplied power (DC deviation). For example, the above DC deviation occurs when the transmission power changes abruptly or when the operation mode is switched. In order to prevent the inductor or the transformer from being magnetically saturated even if there is such a DC deviation, it is necessary to use an inductor or a transformer having a large magnetic core, that is, a large volume. This causes an increase in size and cost of the device.

  Therefore, an object of the present invention is to make it possible to realize a ZVS operation in a wide range even when the input / output voltage ratio is large and the load variation range is wide, and also to prevent a DC deviation caused by a transient change in the operating state. It is to provide a DC-DC converter that suppresses the above and eliminates the increase in size and cost of the device.

(1) The DC-DC converter of the present invention is
A first leg composed of a first high-side switch and a first low-side switch; and a second leg composed of a second high-side switch and a second low-side switch, wherein the first leg and the second A first full bridge circuit to which a first DC voltage is applied to the leg;
A third leg composed of a third high-side switch and a third low-side switch, and a fourth leg composed of a fourth high-side switch and a fourth low-side switch, and the third leg and the fourth A second full bridge circuit to which a second DC voltage is applied to the leg;
A first winding connected to an input / output unit of the first full bridge circuit and a secondary winding connected to an input / output unit of the second full bridge circuit; A transformer that insulates between the two full bridge circuits,
A control unit for controlling the first full bridge circuit and the second full bridge circuit;
Have.

The first high-side switch includes a first switching element connected to the high-side line and a second switching element connected in series to the first switching element,
The first low-side switch includes a fourth switching element connected to the low-side line and a third switching element connected in series to the fourth switching element,
The second high-side switch includes a fifth switching element connected to the high-side line and a sixth switching element connected in series with the fifth switching element,
The second low-side switch is composed of an eighth switching element connected to the low-side line and a seventh switching element connected in series with the eighth switching element.

  The first full bridge circuit is connected between a connection point of the first switching element and the second switching element and a connection point of the fifth switching element and the sixth switching element. A second floating capacitor connected between a floating capacitor, a connection point between the third switching element and the fourth switching element, and a connection point between the seventh switching element and the eighth switching element; Have.

  At least one of the input / output unit of the first full bridge circuit and the primary winding, or the input / output unit of the second full bridge circuit and the secondary winding is connected in series. Equipped with an inductor.

And the control unit
Operating each switching element of the first full bridge circuit and the second full bridge circuit at the same drive frequency, and
Each switching element of the first full bridge circuit is controlled so that the absolute value of the peak value of the voltage of the input / output unit of the first full bridge circuit becomes the first DC voltage over the half cycle of the driving frequency. Full bridge operating mode to control,
The switching elements of the first full bridge circuit are controlled so that the absolute value of the peak value of the voltage of the input / output unit of the first full bridge circuit becomes half of the first DC voltage over the half cycle. Half bridge operating mode, or
During a period of one cycle of the driving frequency, each switching element of the first full bridge circuit is switched between a full bridge operation state and a half bridge operation state to supply a voltage of five levels to the first full bridge circuit. 5 level operation mode output from
Control either.

Further, the control unit is
Of the full-bridge operation mode, the half-bridge operation mode, and the 5-level operation mode, the first high-level operation is performed at a reference cycle timing of the drive frequency in a cycle in which the operation mode is switched from one operation mode to another operation mode. The switching phases of the side switch and the second low side switch are shifted, and the switching phases of the first low side switch and the second high side switch are shifted at the half cycle timing of the reference cycle of the drive frequency, and the operation mode is The phase shift amount is determined so that the output voltage of the first full bridge circuit is positively and negatively balanced before and after the switching.

  According to the above configuration, the voltage output from the first full bridge circuit is different when the voltage input to the first full bridge circuit is applied to the first and second floating capacitors and when it is not applied. Can be made. That is, by operating the first full bridge circuit in the full bridge operation mode or the half bridge operation mode, even if the input / output voltage ratio is large and the variation range of the load connected to the output unit is wide, By expanding the ZVS range rather than the configuration of the technology, it is possible to suppress an increase in the reactive current that does not contribute to transmission and to operate the DC-DC converter efficiently.

  In addition, since the first leg and the second leg that form the first full bridge circuit are formed by connecting four switching elements in series, the voltage is applied to each element as compared with the case where two switching elements are connected in series. The voltage applied is low. Therefore, it is not necessary to increase the element breakdown voltage of each switching element. As a result, a MOS-FET having a low ON resistance value can be used for each switching element.

  In particular, the control unit can output a 5-level potential from the first full bridge circuit by switching between the full bridge operation mode and the half bridge operation mode during one cycle of the driving frequency of the first full bridge circuit. Provide a DC-DC converter that enables ZVS operation even in the light load region, has a large input / output voltage ratio, and has a wide variation range of the load connected to the output section, and can operate more efficiently can do.

  Moreover, since the output voltage of the first full bridge circuit is positively and negatively balanced before and after the switching of the operation mode, the DC deviation of the inductor current and the exciting current of the transformer is suppressed. As a result, the size and cost of the device can be reduced.

(2) The control unit is
U-phase carrier and U-phase inversion carrier that determine the switching phase of the first high-side switch or the first low-side switch, V-phase carrier and V-phase inversion that determine the switching phase of the second high-side switch or the second low-side switch The switching phase of each switching element of the first full-bridge circuit is determined based on the carrier, and the phases of the U-phase carrier and the V-phase inversion carrier are shifted at the reference cycle timing of the driving frequency to change the driving frequency. It is preferable to shift the phases of the U-phase inversion carrier and the V-phase carrier at the half cycle timing of the reference cycle.

  According to the above configuration, compared to a case where the phase difference between the first full bridge circuit and the second full bridge circuit is changed at once, it is possible to suppress the DC deviation when switching the operation mode.

(3) The U-phase carrier, the U-phase inversion carrier, the V-phase carrier, and the V-phase inversion carrier are count values of the reference clock, and the control unit is based on the comparison between the count value and the reference value. Controlling the first full bridge circuit and the second full bridge circuit,
The phase shift amount is preferably determined by changing the count value.

  With the above configuration, the configuration for controlling the phase shift and setting the phase shift amount can be simplified.

(4) The U-phase carrier, the U-phase inversion carrier, the V-phase carrier, and the V-phase inversion carrier are count values of the reference clock, and the control unit is based on the comparison between the count value and the reference value. Controlling the first full bridge circuit and the second full bridge circuit,
The shift amount of the phase may be determined by changing the reference value.

  With the above configuration, the configuration for controlling the phase shift and setting the phase shift amount can be simplified.

  According to the present invention, even when the input / output voltage ratio is large and the load variation connected to the output section is wide, the ZVS operation range can be expanded by switching the operation mode, and the operation mode can be switched. A direct current deviation that sometimes occurs is suppressed, and a compact and low-cost DC-DC converter can be obtained.

FIG. 1 is a circuit diagram of a DC-DC converter 1 according to this embodiment. FIG. 2 shows the relationship between the states of the eight switching elements of the full bridge circuit 10 and the voltages Vu, Vv, and V1, and the relative relationship between the charge / discharge states of the first floating capacitor Cf1 and the second floating capacitor Cf2 for each operation mode. It is a figure. 3 (A), (B), (C), and (D) are diagrams showing paths of current flowing through the full bridge circuit 10 in each state shown in FIG. 4 (A), (B), (C), and (D) are diagrams showing paths of currents flowing through the full bridge circuit 10 in the respective states shown in FIG. 5 (A), (B), (C), and (D) are diagrams showing paths of currents flowing through the full bridge circuit 10 in the respective states shown in FIG. 6 (A), (B), (C), and (D) are diagrams showing paths of currents flowing through the full bridge circuit 10 in the respective states shown in FIG. FIG. 7 is a diagram showing a combination of performing the full-bridge operation mode from the 16 states shown in FIG. FIG. 8 is a diagram showing a combination of performing the half-bridge operation mode from the 16 states shown in FIG. FIG. 9 is a diagram showing a part of combinations in which the 5-level operation mode is performed from the 16 states shown in FIG. FIG. 10 is a diagram showing a part of combinations in which the 5-level operation mode is performed from the 16 states shown in FIG. FIG. 11 is a diagram showing a part of combinations in which the 5-level operation mode is performed from the 16 states shown in FIG. FIG. 12 is a waveform diagram showing ON / OFF states of the switching elements Q1 to Q8 in the full-bridge operation mode, the half-bridge operation mode, and the 5-level operation mode. FIG. 13 is a waveform diagram of the voltages Vu, Vv, V1 and the current iL flowing through the inductor L1 at each position of the full bridge circuit 10. FIG. 14 is a diagram showing voltage waveforms of the voltages Vu, Vv, and V1 of the full bridge circuit 10 when α and β = 0. FIG. 15 is a diagram showing voltage waveforms of the voltages Vu, Vv, and V1 of the full bridge circuit 10 when α = π / 4 and β = π / 2. FIG. 16 is a diagram showing voltage waveforms of the voltages Vu, Vv, and V1 of the full bridge circuit 10 when α = β = π / 4. FIG. 17 is a diagram showing the relationship between the output power Pout of the DC-DC converter 1 and the input / output voltage ratio. FIG. 18A is a waveform diagram of each part when the operation mode is switched from the half bridge operation mode to the full bridge operation mode in the DC-DC converter of the present embodiment. FIG. 18B is a waveform diagram of each part when the operation mode is switched from the half bridge operation mode to the full bridge operation mode in the DC-DC converter of the comparative example. FIG. 19 is an enlarged view of the main waveform of FIG. FIG. 20A is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the half bridge operation mode in the DC-DC converter of the present embodiment. FIG. 20B is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the half bridge operation mode in the DC-DC converter of the comparative example. FIG. 21 is an enlarged view of the main waveform of FIG. 20 (A). FIG. 22A is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the 5-level operation mode in the DC-DC converter of the present embodiment. FIG. 22B is a waveform diagram of the comparative example. FIG. 23A is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the full-bridge operation mode in the DC-DC converter of this embodiment. FIG. 23B is a waveform diagram of the comparative example. FIG. 24A is a waveform diagram of each part when the operation mode is switched from the half-bridge operation mode to the 5-level operation mode in the DC-DC converter of the present embodiment. FIG. 24B is a waveform diagram of the comparative example. FIG. 25A is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the half-bridge operation mode in the DC-DC converter of the present embodiment. FIG. 25B is a waveform diagram of the comparative example. FIG. 26 is a diagram showing waveforms of respective parts before and after the phase shift when the transmission power changes in the DC-DC converter of the present embodiment. FIG. 27 is a waveform diagram showing changes and the like of each carrier and a reference value as a comparison target.

  The DC-DC converter described below is an isolated bidirectional DC-DC converter in which two full bridge circuits are insulated from each other by a transformer and electric power is bidirectionally transmitted between the two full bridge circuits.

  FIG. 1 is a circuit diagram of a DC-DC converter 1 according to this embodiment.

  The DC-DC converter 1 includes input / output terminals IO1, IO2, IO3, IO4. A load and a DC power supply are connected to the input / output terminals IO1, IO2, IO3, IO4. The DC-DC converter 1 is a bidirectional DC-DC converter that transforms a DC voltage input from one of the input / output terminals IO1 and IO2 or one of the input / output terminals IO3 and IO4 and outputs the voltage to the other.

  The input capacitor C1 and the full bridge circuit 10 are connected to the input / output terminals IO1 and IO2. The full bridge circuit 10 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a first series circuit (first leg) of a fourth switching element Q4, a fifth switching element Q5, and a sixth switching element. The element Q6, the seventh switching element Q7, and the second series circuit (second leg) of the eighth switching element Q8 are connected in parallel.

  The first switching element Q1 connected to the high side line and the second switching element Q2 connected in series to the first switching element Q1 constitute a first high side switch. Further, the fourth switching element Q4 connected to the low side line and the third switching element Q3 connected in series to the fourth switching element Q4 constitute a first low side switch. The fifth switching element Q5 connected to the high side line and the sixth switching element Q6 connected in series to the fifth switching element Q5 form a second high side switch. Furthermore, the 8th switching element Q8 connected to the low side line and the 7th switching element Q7 connected in series with this 8th switching element Q8 comprise the 2nd low side switch.

  The first to eighth switching elements Q1 to Q8 are n-type MOS-FETs, and body diodes and parasitic capacitances are formed. In addition, the gates of the first to eighth switching elements Q1 to Q8 are connected to the control unit 31, and a gate voltage is applied from the control unit 31 to perform switching control. In the following, the first to eighth switching elements Q1 to Q8 are simply referred to as switching elements Q1 to Q8.

  A conventional general full bridge circuit is configured by connecting in series a series circuit in which two switching elements are connected in series. On the other hand, in the present embodiment, each of the first series circuit and the second series circuit forming the full-bridge circuit 10 has four switching elements connected in series, and thus has a structure in which two switching elements are connected in series. The voltage applied to each element is lower than that of Therefore, it is not necessary to increase the element breakdown voltage of each switching element. Generally, since a switching element having a high breakdown voltage has a large on-resistance value, a MOS-FET having a low on-resistance value can be used for each switching element.

  The full bridge circuit 10 includes a first floating capacitor Cf1 and a second floating capacitor Cf2. The first floating capacitor Cf1 is connected between a connection point between the first switching element Q1 and the second switching element Q2 and a connection point between the third switching element Q3 and the fourth switching element Q4. The second floating capacitor Cf2 is connected between the connection point between the fifth switching element Q5 and the sixth switching element Q6 and the connection point between the fifth switching element Q5 and the sixth switching element Q6.

  The full bridge circuit 10 corresponds to the "first full bridge circuit" according to the present invention. The first floating capacitor corresponds to the "first floating capacitor" according to the present invention, and the second floating capacitor corresponds to the "second floating capacitor" according to the present invention.

  The input capacitor C2 and the full bridge circuit 20 are connected to the input / output terminals IO3 and IO4. The full bridge circuit 20 includes a series circuit (third leg) of the ninth switching element Q9 and the tenth switching element Q10 connected in series, and a series circuit of the eleventh switching element Q11 and the twelfth switching element Q12 connected in series ( And a fourth leg) are connected in parallel. These ninth to twelfth switching elements Q9 to Q12 are n-type MOS-FETs, and body diodes and parasitic capacitances are formed therein. Further, the ninth to twelfth switching elements Q9 to Q12 have gates connected to the control unit 32, and a gate signal is applied from the control unit 32 to perform switching control. The full bridge circuit 20 corresponds to the "second full bridge circuit" according to the present invention.

  Furthermore, the input / output terminals IO3 and IO4 are provided with an output voltage detection circuit 21 and a load current detection circuit 22.

  A transformer T1 is connected between the full bridge circuit 10 and the full bridge circuit 20. The transformer T1 has a primary winding n1 and a secondary winding n2. The primary winding n1 has one end connected to the connection point U between the second switching element Q2 and the third switching element Q3 via the inductor L1, and the other end connected to the sixth switching element Q6 and the seventh switching element Q7. Is connected to the connection point V. The secondary winding n2 has one end connected to a connection point W between the ninth switching element Q9 and the tenth switching element Q10, and the other end connected to a connection point X between the eleventh switching element Q11 and the twelfth switching element Q12. Has been done. In the present embodiment, the turn ratio between the primary winding n1 and the secondary winding n2 is N: 1.

  In the DC-DC converter 1 configured as described above, the control unit 31 uses the resonance between the parasitic capacitance of each of the switching elements Q1 to Q8 and the inductor (resonance coil) L1 to perform full-bridge circuit with zero voltage switching. Control 10 That is, during a dead time period when the switching element is switched on / off, a current flowing through the inductor L1 is caused to flow in the parasitic capacitance of the switching element, the parasitic capacitance is discharged, and the switching element is turned on at zero voltage. Thereby, switching loss, switching noise, etc. can be reduced. The inductor L1 may be provided on the secondary side of the transformer T1. Zero voltage switching may be performed by using the resonance between the leakage inductance of the transformer T1 and the parasitic capacitance of each of the switching elements Q1 to Q8 without using the inductor L1.

  The DC voltage Vin is applied to the input / output terminals IO1 and IO2 of the DC-DC converter 1 configured as described above. The control unit 31 controls switching of the switching elements Q1 to Q8 of the full bridge circuit 10. A five-level voltage V1 of 0, ± Vin / 2, and ± Vin is applied to the primary winding n1 of the transformer T1. When the voltage V1 is applied to the primary winding n1, a voltage is induced in the secondary winding n2. The control unit 32 controls the switching of the full bridge circuit 20, and outputs the DC voltage Vout of 0, Vin / 2N, Vin / N from the input / output terminals IO3, IO4. That is, the full bridge circuit 10 is a five-level circuit that outputs five voltage levels. The full bridge circuit 20 is a three-level circuit that outputs three voltage levels.

  Since the DC-DC converter 1 is a bidirectional DC-DC converter, when a DC voltage is input from the input / output terminals IO3, IO4, the full bridge circuits 10, 20 are switching-controlled to input / output. DC voltage is output from terminals IO1 and IO2.

  FIG. 2 shows the relationship between the states of the eight switching elements of the full bridge circuit 10 and the voltages Vu, Vv, and V1 and the relative relationship between the charge / discharge states of the first floating capacitor Cf1 and the second floating capacitor Cf2 for each operation mode. It is a figure. The voltage Vu is the voltage at the connection point U of the switching elements Q2 and Q3. The voltage Vv is the voltage at the connection point V of the switching elements Q6 and Q7. The voltage V1 is the output voltage from the full bridge circuit 10 applied to the primary winding n1 of the transformer T1, and is the potential difference between the connection point U and the connection point V. 3 (A) (B) (C) (D), FIG. 4 (A) (B) (C) (D), FIG. 5 (A) (B) (C) (D), FIG. 6 (A) (B) (C) (D) is a figure which shows the path | route of the electric current which flows into the full bridge circuit 10 in each state shown in FIG.

  The full bridge circuit 10 according to the present embodiment operates in any one of a full bridge operation mode, a half bridge operation mode, and a 5-level operation mode. The full-bridge operation mode is an operation mode in which the voltage V1 = ± Vin. In this full bridge operation mode, the current path does not pass through either the first floating capacitor or the second floating capacitor. The half-bridge operation mode is an operation mode in which the voltage V1 = ± Vin / 2. In this half-bridge operation mode, the current path passes through only one of the first floating capacitor and the second floating capacitor. The 5-level operation mode is an operation mode in which the voltage V1 = 0, ± Vin / 2, ± Vin is obtained by combining the full-bridge operation mode and the half-bridge operation mode.

(V1 = Vin)
When the switching elements Q1, Q2, Q7, Q8 are ON and the switching elements Q3, Q4, Q5, Q6 are OFF, current flows through the path shown in FIG. The output voltage V1 in this case is Vin. In this case, the voltage Vu = Vin, the voltage Vv = 0, and the voltage V1 = Vu−Vv = Vin.

(V1 = -Vin)
When the switching elements Q3, Q4, Q5, Q6 are ON and the switching elements Q1, Q2, Q7, Q8 are OFF, current flows through the path shown in FIG. 3 (B). In this case, the voltage having the opposite polarity to that in the case of FIG. 3A is applied to the primary winding n1 of the transformer T1, and the voltage Vu = 0, the voltage Vv = Vin, and the voltage V1 = Vu−Vv = −Vin. Is.

(V1 = 0)
When the switching elements Q1, Q3, Q6, Q8 are on and the switching elements Q2, Q4, Q5, Q7 are off, current flows through the path shown in FIG. 3 (C). In this case, the voltage Vu = Vin−Vc1. Here, Vc1 is the charging voltage of the first floating capacitor Cf1. If Vc1 = Vin / 2, then the voltage Vu = Vin / 2. Further, the voltage Vv = Vc2. Here, Vc2 is the charging voltage of the second floating capacitor Cf2. If Vc2 = Vin / 2, then the voltage Vu = Vin / 2. The voltage V1 = Vu−Vv = 0.

  Further, when the switching elements Q2, Q4, Q5, Q7 are ON and the switching elements Q1, Q3, Q6, Q8 are OFF, current flows through the path shown in FIG. 3 (D). In this case, the voltage Vu = Vin−Vc1 = Vin / 2, the voltage Vv = Vin−Vc2 = Vin / 2, and the voltage V1 = Vu−Vv = 0.

  In addition, when the switching elements Q2, Q4, Q6, Q8 are ON and the switching elements Q1, Q3, Q5, Q7 are OFF, current flows through the paths shown in FIGS. 4 (A) and 4 (B). . In this case as well, the voltage V1 = 0, but the direction of current flow is opposite between FIG. 4 (A) and FIG. 4 (B). This depends on the relative charge / discharge states of the first floating capacitor Cf1 and the second floating capacitor Cf2.

  Further, even when the switching elements Q1, Q2, Q5, Q6 are ON and the switching elements Q3, Q4, Q7, Q8 are OFF, as shown in FIG. 4 (C), the voltage V1 = 0 and the switching element Q3. , Q4, Q7, Q8 are ON and the switching elements Q1, Q2, Q5, Q6 are OFF, as shown in FIG. 4D, the voltage V1 = 0.

(V1 = Vin / 2)
When the switching elements Q1, Q3, Q7, Q8 are ON and the switching elements Q2, Q4, Q5, Q6 are OFF, current flows through the path shown in FIG. 5 (A). In this case, the voltage Vu = Vin−Vc1 = Vin / 2, the voltage Vv = 0, and the voltage V1 = Vu−Vv = Vin / 2. Further, when the switching elements Q2, Q4, Q7, Q8 are on and the switching elements Q1, Q3, Q5, Q6 are off, current flows through the path shown in FIG. 5 (B). In this case, the voltage Vu = Vc1 = Vin / 2, the voltage Vv = 0, and the voltage V1 = Vu−Vv = Vin / 2. The voltage Vu is the voltage Vc1 charged in the first floating capacitor Cf1 in the state of FIG.

  Further, when the switching elements Q1, Q2, Q6, Q8 are on and the switching elements Q3, Q4, Q5, Q7 are off, current flows through the path shown in FIG. 5 (C). Further, even when the switching elements Q1, Q2, Q5, Q7 are ON and the switching elements Q3, Q4, Q6, Q8 are OFF, the current flows through the path shown in FIG. 5D, and the voltage V1 = Vin / 2. Become. The voltage Vu in this case is the voltage Vc2 charged in the second floating capacitor Cf2 in the state of FIG. 5 (C).

(V1 = -Vin / 2)
When the switching elements Q3, Q4, Q5, Q7 are ON and the switching elements Q1, Q2, Q6, Q8 are OFF, current flows through the path shown in FIG. 6 (A). In this case, voltage Vu = 0, voltage Vv = Vin−Vc2 = Vin / 2, and voltage V1 = Vu−Vv = −Vin / 2. Further, when the switching elements Q3, Q4, Q6, Q8 are on and the switching elements Q1, Q2, Q5, Q7 are off, current flows through the path shown in FIG. 6 (B). In this case, the voltage Vu = 0, the voltage Vv = Vc2 = Vin / 2, and the voltage V1 = Vu−Vv = −Vin / 2. The voltage Vv is the voltage Vc2 charged in the second floating capacitor Cf2 in the state of FIG. 6 (A).

  Further, when the switching elements Q2, Q4, Q5, Q6 are ON and the switching elements Q1, Q3, Q7, Q8 are OFF, a current flows through the path shown in FIG. 6C, and the voltage V1 = −Vin / 2. Becomes Further, when the switching elements Q1, Q3, Q5, Q6 are ON and the switching elements Q2, Q4, Q7, Q8 are OFF, a current flows through the path shown in FIG. 6D, and the voltage V1 = −Vin / 2. Becomes In this case, the voltage Vv is the voltage Vc1 charged in the first floating capacitor Cf1 in the state of FIG. 6 (C).

  In this way, the full bridge circuit 10 operates in any of the full bridge operation mode, the half bridge operation mode, and the 5-level operation mode. In the 5-level operation mode, the output period of the five voltage levels is determined by the period in which the voltage Vu = Vin / 2 and the phase difference between the voltages Vu and Vv.

  When operating in the full-bridge operation mode, the voltage V1 makes a transition of V1 → −V1 → V1 → −V1 → ... Within one cycle of the driving frequency. FIG. 7 is an example of a combination satisfying the above-mentioned conditions from the 16 states shown in FIG. That is, the state (7) and the state (8) are alternately repeated.

  When operating in the half-bridge operation mode, the voltage V1 undergoes a transition of V1 / 2 → −V1 / 2 → V1 / 2 → −V1 / 2 → ... In one cycle of the driving frequency. FIG. 8 is an example of a combination satisfying the above-mentioned condition from the 16 states shown in FIG. That is, in the half-bridge operation mode, there are 12 combinations as shown in FIG. When operating in the 5-level operation mode, the voltage V1 transits from 0 → Vin / 2 → Vin → Vin / 2 → 0 → −Vin / 2 → −Vin → −Vin / 2 → 0 within one cycle of the driving frequency. Is done. Examples of combinations satisfying the above-mentioned conditions from the 16 states shown in FIG. 2 are shown in FIGS. 9, 10 and 11. FIGS. 9, 10 and 11 are diagrams showing transition patterns in the “one switching period” of the operation mode shown in FIG. 2 in the 5-level operation mode.

  FIG. 12 is a waveform diagram showing ON / OFF states of the switching elements Q1 to Q8 in the full-bridge operation mode, the half-bridge operation mode, and the 5-level operation mode.

  FIG. 13 is a waveform diagram of the voltages Vu, Vv, V1 and the current iL flowing through the inductor L1 at each position of the full bridge circuit 10. In FIG. 13, phase 0 corresponds to the reference carrier peak timing described later, and phase π corresponds to the reference carrier bottom timing described later.

  The α shown in FIG. 13 is a period in which the voltage Vu = Vin / 2 during one cycle. Further, β is the phase difference between the voltages Vu and Vv. The period in which the voltage V1 = 0 is 2α-β, the period in which the voltage V1 = Vin / 2 is 2β, and the period in which the voltage V1 = Vin is π-2α-β. The output period of each of the five levels of voltage is determined by the values of α and β.

  FIG. 13 also shows the switch timing of the switching elements Q9 to Q12 of the full bridge circuit 20. The controller 32 turns on / off the switching elements Q9, Q12 and the switching elements Q10, Q11 at a duty ratio of 50%. δ is a switching phase difference between the full bridge circuits 10 and 20. The transmission power of the DC-DC converter 1 is controlled by α, β, δ. In particular, even in the same operation mode, the on-duty ratio of the second full-bridge circuit 20 changes by changing δ, so the control unit 32 maintains the output voltage at the specified value by adjusting δ.

  When the full bridge circuit 10 is switching-controlled so that α and β = 0, the voltage V1 = ± Vin. FIG. 14 is a diagram showing voltage waveforms of the voltages Vu, Vv, and V1 of the full bridge circuit 10 when α and β = 0. As shown in FIG. 14, the full bridge circuit 10 operates in the full bridge operation mode.

  When the full bridge circuit 10 is switching-controlled so that α = π / 4 and β = π / 2, the voltage V1 = ± Vin / 2. FIG. 15 is a diagram showing voltage waveforms of the voltages Vu, Vv, and V1 of the full bridge circuit 10 when α = π / 4 and β = π / 2. As shown in FIG. 15, the full bridge circuit 10 operates in the half bridge operation mode.

  Further, when the full bridge circuit 10 is switching-controlled so that α = β = π / 4, the voltage V1 makes a stepwise transition between ± Vin and ± Vin / 2,0 as shown in FIG. It operates in the 5-level operation mode.

  Since the DC-DC converter 1 according to the present embodiment outputs three voltage levels, it is possible to operate the DC-DC converter 1 with high efficiency according to the load fluctuation of the load connected to the DC-DC converter 1. it can. In the case of a general insulation type two-level DC-DC converter, the ZVS range is limited by the input / output voltage ratio and the transformer winding number ratio. Therefore, when the input / output voltage ratio is large, when the light load is connected to the two-level DC-DC converter, the ZVS operation range may be exceeded, and the ZVS operation may not be possible. As a result, the reactive current that does not contribute to the transmission power increases, and the transmission efficiency of the DC-DC converter deteriorates. On the other hand, in the present embodiment, it is possible to operate the DC-DC converter 1 with high efficiency by determining the operation mode of the DC-DC converter 1 according to the load fluctuation. The method of determining the operation mode of the full bridge circuit 10 will be described below.

  FIG. 17 is a diagram showing the relationship between the output power Pout of the DC-DC converter 1 and the input / output voltage ratio. The input / output voltage ratio can be expressed by NVout / Vin. Note that N is the turn ratio (N: 1) between the primary winding n1 and the secondary winding n2 of the transformer T1. The area (1) is the control range of the full-bridge operation mode, the area (2) is the control range of the half-bridge operation mode, and the area (3) is the control range of the 5-level operation mode.

  For example, when NVout / Vin = 1.0, the operation mode of the DC-DC converter 1 is set to the full bridge operation mode. In the case of NVout / Vin <0.6, the operation mode of the DC-DC converter 1 is set to the half-bridge operation mode in the area excluding the above-mentioned area (3). In the region where NVout / Vin <1.0, which does not correspond to the above-mentioned regions (1) and (2), the operation mode of the DC-DC converter 1 is set to the 5-level operation mode.

  As described above, by setting the operation mode according to the input / output voltage ratio and the output power Pout, the ZVS operation can be performed in a wide load variation range, the reactive current can be suppressed, and the DC-DC converter 1 can be operated with high efficiency. be able to. Further, even in the region (3) where the zero voltage switching is impossible in the conventional two-level DC-DC converter, the zero voltage switching is possible in the present embodiment, and the zero voltage switching in a wide load variation range is possible. It will be possible.

  Note that, for example, in the half-bridge operation mode, switching elements Q1, Q3, Q7, Q8 and switching elements Q2, Q4, Q5, Q6 are turned on / off alternately, and switching elements Q1, Q2, Q6, Q8 are replaced. And switching control for alternately turning on and off the switching elements Q3, Q4, Q5, Q7 may be used. In this case, a current flows through the second floating capacitor Cf2, so that the voltage V1 = ± Vin / 2.

  Next, the phase shift control when switching the operation mode will be described.

  FIG. 18A is a waveform diagram of each part when the operation mode is switched from the half bridge operation mode to the full bridge operation mode in the DC-DC converter of the present embodiment. FIG. 18B is a waveform diagram of each part when the operation mode is switched from the half bridge operation mode to the full bridge operation mode in the DC-DC converter of the comparative example. FIG. 19 is an enlarged view of the main waveform of FIG.

  Further, FIG. 20A is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the half bridge operation mode in the DC-DC converter of the present embodiment. FIG. 20B is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the half bridge operation mode in the DC-DC converter of the comparative example. FIG. 21 is an enlarged view of the main waveform of FIG. 20 (A).

  18A, 18B, 19, and 20A, 20B, the voltage V2 is the input voltage of the second full bridge circuit 20. Further, in FIGS. 19 and 21, the peak timing of the reference carrier is the reference cycle timing of the drive frequency, and the bottom timing of the reference carrier is the half cycle timing of the reference cycle of the drive frequency.

  18 (A) (B), FIG. 19, FIG. 20 (A) (B), and FIG. 21, the U-phase carrier and the U-phase inverted carrier are the first high-side switches Q1 and Q2 or the first low-side switches Q3 and Q4. The V phase carrier and the V phase inversion carrier are values that determine the switching phases of the second high side switches Q5, Q6 and the second low side switches Q7, Q8. The W-phase carrier is a value that determines the switching phases of the third high-side switch Q9 and the fourth low-side switch Q12, and the X-phase carrier is a value that determines the switching phases of the third low-side switch Q10 and the fourth high-side switch Q11. is there.

  The DC-DC converter of the comparative example is configured to phase-shift the U-phase carrier, the U-phase inversion carrier, the V-phase inversion carrier, and the V-phase inversion carrier when switching the operation mode.

  In FIGS. 18 (A) (B) and 20 (A) (B), the U-phase carrier, the U-phase inversion carrier, the V-phase carrier, and the V-phase inversion carrier are count values of the reference clock. The values are represented as a triangular waveform. Also, the horizontal broken line shown superimposed on the triangular waveform is a reference value for comparison with these carriers.

  In the DC-DC converter 1 of this embodiment, as shown in FIGS. 19 and 21, the operation mode is switched at the peak timing of the reference carrier. Then, the U-phase carrier is phase-shifted at the peak timing of this reference carrier. The U-phase inverted carrier is phase-shifted at the bottom timing of the reference carrier.

  The phase shift of the capacitor is performed by adding or subtracting the count value of the reference clock by a value corresponding to the phase shift amount.

  In the example shown in FIG. 19, when switching from the half bridge operation mode (HB) to the full bridge operation mode (FB), the U-phase carrier is phase-shifted by γ / 2 in the delay direction, and the V-phase inversion carrier is γ. The phase is shifted in the forward direction by / 2. Further, the U-phase inverted carrier is phase-shifted by γ / 2 in the delay direction, and the V-phase carrier is phase-shifted by γ / 2 in the advance direction.

  In the example shown in FIG. 21, when switching from the full bridge operation mode (FB) to the half bridge operation mode (HB), the U-phase carrier is phase-shifted by γ / 2 in the forward direction, and the V-phase inversion carrier is γ. The phase is shifted by / 2 in the delay direction. Further, the U-phase inverted carrier is phase-shifted by γ / 2 in the advance direction, and the V-phase carrier is phase-shifted by γ / 2 in the delay direction.

  Here, γ is a new phase shift amount with respect to the switching phase difference between the U phase and the V phase, which is caused by switching the operation mode. In this way, each carrier is divided into two parts within one cycle of the drive frequency and the phase is shifted (every half cycle), so that the positive / negative voltage of the output voltage V1 of the first full bridge circuit 10 at the time of switching the operation mode is changed. The difference in time product becomes small. That is, the DC deviation at the time of switching the operation mode can be suppressed.

  As is clear from a comparison between the inductor current iL in FIG. 18A and the inductor current iL in FIG. 18B, ripples and DC deviation are suppressed. Similarly, the direct current deviation is suppressed, as is clear from a comparison between the inductor current iL in FIG. 20 (A) and the inductor current iL in FIG. 20 (B).

  Not only at the time of switching from the full bridge operation mode (FB) to the half bridge operation mode (HB) or at the time of switching from the half bridge operation mode (HB) to the full bridge operation mode (FB), as shown below, Similarly, when switching between other operation modes, the DC deviation can be suppressed.

  FIG. 22A is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the 5-level operation mode in the DC-DC converter of the present embodiment. FIG. 22B is a waveform diagram of each part when the operation mode is switched from the full bridge operation mode to the 5-level operation mode in the DC-DC converter of the comparative example.

  FIG. 23A is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the full-bridge operation mode in the DC-DC converter of this embodiment. FIG. 23B is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the full-bridge operation mode in the DC-DC converter of the comparative example.

  FIG. 24A is a waveform diagram of each part when the operation mode is switched from the half-bridge operation mode to the 5-level operation mode in the DC-DC converter of the present embodiment. FIG. 24B is a waveform diagram of each part when the operation mode is switched from the half-bridge operation mode to the 5-level operation mode in the DC-DC converter of the comparative example.

  FIG. 25A is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the half-bridge operation mode in the DC-DC converter of the present embodiment. FIG. 25B is a waveform diagram of each part when the operation mode is switched from the 5-level operation mode to the half bridge operation mode in the DC-DC converter of the comparative example.

  22 (A) (B), 23 (A) (B), 24 (A) (B), and 25 (A) (B), the voltage V2 is the input of the second full bridge circuit 20. Voltage.

  Next, the phase shift control when the transmission power changes without changing the operation mode will be described.

  FIG. 26 is a diagram showing waveforms of respective parts before and after the phase shift when the transmission power changes in the DC-DC converter of the present embodiment. As shown in this figure, the U-phase carrier, the V-phase inverted carrier, and the W-phase carrier are phase-shifted at the peak timing of the reference carrier, and the U-phase inverted carrier, the V-phase carrier, and the X-phase carrier are shifted at the bottom timing of the reference carrier. A phase shift of the phase carrier is performed.

  Next, an example of a phase shift method other than the method of shifting the carrier phase will be described.

  FIG. 27 is a waveform diagram showing changes and the like of each carrier and a reference value as a comparison target. Here, particularly, a portion for shifting the switching phase of the first high-side switches Q1 and Q2 and the first low-side switches Q3 and Q4 will be shown. In FIG. 27, the U-phase carrier is generated with reference to the reference carrier peak timing, and the U-phase inverted carrier is generated with reference to the reference carrier bottom timing. The U-phase carrier and the U-phase inverted carrier are count values of the reference clock, and these values are represented here as a triangular waveform. The rectangular-wave-shaped broken line superimposed and shown on these triangular-wave-shaped waveforms is a reference value for comparing the magnitude with these carriers.

  The same applies to the shift of the switching phase of the second high side switch (Q5, Q6) and the second low side switch (Q7, Q8).

  In this way, the switching phases of the first high-side switches Q1 and Q2 and the first low-side switches Q3 and Q4 may be shifted by changing the reference value in synchronization with the carrier cycle.

  The shift amount of the phase shift at the time of switching the operation mode and the shift amount of the phase shift at the time of changing the transmission power are determined so that the output voltage of the first full bridge circuit is positively and negatively balanced before and after the phase shift control. In other words, before and after the operation mode is switched, the energy stored in the inductor is phase-shifted so as to approach the same positive and negative amounts. Further, this also means that the phase of the current flowing through the inductor L1 shifts toward a decrease before and after the operation mode is switched.

  In the example described above, the full bridge circuit 10 of the DC-DC converter 1 is configured to operate in any one of the full bridge operation mode, the half bridge operation mode, and the 5-level operation mode. It may be configured to operate in the full bridge operation mode or the half bridge operation mode. Even in this case, since it is not necessary to provide two circuits, a full bridge circuit and a half bridge circuit, it is possible to suppress an increase in size.

  In the embodiment described above, the voltage applied across the first winding of the transformer in the full bridge operation mode is applied to the direct current voltage Vin, and across the first winding of the transformer in the half bridge operation mode. The voltage is half the direct current voltage (Vin / 2), but these may include some errors. For example, the DC voltages Vin and Vin / 2 also include the case where they fluctuate due to variations in the parasitic capacitance of the FET, manufacturing errors, and the like.

  In the example shown in FIG. 1, the inductor L1 is connected to the primary side of the transformer T1, but the inductor may be connected to the secondary side. In addition, inductors may be connected to both the primary side and the secondary side.

C1 ... Input capacitor C2 ... Input capacitor Cf1 ... First floating capacitor Cf2 ... Second floating capacitor IO1, IO2, IO3, IO4 ... Input / output terminal L1 ... Inductor n1 ... Primary winding n2 ... Secondary winding Q1-Q12 ... Switching elements Q1, Q2 ... First high side switch Q3, Q4 ... First low side switch Q5, Q6 ... Second high side switch Q7, Q8 ... Second low side switch Q9 ... Third high side switch Q10 ... Third low side switch Q11 ... Fourth high-side switch Q12 ... Fourth low-side switch T1 ... Transformer U ... Connection point V ... Connection point W ... Connection point X ... Connection point 1 ... DC-DC converter 10 ... First full bridge circuit 20 ... Second full bridge Circuit 21 ... Output voltage detection circuit 22 ... Load current detection circuits 31, 32 Control unit

Claims (4)

A first leg composed of a first high-side switch and a first low-side switch; and a second leg composed of a second high-side switch and a second low-side switch, wherein the first leg and the second A first full bridge circuit to which a first DC voltage is applied to the leg;
A third leg composed of a third high-side switch and a third low-side switch, and a fourth leg composed of a fourth high-side switch and a fourth low-side switch, and the third leg and the fourth A second full bridge circuit to which a second DC voltage is applied to the leg;
A first winding connected to an input / output unit of the first full bridge circuit and a secondary winding connected to an input / output unit of the second full bridge circuit; A transformer that insulates between the two full bridge circuits,
A control unit for controlling the first full bridge circuit and the second full bridge circuit;
A DC-DC converter having:
The first high-side switch includes a first switching element connected to the high-side line and a second switching element connected in series to the first switching element,
The first low-side switch includes a fourth switching element connected to the low-side line and a third switching element connected in series to the fourth switching element,
The second high-side switch includes a fifth switching element connected to the high-side line and a sixth switching element connected in series with the fifth switching element,
The second low-side switch includes an eighth switching element connected to the low-side line and a seventh switching element connected in series with the eighth switching element,
The first full bridge circuit is connected between a connection point between the first switching element and the second switching element and a connection point between the third switching element and the fourth switching element. A second floating capacitor connected between a floating capacitor, a connection point between the fifth switching element and the sixth switching element, and a connection point between the seventh switching element and the eighth switching element; Have
It was connected in series between at least one of the input / output unit of the first full bridge circuit and the primary winding, or between the input / output unit of the second full bridge circuit and the secondary winding. Equipped with an inductor,
The control unit is
Operating each switching element of the first full bridge circuit and the second full bridge circuit at the same drive frequency, and
Each switching element of the first full bridge circuit is controlled so that the absolute value of the peak value of the voltage of the input / output unit of the first full bridge circuit becomes the first DC voltage over the half cycle of the driving frequency. Full bridge operating mode to control,
The switching elements of the first full bridge circuit are controlled so that the absolute value of the peak value of the voltage of the input / output unit of the first full bridge circuit becomes half of the first DC voltage over the half cycle. Half bridge operating mode, or
During a period of one cycle of the driving frequency, each switching element of the first full bridge circuit is switched between a full bridge operation state and a half bridge operation state to supply a voltage of five levels to the first full bridge circuit. 5 level operation mode output from
Control any of
Of the full-bridge operation mode, the half-bridge operation mode, and the 5-level operation mode, the first high-level operation is performed at a reference cycle timing of the drive frequency in a cycle in which the operation mode is switched from one operation mode to another operation mode. The switching phases of the side switch and the second low side switch are shifted, and the switching phases of the first low side switch and the second high side switch are shifted at the half cycle timing of the reference cycle of the drive frequency, and the operation mode is The phase shift amount is determined so that the output voltage of the first full-bridge circuit is positively and negatively balanced before and after switching.
DC-DC converter. The control unit is
U-phase carrier and U-phase inversion carrier that determine the switching phase of the first high-side switch or the first low-side switch, V-phase carrier and V-phase inversion that determine the switching phase of the second high-side switch or the second low-side switch The switching phase of each switching element of the first full bridge circuit is determined based on the carrier,
The phases of the U-phase carrier and the V-phase inversion carrier are shifted at the reference cycle timing of the drive frequency, and the phases of the U-phase inversion carrier and the V-phase carrier are shifted at the half cycle timing of the reference cycle of the drive frequency. Let
The DC-DC converter according to claim 1. The U-phase carrier, the U-phase inversion carrier, the V-phase carrier and the V-phase inversion carrier are count values of the reference clock,
The control unit controls the first full bridge circuit and the second full bridge circuit based on a comparison between the count value and a reference value,
The DC-DC converter according to claim 2, wherein the shift amount of the phase is determined by changing the count value. The U-phase carrier, the U-phase inversion carrier, the V-phase carrier and the V-phase inversion carrier are count values of the reference clock,
The control unit controls the first full bridge circuit and the second full bridge circuit based on a comparison between the count value and a reference value,
The DC-DC converter according to claim 2, wherein the phase shift amount is determined by changing the reference value.

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