JPWO2018142840A1 - Substrate processing method, computer storage medium, and substrate processing system - Google Patents

Abstract

In the substrate processing method, a substrate temperature is measured over time in a plurality of heat treatment apparatuses that perform heat treatment, a difference in substrate temperature between the heat treatment apparatuses is calculated, a resist pattern is formed on the substrate, a resist pattern dimension is measured, Calculate the difference in resist pattern dimensions between the heat treatment apparatuses, calculate the reaction rate for converting the substrate temperature into the resist pattern dimension using the substrate temperature difference and the resist pattern dimension difference, and a function of time for the reaction rate In order to derive the reaction model, the reaction rate at the beginning and end of the heat treatment is zero, the reaction rate is continuous in the time direction, and the product sum of the substrate temperature difference and the reaction model is the resist pattern dimension. The evaluation function is determined so that the difference is close to the solution, the optimization problem for the reaction model is solved, the reaction model is determined, and the reaction model is determined. Setting processing conditions of the substrate processing using Le.

Description

(Cross-reference of related applications)
This application claims priority based on Japanese Patent Application No. 2017-016433 for which it applied to Japan on February 1, 2017, and uses the content here.

  The present invention relates to a substrate processing method, a computer storage medium, and a substrate processing system for performing a photolithography process on a substrate and forming a resist pattern on the substrate.

  For example, in a photolithography process in a semiconductor device manufacturing process, for example, a resist coating process is performed on a semiconductor wafer (hereinafter referred to as “wafer”) to form a resist film, and a predetermined pattern is exposed on the resist film. Wafer exposure process, post-exposure baking process (hereinafter referred to as “PEB process”) that is heated to promote the chemical reaction of the resist film after exposure, and development process that develops the exposed resist film. A predetermined resist pattern is formed thereon.

  Incidentally, in recent years, with further higher integration of semiconductor devices, there is a demand for finer resist patterns. During such miniaturization, the resist pattern determines the pattern shape of the underlying film to be processed, and it is necessary to form the resist pattern uniformly on the wafer surface with strict dimensions.

  Therefore, in Patent Document 1, a photolithography process using a chemically amplified resist is performed to form a resist pattern on a wafer, and a dimension such as a line width of the resist pattern is measured. For example, it has been proposed to correct the resist pattern dimensions by correcting the heating temperature of the PEB process. In such a case, the correction of the heating temperature is performed, for example, by correcting the temperature of the hot plate that places and heats the wafer. That is, the hot plate temperature in the stable state of the PEB process is adjusted using a correlation equation between the hot plate temperature and the pattern profile (Zernike coefficient which is a characteristic component).

  In addition, as a system for correcting the heating temperature of the PEB process as described above, that is, a system for correcting the processing conditions of the processing apparatus, conventionally, for example, the APC ( There is an Advanced Process Control (advanced process control) system.

  With respect to this APC system, Patent Document 2 proposes process management using an SPC (Statistical Process Control) method for selecting a management target and setting an abnormality determination definition. Specifically, for example, when an abnormality occurs in the quality characteristic (resist pattern dimension), the processing parameter (PEB processing heating temperature) of the processing apparatus is corrected using a predetermined definition formula.

  Further, Patent Document 3 proposes a method of optimizing a recipe indicating a wafer processing condition (a heating temperature of PEB processing) by performing wafer processing and inspection and repeating trial and check. Specifically, a plurality of candidate recipes are stored in the database unit, and each candidate recipe is sequentially used to process and inspect the wafer. Based on the inspection result, the best recipe is selected from the plurality of candidate recipes. Select. In such a case, the work load on the operator is reduced by automatically repeating the trial and check.

Japanese Unexamined Patent Publication No. 2007-31690 Japanese Unexamined Patent Publication No. 2012-43245 Japanese Unexamined Patent Publication No. 2010-67812

  In the method described in Patent Document 1, a variation component that can be canceled by PEB processing is obtained from the final finished pattern, and the hot plate temperature is manipulated by a necessary amount. For this reason, when a plurality of other processing apparatuses capable of parallel processing, such as a resist coating processing apparatus and a development processing apparatus, are mounted in a system that performs photolithography processing, there is a difference between the processing apparatuses. A series of transport paths for performing wafer processing including PEB processing is limited to one pass. As a result, it is expected that there will be a restriction on the transport route, and versatility will be an issue in setting an alternative path when replacing the PEB device. Furthermore, the method described in Patent Document 1 requires a step of preparing a correlation equation between the hot plate temperature and the pattern profile in advance, and the wafer processing becomes complicated.

  In the method described in Patent Document 2, there is no mention or suggestion of how to define and review the definition formula when the material (resist material) or the apparatus state changes. Furthermore, there is no mention of the trouble of reviewing these definition formulas.

  With the method described in Patent Document 3, the operator's workload is reduced, but it takes time to optimize the processing conditions because wafer processing using a plurality of candidate recipes, inspection of results, and review of candidate recipes are repeated. It takes.

  As described above, in the conventional method, there is room for improvement in order to form a resist pattern uniformly on the wafer surface while taking into consideration the machine difference between processing apparatuses that perform photolithography processing.

  The present invention has been made in view of such points, and an object thereof is to uniformly form a resist pattern on a substrate within the substrate surface.

  In order to achieve the above object, one embodiment of the present invention is a substrate processing method for performing a photolithography process on a substrate and forming a resist pattern on the substrate, and a plurality of heat treatment apparatuses for performing a heat treatment in the photolithography process The substrate temperature is measured over time, and a temperature difference calculating step for calculating a difference in substrate temperature between the heat treatment apparatuses and a photolithography process including heat treatment using the plurality of heat treatment apparatuses are performed on the substrate. After forming the resist pattern, measure the resist pattern dimension, calculate the difference in resist pattern dimension between heat treatment apparatuses, and use the difference in the substrate temperature and the difference in the resist pattern dimension to determine the substrate temperature. Calculate the reaction rate for conversion to resist pattern dimensions and a function of time for the reaction rate It has a model derivation step of deriving a certain reaction model, and a condition setting step of setting the processing conditions of the substrate processing using the reaction model. In the model derivation step, the reaction rate at the start and end of the heat treatment is zero, the reaction rate is continuous in the time direction, and the product sum of the substrate temperature and the reaction model is the resist pattern dimension. An evaluation function is determined so as to be close to the difference between the above, the optimization problem is solved for the reaction model, and the reaction model is determined.

  According to one aspect of the present invention, the measurement of the substrate temperature in the temperature difference calculating step and the measurement of the resist pattern dimension in the dimensional difference calculating step are, for example, setup and maintenance of a processing apparatus that performs photolithography processing, or input of a chemical solution such as a resist solution It can be collected when adjusting later processing conditions. That is, normal inspection data can be used for the substrate temperature and resist pattern dimensions. In the model deriving step, it is possible to automatically model a function of time with respect to the reaction rate, that is, a pattern latent image forming process every moment in the heat treatment step, using the temperature difference and the dimensional difference. As described above, in order to derive the reaction model in one embodiment of the present invention, irregular operations different from normal operations such as special data collection and correlation formulation are almost unnecessary.

  When the reaction model is derived in this way, the substrate processing conditions can be set using the reaction model in the condition setting step. Although details of this processing condition will be described later, for example, a heat treatment recipe (hot plate temperature) applied to each heat treatment apparatus can be automatically adjusted. In addition, when combining such heat treatment with processing performed by a processing apparatus other than the heat processing apparatus, such as a resist coating processing apparatus or a development processing apparatus, a substrate processing path is selected so that a good resist pattern dimension can be obtained. It can be carried out. As a result, the resist pattern can be uniformly formed on the substrate surface on the substrate while reducing machine differences between the processing apparatuses. In addition, since it is not necessary to take the time required for the derivation of the reaction model as in the prior art described above, the throughput of the substrate processing can be improved and the productivity can be improved.

  According to another aspect of the present invention, there is provided a readable computer storage medium storing a program that operates on a computer of a control unit that controls the substrate processing system so that the substrate processing method is executed by the substrate processing system. It is.

  Another embodiment of the present invention according to another aspect is a substrate processing system that performs a photolithography process on a substrate and forms a resist pattern on the substrate, and includes a plurality of heat treatment apparatuses that perform heat treatment on the substrate, A dimension measuring device for measuring a resist pattern dimension, and a control unit for setting processing conditions for substrate processing, wherein the control unit measures the substrate temperature over time in the plurality of heat treatment apparatuses, A temperature difference calculating step for calculating a difference in substrate temperature in the substrate, and performing a photolithography process on the substrate using the plurality of heat treatment apparatuses, forming a resist pattern on the substrate, and then measuring a resist pattern dimension in the dimension measuring apparatus A dimensional difference calculating step for calculating a difference in resist pattern dimension between heat treatment apparatuses, a difference in the substrate temperature, and the resist pattern. A model deriving step for calculating a reaction rate for converting the substrate temperature into a resist pattern size using a difference in the process size, and deriving a reaction model that is a function of time for the reaction rate; and And a condition setting step for setting processing conditions for substrate processing. In the model derivation step, the reaction rate at the start and end of the heat treatment is zero, the reaction rate is continuous in the time direction, and the product sum of the substrate temperature and the reaction model is the resist pattern dimension. An evaluation function is determined so as to be close to the difference between the above, the optimization problem is solved for the reaction model, and the reaction model is determined.

  According to one embodiment of the present invention, a resist pattern can be uniformly formed on a substrate surface on a substrate while reducing machine differences between processing apparatuses. In addition, the throughput of substrate processing can be improved and productivity can be improved.

It is a top view showing typically the outline of the composition of the substrate processing system concerning this embodiment. It is a front view showing an outline of composition of a substrate processing system concerning this embodiment typically. It is a rear view which shows typically the outline of the structure of the substrate processing system concerning this embodiment. It is a longitudinal cross-sectional view which shows the outline of a structure of the heat processing apparatus typically. It is a top view which shows the outline of a structure of the heat processing apparatus typically. It is explanatory drawing which shows arrangement | positioning (arrangement | positioning of the measurement point of a wafer) of the temperature sensor provided in a hot platen. It is the graph which showed the time-dependent change of the wafer temperature in a PEB process for every measurement point. It is explanatory drawing which shows a mode that the resist pattern dimension in the position corresponding to the measurement point of a wafer is extracted. It is explanatory drawing which shows the relationship between wafer temperature and a resist pattern dimension. It is explanatory drawing which shows the wafer temperature difference between PEB apparatuses, and a resist pattern dimension difference. It is explanatory drawing which shows a reaction model. It is explanatory drawing which shows a mode that PEB processing time is shortened in the 1st usage method of a reaction model. It is explanatory drawing which shows a mode that a PEB component is calculated in the 2nd utilization method of a reaction model. It is explanatory drawing which shows the correlation with the operation amount of a hot plate temperature, and the variation | change_quantity of wafer temperature in the 2nd utilization method of a reaction model. It is explanatory drawing which shows the relationship between a wafer temperature and a resist pattern dimension in the 3rd usage method of a reaction model. It is explanatory drawing which shows a mode that a PEB component and another process component are calculated in the 3rd usage method of a reaction model. It is explanatory drawing which shows a mode that a resist pattern dimension is estimated in the 3rd usage method of a reaction model. It is explanatory drawing which shows a mode that the resist pattern dimension was estimated in the 3rd usage method of the reaction model. In an Example, it is explanatory drawing which shows a reaction model. In an Example, it is explanatory drawing which shows a mode that the in-plane average PEB component of a 1st PEB apparatus is calculated. In an Example, it is explanatory drawing which shows a mode that the in-plane average PEB component of a 2nd PEB apparatus is calculated. In an Example, it is explanatory drawing which shows a mode that the hotplate temperature in a 1st PEB apparatus is updated from the difference of the in-plane average PEB component between PEB apparatuses. In an Example, it is explanatory drawing which shows the correlation with the operation amount of hot plate temperature, and the variation | change_quantity of wafer temperature.

  Hereinafter, embodiments of the present invention will be described. In the present specification and drawings, elements having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

<Substrate processing system>
First, the configuration of the substrate processing system according to the present embodiment will be described. FIG. 1 is a plan view schematically showing the outline of the configuration of the substrate processing system 1. 2 and 3 are a front view and a rear view, respectively, schematically showing the outline of the internal configuration of the substrate processing system 1. In the present embodiment, a case where the substrate processing system 1 is a coating and developing processing system that performs photolithography processing on a wafer W as a substrate will be described as an example.

  As shown in FIG. 1, the substrate processing system 1 includes a cassette station 10 in which a cassette C containing a plurality of wafers W is loaded and unloaded, and a processing station 11 having a plurality of various processing apparatuses for performing predetermined processing on the wafers W. And an interface station 13 that transfers the wafer W to and from the exposure apparatus 12 adjacent to the processing station 11 is integrally connected.

  The cassette station 10 is provided with a cassette mounting table 20. The cassette mounting table 20 is provided with a plurality of cassette mounting plates 21 on which the cassette C is mounted when the cassette C is carried into and out of the substrate processing system 1.

  As shown in FIG. 1, the cassette station 10 is provided with a wafer transfer device 23 that is movable on a transfer path 22 that extends in the X direction. The wafer transfer device 23 is also movable in the vertical direction and the vertical axis direction (θ direction), and includes a cassette C on each cassette mounting plate 21 and a delivery device for a third block G3 of the processing station 11 described later. The wafer W can be transferred between the two.

  The processing station 11 is provided with a plurality of, for example, four blocks including various devices, that is, a first block G1 to a fourth block G4. For example, the first block G1 is provided on the front side of the processing station 11 (X direction negative direction side in FIG. 1), and on the back side of the processing station 11 (X direction positive direction side in FIG. 1, upper side in the drawing). Is provided with a second block G2. Further, the third block G3 described above is provided on the cassette station 10 side (the Y direction negative direction side in FIG. 1) of the processing station 11, and the interface station 13 side (the Y direction positive side in FIG. 1) of the processing station 11 is provided. On the direction side), a fourth block G4 is provided.

  For example, in the first block G1, as shown in FIG. 2, a plurality of liquid processing apparatuses, for example, a development processing apparatus 30 for developing the wafer W, an antireflection film (hereinafter referred to as “lower reflection” below the resist film of the wafer W). A lower anti-reflection film forming apparatus 31 for forming an anti-reflection film), a resist coating apparatus 32 for applying a resist solution to the wafer W to form a resist film, and an anti-reflection film (hereinafter referred to as an anti-reflection film) on the resist film of the wafer W. An upper antireflection film forming apparatus 33 for forming “an upper antireflection film”) is arranged in this order from the bottom.

  For example, three development processing devices 30, a lower antireflection film forming device 31, a resist coating device 32, and an upper antireflection film forming device 33 are arranged in a horizontal direction. The number and arrangement of the development processing device 30, the lower antireflection film forming device 31, the resist coating device 32, and the upper antireflection film forming device 33 can be arbitrarily selected.

  In the development processing device 30, the lower antireflection film forming device 31, the resist coating device 32, and the upper antireflection film forming device 33, for example, spin coating for applying a predetermined processing solution onto the wafer W is performed. In spin coating, for example, the processing liquid is discharged onto the wafer W from an application nozzle, and the wafer W is rotated to diffuse the processing liquid to the surface of the wafer W.

  For example, as shown in FIG. 3, the second block G2 is subjected to a heat treatment apparatus 40 to 43 for performing a heat treatment such as heating or cooling of the wafer W, or a hydrophobic treatment for improving the fixability between the resist solution and the wafer W. A hydrophobic processing device 44 and a peripheral exposure device 45 for exposing the outer peripheral portion of the wafer W are provided side by side in the vertical direction and the horizontal direction. The number and arrangement of the heat treatment apparatuses 40 to 43, the hydrophobic treatment apparatus 44, and the peripheral exposure apparatus 45 can be arbitrarily selected.

  In the heat treatment apparatuses 40 to 43, the heat treatment apparatus 40 performs a pre-baking process (hereinafter referred to as “PAB process”) in which the wafer W after the resist coating process is heated, and may be referred to as a PAB apparatus 40 hereinafter. The heat treatment apparatus 41 performs a post-exposure baking process (hereinafter referred to as “PEB process”) that heat-treats the wafer W after the exposure process, and may be referred to as a PEB apparatus 41 hereinafter. The heat treatment apparatus 42 performs a post-baking process (hereinafter referred to as “POST process”) in which the wafer W after the development process is heated, and may be referred to as a POST apparatus 42 hereinafter. The heat treatment apparatus 43 is an apparatus that performs other heat treatment. In addition, the structure of these heat processing apparatuses 40-43 is mentioned later.

  For example, in the third block G3, a plurality of delivery devices 50, 51, 52, 53, 54, 55, and 56 are provided in order from the bottom. The fourth block G4 is provided with a plurality of delivery devices 60, 61, 62 in order from the bottom.

  As shown in FIG. 1, a wafer transfer region D is formed in a region surrounded by the first block G1 to the fourth block G4. In the wafer transfer region D, for example, a plurality of wafer transfer devices 70 having transfer arms 70a that are movable in the Y direction, the X direction, the θ direction, and the vertical direction are arranged. The wafer transfer device 70 moves in the wafer transfer area D and transfers the wafer W to a predetermined device in the surrounding first block G1, second block G2, third block G3, and fourth block G4. it can.

  In addition, as shown in FIG. 3, a shuttle transfer device 80 is provided in the wafer transfer region D to transfer the wafer W linearly between the third block G3 and the fourth block G4.

  The shuttle conveyance device 80 is linearly movable in the Y direction of FIG. 3, for example. The shuttle transfer device 80 moves in the Y direction while supporting the wafer W, and can transfer the wafer W between the transfer device 52 of the third block G3 and the transfer device 62 of the fourth block G4.

  As shown in FIG. 1, a wafer transfer device 90 is provided next to the third block G3 on the positive side in the X direction. The wafer transfer device 90 includes a transfer arm 90a that can move in the X direction, the θ direction, and the vertical direction, for example. The wafer transfer device 90 moves up and down while supporting the wafer W, and can transfer the wafer W to each delivery device in the third block G3.

  The interface station 13 is provided with a wafer transfer device 100 and a delivery device 101. The wafer transfer apparatus 100 includes a transfer arm 100a that is movable in the Y direction, the θ direction, and the vertical direction, for example. For example, the wafer transfer apparatus 100 can support the wafer W on the transfer arm 100a and transfer the wafer W between the transfer apparatuses, the transfer apparatus 101, and the exposure apparatus 12 in the fourth block G4.

  The substrate processing system 1 is provided with a control unit 200 as shown in FIG. The control unit 200 is a computer, for example, and has a program storage unit (not shown). The program storage unit stores a program for controlling the processing of the wafer W in the substrate processing system 1. The program is recorded on a computer-readable storage medium such as a computer-readable hard disk (HD), a flexible disk (FD), a compact disk (CD), a magnetic optical desk (MO), or a memory card. Or installed in the control unit 200 from the storage medium.

  In addition, a dimension measuring device 210 that measures the dimension of a resist pattern formed on the wafer W in the substrate processing system 1 is provided outside the substrate processing system 1. The dimension measuring apparatus 210 measures a resist pattern dimension using, for example, a scatterometry method. Specifically, for example, the wafer W is irradiated with light from an oblique direction, and the light reflected by the wafer W is detected. The light intensity distribution in the wafer surface obtained from the detected light is collated with a virtual light intensity distribution stored in advance, and a resist pattern dimension corresponding to the collated virtual light intensity distribution is obtained. In the present embodiment, for example, the line width of the resist pattern is measured as the resist pattern dimension.

  Note that the dimension measuring apparatus 210 may be provided inside the substrate processing system 1. In such a case, the dimension measuring apparatus 210 is disposed at an arbitrary position inside the substrate processing system 1. For example, an inspection station (not shown) may be provided between the cassette station 10 and the processing station 11, and the dimension measuring device 210 may be disposed in this inspection station.

  Next, wafer processing performed using the substrate processing system 1 configured as described above will be described.

  First, a cassette C storing a plurality of wafers W is loaded into the cassette station 10 of the substrate processing system 1 and placed on the cassette placement plate 21. Thereafter, the wafers W in the cassette C are sequentially taken out by the wafer transfer device 23 and transferred to the transfer device 53 of the third block G3 of the processing station 11.

  Next, the wafer W is transferred to the heat treatment apparatus 40 of the second block G2 by the wafer transfer apparatus 70 and subjected to temperature adjustment processing. Thereafter, the wafer W is transferred to, for example, the lower antireflection film forming device 31 of the first block G1 by the wafer transfer device 70, and a lower antireflection film is formed on the wafer W. Thereafter, the wafer W is transferred to the heat treatment apparatus 40 of the second block G2, and heat treatment is performed. Thereafter, the wafer W is returned to the delivery device 53 of the third block G3.

  Next, the wafer W is transferred by the wafer transfer device 90 to the delivery device 54 of the same third block G3. Thereafter, the wafer W is transferred by the wafer transfer apparatus 70 to the hydrophobizing apparatus 44 of the second block G2, and subjected to the hydrophobizing process.

  Next, the wafer W is transferred to the resist coating device 32 by the wafer transfer device 70, and a resist solution is applied onto the wafer W to form a resist film. Thereafter, the wafer W is transferred to the PAB apparatus 40 by the wafer transfer apparatus 70 and subjected to PAB processing. Thereafter, the wafer W is transferred by the wafer transfer device 70 to the transfer device 55 of the third block G3.

  Next, the wafer W is transferred to the upper antireflection film forming apparatus 33 by the wafer transfer apparatus 70, and an upper antireflection film is formed on the wafer W. Thereafter, the wafer W is transferred to the heat treatment apparatus 43 by the wafer transfer apparatus 70, heated, and the temperature is adjusted. Thereafter, the wafer W is transferred to the peripheral exposure device 45 and subjected to peripheral exposure processing.

  Thereafter, the wafer W is transferred by the wafer transfer device 70 to the delivery device 56 of the third block G3.

  Next, the wafer W is transferred to the transfer device 52 by the wafer transfer device 90 and transferred to the transfer device 62 of the fourth block G4 by the shuttle transfer device 80. Thereafter, the wafer W is transferred to the exposure apparatus 12 by the wafer transfer apparatus 100 of the interface station 13 and subjected to exposure processing in a predetermined pattern.

  Next, the wafer W is transferred by the wafer transfer apparatus 100 to the delivery apparatus 60 of the fourth block G4. Thereafter, the wafer W is transferred to the PEB apparatus 41 by the wafer transfer apparatus 70 and subjected to PEB processing.

  Next, the wafer W is transferred to the development processing apparatus 30 by the wafer transfer apparatus 70 and developed. After the development is completed, the wafer W is transferred to the POST apparatus 42 by the wafer transfer apparatus 90 and subjected to the POST process.

  Thereafter, the wafer W is transferred to the transfer device 50 of the third block G3 by the wafer transfer device 70, and then transferred to the cassette C of the predetermined cassette mounting plate 21 by the wafer transfer device 23 of the cassette station 10. Thus, a series of photolithography steps is completed.

<Heat treatment equipment>
Next, the configuration of the PEB apparatus 41, which is a heat treatment apparatus, will be described. The configurations of the PAB apparatus 40, the POST apparatus 42, and the heat treatment apparatus 43, which are other heat treatment apparatuses, are the same as those of the PEB apparatus 41. FIG. 4 is a longitudinal sectional view schematically showing an outline of the configuration of the PEB device 41. FIG. 5 is a plan view schematically showing the outline of the configuration of the PEB apparatus 41.

  The PEB apparatus 41 has a processing container 300 that can be closed inside. A loading / unloading port (not shown) for the wafer W is formed on the side surface of the processing container 300 on the wafer transfer region D side, and an opening / closing shutter (not shown) is provided at the loading / unloading port.

  Inside the processing container 300, a heating unit 310 that heat-processes the wafer W and a cooling unit 311 that cools the wafer W and adjusts the temperature are provided. The heating unit 310 and the cooling unit 311 are arranged side by side in the Y direction.

  The heating unit 310 includes a cover 320 that can be moved up and down on the upper side, and a hot plate storage unit 321 that forms a processing chamber R integrally with the cover 320 on the lower side.

  The lid 320 has a substantially cylindrical shape with an open bottom surface. An exhaust part 320 a is provided at the center of the upper surface of the lid 320. The atmosphere in the processing chamber R is uniformly exhausted from the exhaust unit 320a.

  The hot plate accommodating portion 321 includes an annular holding member 331 that accommodates the hot plate 330 and holds the outer peripheral portion of the hot plate 330, and a substantially cylindrical support ring 332 that surrounds the outer periphery of the holding member 331. The hot plate 330 has a thick and substantially disk shape, and can place and heat the wafer W thereon. In addition, the heating plate 330 incorporates a heater 333 that generates heat by power supply, for example. The heating temperature of the hot plate 330 is controlled by the control unit 200, for example, and the wafer W placed on the hot plate 330 is heated to a predetermined temperature.

  As shown in FIG. 6, the hot plate 330 is provided with temperature sensors 334 to 338 that measure the temperature of the wafer W placed on the hot plate 330. The temperature sensor 334 is arranged at the center of the hot plate 330, and the temperature sensors 335 to 338 are arranged on the concentric circle of the hot plate 330 at equal intervals (90 degree intervals). And the temperature sensor 334 measures the temperature of the measurement point k1 in the center part of the wafer W, and the temperature sensors 335 to 338 measure the temperature of the measurement points k2 to k5 in the outer peripheral part of the wafer W, respectively. In addition, arrangement | positioning and the number of the temperature sensors (measurement point of the wafer W) of the hot plate 330 are not limited to this embodiment, and can be set arbitrarily.

  As shown in FIGS. 4 and 5, for example, three elevating pins 340 for supporting the wafer W from below and elevating it are provided below the hot plate 330. The elevating pin 340 can be moved up and down by the elevating drive unit 341. Near the central portion of the hot plate 330, through holes 342 that penetrate the hot plate 330 in the thickness direction are formed, for example, at three locations. The elevating pins 340 are inserted through the through holes 342 and can protrude from the upper surface of the heat plate 330.

  The cooling unit 311 has a cooling plate 350. The cooling plate 350 has a substantially square flat plate shape, and the end surface on the heat plate 330 side is curved in an arc shape. In the cooling plate 350, two slits 351 are formed along the Y direction. The slit 351 is formed from the end surface of the cooling plate 350 on the hot plate 330 side to the vicinity of the central portion of the cooling plate 350. The slit 351 can prevent the cooling plate 350 from interfering with the lifting pins 340 of the heating unit 310 and the lifting pins 360 of the cooling unit 311 described later. The cooling plate 350 includes a cooling member (not shown) such as cooling water or a Peltier element. The cooling temperature of the cooling plate 350 is controlled by the control unit 200, for example, and the wafer W placed on the cooling plate 350 is cooled to a predetermined temperature.

  The cooling plate 350 is supported by the support arm 352. A drive unit 353 is attached to the support arm 352. The drive unit 353 is attached to a rail 354 extending in the Y direction. The rail 354 extends from the cooling unit 311 to the heating unit 310. With this driving unit 353, the cooling plate 350 can move between the heating unit 310 and the cooling unit 311 along the rail 354.

  Below the cooling plate 350, for example, three elevating pins 360 for supporting the wafer W from below and elevating it are provided. The elevating pin 360 can be moved up and down by an elevating drive unit 361. The elevating pins 360 are inserted through the slits 351 and can protrude from the upper surface of the cooling plate 350.

  Next, a PEB process performed using the PEB apparatus 41 configured as described above will be described.

  First, when the wafer W is loaded into the PEB device 41 by the wafer transfer device 70, the wafer W is transferred from the wafer transfer device 70 to the lift pins 360 that have been lifted and waited in advance. Subsequently, the lift pins 360 are lowered, and the wafer W is placed on the cooling plate 350.

  Next, the driving unit 353 moves the cooling plate 350 along the rails 354 to the upper side of the hot plate 330, and the wafer W is transferred to the lifting pins 340 that have been lifted and waited in advance. Thereafter, after the lid 320 is closed, the elevating pins 340 are lowered and the wafer W is placed on the hot plate 330. Then, the wafer W on the hot plate 330 is heated to a predetermined temperature.

  Next, after the lid 320 is opened, the elevating pins 340 are raised and the cooling plate 350 is moved above the hot plate 330. Subsequently, the wafer W is transferred from the lift pins 340 to the cooling plate 350, and the cooling plate 350 moves to the loading / unloading side. During the movement of the cooling plate 350, the wafer W is cooled to a predetermined temperature.

<Reaction model of PEB device>
The present inventor has high operational sensitivity with respect to the chemically amplified resist in order to form a resist pattern uniformly on the wafer W on the wafer W while reducing machine differences between the processing apparatuses in the substrate processing system 1. Focusing on the PEB treatment, modeling was performed to clarify the reaction mechanism of the PEB treatment. Specifically, in PEB processing, the correlation between the wafer temperature and the resist pattern dimension that changes over time was modeled.

  According to this reaction model, the progress of the reaction during the PEB process can be estimated, and information obtained from the reaction model can be fed back to the wafer process. Further, by using this reaction model, it is possible to separate the influence of PEB processing and other processes (resist coating processing, PAB processing, exposure processing, development processing, etc.) on the resist pattern dimensions. Then, it becomes possible to optimize wafer processing.

  Hereinafter, a reaction model and a method of using the reaction model (first usage method to third usage method) will be described. First, a method for deriving a reaction model will be described. The reaction model uses a wafer temperature in PEB processing and a resist pattern dimension obtained by performing photolithography processing.

  The PEB process requires highly accurate temperature control in a photolithography process using a chemically amplified resist. For this reason, as shown in FIG. 6, the PEB apparatus 41 is provided with temperature sensors 334 to 338 that measure the temperature of the wafer W placed on the hot platen 330. During the setup and maintenance of the PEB apparatus 41, the temperature of the measurement points k1 to k5 of the wafer W is measured using these temperature sensors 334 to 338, and the temperature profile of the hot plate 330 is adjusted. Further, the substrate processing system 1 is provided with a plurality of PEB apparatuses 41, and the wafer temperature is acquired for each PEB apparatus 41.

  FIG. 7 is a graph showing the change over time of the wafer temperature in the PEB process acquired as described above for each of the measurement points k1 to k5. The horizontal axis in FIG. 7 indicates time t, and the horizontal axis indicates the wafer temperature θ [k, t]. k is the number of the measurement point of the wafer W. Normally, the hot plate temperature profile is adjusted so that the wafer temperature θ [k, t] shown in FIG. 7 falls within a preset allowable range. The wafer temperature θ [k, t] acquired at this time is recorded in association with each PEB apparatus 41 in which the hot plate temperature profile is adjusted. The wafer temperature θ [k, t] for each PEB apparatus 41 is used for deriving the reaction model.

  Further, as described above, when the hot plate temperature profile in the PEB apparatus 41 is adjusted and a chemical solution such as a resist solution is introduced into and passed through each processing apparatus, the processing of each processing apparatus in the substrate processing system 1 is subsequently performed. Conditions (processing recipes and parameters) are adjusted. Then, after a series of photolithography processes are performed in the substrate processing system 1 to form a resist pattern on the wafer W, the dimension of the resist pattern is measured by the dimension measuring device 210 to confirm the finish of the resist pattern.

  The substrate processing system 1 is provided with a plurality of types of processing apparatuses, for example, a plurality of PAB apparatuses 40 and a plurality of PEB apparatuses 41. Each processing step in the photolithography process is performed by selecting one processing apparatus from a plurality of processing apparatuses. Hereinafter, the path of the processing apparatus through which the wafer W passes when performing each processing step is referred to as a “processing path”. Then, a resist pattern dimension is acquired for each processing path.

  As shown in FIG. 8, the resist pattern dimension is acquired for each shot in the exposure process. If there is a shot that coincides with the measurement points k1 to k5 of the wafer W, the resist pattern dimension l [k] in that shot is extracted. If there is no shot that coincides with the measurement points k1 to k5 of the wafer W, for example, the resist pattern dimension in the shot nearest to the measurement points k1 to k5 is substituted, or the shots around the measurement points k1 to k5 are used. The resist pattern dimension is calculated by appropriate two-dimensional interpolation. Then, the resist pattern dimension l [k] corresponding to the measurement points k1 to k5 of the wafer W is acquired.

  The resist pattern dimension l [k] obtained in this way is recorded in association with each processing path. These resist pattern dimensions l [k] are used to derive a reaction model.

  As described above, the wafer temperature θ [k, t] and the resist pattern dimension l [k] are acquired when setting up or maintaining the PEB apparatus 41 or when processing conditions after adding a chemical solution such as a resist solution are acquired. be able to. That is, inspection data acquired at normal time is used for the wafer temperature θ [k, t] and the resist pattern dimension l [k]. For this reason, in order to derive a reaction model, there is almost no need for irregular operations that are different from normal operations such as special data collection and correlation formulation.

  An example of the wafer temperature θ [k, t] and the resist pattern dimension l [k] are shown in FIG. The substrate processing system 1 is provided with a plurality of various processing apparatuses for performing a photolithography process. Here, two first PAB apparatuses 40 (A1) and a second PAB apparatus 40 (A2) are used as processing paths. Combination of two first PEB devices 41 (E1) and second PEB devices 41 (E2), two first development processing devices 30 (D1) and second development processing devices 30 (D2), and others The processing path which made these processing apparatuses common is illustrated.

  Then, as shown in FIG. 10, the wafer temperature θ [k, t] of the second PEB device 41 (E2) is subtracted from the wafer temperature θ [k, t] of the first PEB device 41 (E1) to obtain a PEB device. A wafer temperature difference Δθ [k, t] between 41 is calculated.

  Further, the resist pattern dimension l [k] shown in FIG. 9 is averaged for each group of the first PEB device 41 (E1) and the second PEB device 41 (E2). Thereafter, as shown in FIG. 10, the average resist pattern dimension l [k] of the second PEB apparatus 41 (E2) is subtracted from the average resist pattern dimension l [k] of the first PEB apparatus 41 (E1) to obtain a PEB apparatus. A resist pattern dimension difference Δl [k] between 41 is calculated.

  Then, by taking the difference between the first PEB device 41 (E1) and the second PEB device 41 (E2) in this way, the influence of the PAB device 40 and the development processing device 30 is eliminated, and the PEB processing is directly performed. The correlation between the wafer temperature at and the resist pattern dimension resulting from the PEB process can be obtained.

  In the following description, the wafer temperature difference Δθ [k, t] and the resist pattern dimension difference Δl [k] may be collectively referred to as “difference data”.

  Further, the processing paths shown in FIGS. 9 and 10 are examples, and the selection of the processing paths can be arbitrarily performed. For example, in the above example, there are two PEB devices 41, and there is one difference data between the PEB devices 41. For example, when there are three PEB devices 41, there are three difference data. For example, when there are four PEB devices 41, the difference data is six. Thus, the number of difference data is the number of combinations of PEB devices 41. Hereinafter, the number of the difference data is i.

  The reaction model c [t] is derived from the wafer temperature difference Δθ [k, t] and the resist pattern dimension difference Δl [k]. This reaction model c [t] is a weighting factor in the time direction for the wafer temperature difference Δθ [k, t]. Specifically, the product sum of the reaction model c [t] and the wafer temperature difference Δθ [k, t], that is, the product of the reaction model c [t] and the wafer temperature difference Δθ [k, t] is integrated at the time t. If c [t] is determined so that the value is close to the resist pattern dimension difference Δl [k], the c [t] becomes a reaction model. That is, the reaction model c [t] is the information itself of the latent image formation speed (hereinafter referred to as “reaction speed”) of the resist pattern that changes with time during the PEB process. In the following description, c [t] may be referred to as a reaction model and may be referred to as a reaction rate, but both have the same meaning.

  In deriving the reaction model c [t], as a constraint condition, the reaction rate at the start of heat treatment and at the end of heat treatment is set to zero, that is, c [0] = c [T] = 0. T is the PEB processing time including heating and cooling. The reaction rate c [t] is continuous in the time direction, and as described above, the product sum of the reaction model c [t] and the wafer temperature difference Δθ [k, t] becomes the resist pattern dimension difference Δl [k]. The reaction model c [t] is determined so as to be close.

但し、Ｆ：評価関数、Ｃ［ｔ］：反応モデル、Δθ［ｔ、ｋ］：ウェハ温度差、Δｌ［ｋ］：レジストパターン寸法差、ｔ：ＰＥＢ処理開始をゼロとしたＰＥＢ処理の経過時間、Ｔ：ＰＥＢ処理終了時の時間、ｋ：ウェハ温度の測定点の番号（レジストパターン寸法の測定点の番号）、Ｋ：ウェハ温度の測定点の総数（レジストパターン寸法の測定点の総数）、ｉ：複数のＰＥＢ装置から取得される差分データの総数（ウェハ温度の差の総数、レジストパターン寸法の差の総数）Specifically, the optimization problem is solved so that the evaluation function represented by the following formula (1) approaches zero, and the reaction model c [t] is determined. That is, when several patterns of reaction models c [t] are prepared, the constraint condition is satisfied, and optimization calculation is performed where the evaluation function of the following formula (1) approaches zero, one reaction model c [t] is obtained. To be determined.

Where F: evaluation function, C [t]: reaction model, Δθ [t, k]: wafer temperature difference, Δl [k]: resist pattern dimension difference, t: PEB processing elapsed time with zero PEB processing start. T: time at the end of PEB processing, k: number of measurement points of wafer temperature (number of measurement points of resist pattern dimension), K: total number of measurement points of wafer temperature (total number of measurement points of resist pattern dimension), i: Total number of difference data acquired from a plurality of PEB apparatuses (total number of differences in wafer temperature, total number of differences in resist pattern dimensions)

  The first term on the right side of the above formula (1) indicates a condition that the reaction rate c [t] is continuous in the time direction. This is the sum of squares of the change amount of c [t] in one data acquisition interval (sampling time interval), and a small value indicates that the time change of c [t] is smooth.

  The second term on the right side of the above equation (1) represents a condition that the product sum of the reaction model c [t] and the wafer temperature difference Δθ [k, t] is close to the resist pattern dimension difference Δl [k]. If the sum of products Σc [t] · Δθ [k, t] and Δl [k] is small and the value is small, the resist pattern dimension component (hereinafter referred to as “ This indicates that the accuracy of predicting “PEB component” is high.

  Further, in addition to the above formula (1), if sensitivity information γ indicating the rate of change of the resist pattern dimension with respect to the wafer temperature when the PEB process is further performed with respect to the resist solution is known in advance, the sensitivity information γ is calculated. It may be added to the evaluation function. The sensitivity information γ is information indicating how much the resist pattern dimension changes when the wafer temperature changes by 1 ° C.

但し、γ：感度情報（単位はｎｍ／℃）Specifically, the optimization problem is solved so that the evaluation function represented by the following formula (2) approaches zero, and the reaction model c [t] is determined.

Where γ: sensitivity information (unit: nm / ° C)

  The third term on the right side of the above equation (2) is the sum of squares of the deviation between the actual sensitivity information γ and the sensitivity estimated from the reaction model c [t], that is, the time integral value of the reaction model c [t]. The condition that the time integral value of the reaction model c [t] is close to the sensitivity information γ is shown.

  The reaction model c [t] shown in FIG. 11 can be automatically derived using the evaluation function of the above formula (1) or formula (2). In FIG. 11, the horizontal axis indicates time t, and the vertical axis indicates the reaction model c [t]. Since the reaction mechanism of PEB processing is automatically modeled in this way, it is not necessary to take time and labor as in the prior art, and the throughput of wafer processing can be improved and productivity can be improved.

  In addition, as a result of intensive studies by the present inventor, it has been empirically known that a reaction model c [t] with higher accuracy can be obtained as the difference data number i increases.

  The reaction model c [t] is uniquely determined with respect to the type of resist. Therefore, the reaction model c [t] is a model common to the plurality of PEB apparatuses 41.

<First use method of reaction model>
Next, a first usage method of the reaction model c [t] for PEB processing will be described. When the reaction model c [t] is close to zero, it means that the reaction rate is close to zero. A time zone in which the latent image formation speed of the resist pattern is slow in PEB processing indicates that the chemical reaction is not progressing, and is not so meaningful from the viewpoint of the PEB processing. In particular, the time when the reaction rate is zero in the cooling process after heating is a wasteful process time, and there is no problem even if it is positively excluded from the PEB treatment.

  As shown in FIG. 12, after the start of cooling in the PEB process, a time zone tc in which the reaction model c [t] is almost zero is cut. For example, when the cooling time of the wafer W is specified in the heat treatment conditions (recipe setting, etc.) of the PEB process, the time zone tc is cut from the cooling time. If it does so, the processing time of the whole PEB process can be shortened, the throughput of a wafer process can be improved, and productivity can be improved.

<Second use of reaction model>
Next, a second usage method of the reaction model c [t] for PEB processing will be described. Here, the temperature operation amount of the hot plate 330 in each PEB apparatus 41 is derived, and the resist pattern is uniformly formed in the wafer surface while canceling out the machine difference between the PEB apparatuses 41.

First, an in-plane average is calculated for the wafer temperature θ [k, t] recorded for each PEB apparatus 41. Hereinafter, no. The in-plane average wafer temperature in the p PEB apparatus 41 is represented by θp _mean [t]. That is, the in-plane average wafer temperature in the first PEB apparatus 41 (E1) is θ1 _mean [t], and the in-plane average wafer temperature in the second PEB apparatus 41 (E2) is θ2 _mean [t].

  On the other hand, as shown in FIG. 13, the product sum of the reaction model c [t] and the wafer temperature θ [k, t] recorded for each PEB apparatus 41, that is, the reaction model c [t] and the wafer temperature difference θ [k, t ] Is integrated over time t. This sum of products is estimated as a dimensional component (hereinafter referred to as “PEB component”) l ′ [k] of the resist pattern formed due to the PEB process out of the resist pattern size l [k]. Hereinafter, no. The PEB component in the p PEB apparatus 41 is assumed to be l'p [k]. That is, the PEB component in the first PEB device 41 (E1) is l'1 [k], and the PEB component in the second PEB device 41 (E2) is l'2 [k].

Then, for each PEB device 41, an in-plane average of PEB components is calculated. Hereinafter, no. The in-plane average PEB component in the p PEB apparatus 41 is defined as l′ p _mean . That is, the in-plane average PEB component in the first PEB device 41 (E1) is l′ 1 _mean , and the in-plane average PEB component in the second PEB device 41 (E2) is l′ 2 _mean .

When there is a machine difference between the PEB apparatuses 41, the machine difference can be canceled by using the in-plane average wafer temperature θp _mean [t], the in-plane average PEB component l′ p _mean and the reaction model c [t]. It is possible to derive the operation amount of the wafer temperature necessary for the above.

但し、Ｇ：ウェハ温度操作倍率、ｌ’１_ｍｅａｎ：第１のＰＥＢ装置４１（Ｅ１）における面内平均ＰＥＢ成分、ｌ’２_ｍｅａｎ：第２のＰＥＢ装置４１における面内平均ＰＥＢ成分、Ｃ［ｔ］：反応モデル、θ１_ｍｅａｎ［ｔ］：第１のＰＥＢ装置４１（Ｅ１）における面内平均ウェハ温度、ｔ：ＰＥＢ処理開始をゼロとしたＰＥＢ処理の経過時間、Ｔ：ＰＥＢ処理終了時の時間Specifically, for example, when it is desired to cancel the machine difference of the first PEB device 41 (E1) with respect to the second PEB device 41 (E2), the wafer temperature operation magnification obtained by the following equation (3) is used.

Where G: wafer temperature operation magnification, l′ 1 _mean : in-plane average PEB component in the first PEB apparatus 41 (E1), l′ 2 _mean : in-plane average PEB component in the second PEB apparatus 41, C [ t]: Reaction model, θ1 _mean [t]: In-plane average wafer temperature in the first PEB apparatus 41 (E1), t: PEB processing elapsed time with zero PEB processing start, T: PEB processing end time time

但し、Δθ１_ｍｅａｎ：第１のＰＥＢ装置４１（Ｅ１）におけるウェハ温度の操作量、θ１_ｍｅａｎ［ｔ］：第１のＰＥＢ装置４１（Ｅ１）における面内平均ウェハ温度、θｂ：ＰＥＢの加熱温度、Ｇ：ウェハ温度操作倍率Then, the operation amount Δθ1 _mean of the wafer temperature in the first PEB apparatus 41 (E1) is calculated by the following equation (6). In such a case, the machine difference between the PEB apparatuses 41 can be canceled, and the in-plane average wafer temperature θ1 _mean [t] in the first PEB apparatus (E1) is changed to the in-plane average in the second PEB apparatus 41 (E2). It can approach the average wafer temperature θ2 _mean [t].

However, Δθ1 _mean : Manipulation amount of wafer temperature in the first PEB apparatus 41 (E1), θ1 _mean [t]: In-plane average wafer temperature in the first PEB apparatus 41 (E1), θb: Heating temperature of PEB, G: Wafer temperature operation magnification

Furthermore, as shown in FIG. 14, the correlation between the operation amount of the hot plate temperature in the PEB apparatus 41 and the change amount of the wafer temperature is obtained in advance. In general, there is a linear correlation between the hot plate temperature manipulated variable x and the wafer temperature change amount y within a very narrow range. Then, based on the correlation equation y = a · x shown in FIG. 14, the wafer temperature operation amount Δθ1 _mean in the first PEB apparatus 41 (E1) obtained using the wafer temperature operation magnification of the above equation (3) is The temperature of the hot plate 330 is set in terms of the hot plate temperature manipulated variable.

According to the present embodiment, the temperature of the hot plate 330 in the first PEB device 41 (E1) can be set without using an operator. Then, using the difference between the in-plane average PEB components l′ 1 _mean and l′ 2 _mean , the machine difference between the PEB apparatuses 41 can be canceled, and the resist pattern can be formed uniformly in the wafer plane. .

In the above embodiment, the first PEB device 41 (E1) with respect to the second PEB device 41 (E2) is obtained by using the difference between the in-plane average PEB components l′ 1 _mean and l′ 2 _{mean in} the equation (3). However, the average value of the in-plane average PEB components l′ 1 _mean and l′ 2 _mean may be used.

Specifically, the wafer temperature operation magnification G is calculated using the following equation (4), and the wafer temperature operation amount Δθ1 _mean in the first PEB apparatus 41 (E1) is calculated using the above equation (6). . Further, the wafer temperature operation magnification G is calculated using the following equation (5), and the operation amount Δθ2 _mean of the wafer temperature in the second PEB apparatus 41 (E2) is calculated using the equation corresponding to the above equation (6). To do.

  Even in such a case, the machine difference between the PEB apparatuses 41 can be canceled without an operator, and the resist pattern can be formed uniformly in the wafer surface.

  In addition, the 2nd utilization method of this reaction model c [t] is demonstrated also in the Example mentioned later.

<Third use of reaction model>
Next, a third method of using the reaction model c [t] for PEB processing will be described. Here, the processing path is selected so that the resist pattern is uniformly formed in the wafer surface.

  When the wafer temperature θ [k, t] and the resist pattern dimension l [k] shown in FIG. 9 are actually limited in terms of time, the resist pattern dimension l [k] for all the processing paths can be measured. Is not limited. For example, as shown in FIG. 15, when the resist pattern dimension l [k] of the processing path passing through the second PAB apparatus (A2) is not acquired in the first PEB apparatus 41 (E1), In some cases, the resist pattern dimension l [k] of the processing path passing through the first PAB apparatus (A1) is not acquired in the PEB apparatus 41 (E2). In this embodiment, the resist pattern dimension l [k] of such a processing path is estimated, and an optimal processing path is selected.

  First, as shown in FIG. 16, the PEB component l′ 1 [k] in the first PEB device 41 (E1) and the PEB component l′ 2 [k] in the second PEB device 41 (E2) are calculated. . Since the calculation method of these PEB components l′ 1 [k] and l′ 2 [k] is the same as the calculation method for the second usage method, detailed description thereof is omitted.

  Next, the PEB component l′ 1 [k] is subtracted from the resist pattern dimension l [k] in the first PEB apparatus 41 (E1). Then, processing other than the first PEB device 41 (E1), that is, a resist pattern dimension component (hereinafter referred to as other processing component) l ″ 1 [k] caused by the first PAB device 40 (A1). Is estimated.

  Similarly, when the PEB component l′ 2 [k] is subtracted from the resist pattern dimension l [k] in the second PEB device 41 (E2), processing other than the second PEB device 41 (E2), that is, the second A resist pattern dimension component (hereinafter referred to as other processing component) l ″ 2 [k] caused by the PAB apparatus 40 (A2) is estimated.

  Then, when the PEB component l′ 1 [k] and the other processing component l ″ 2 [k] are added as shown in FIG. 17, the first PEB device 41 (E1) and the second PAB device 40 (E2) are added. Then, the resist pattern dimensions of all the processing paths are obtained for the first PEB apparatus 41 (E1) as shown in FIG. Then, it is possible to select an optimum processing path in which the resist pattern dimension l [k] is uniform in the plane, in the illustrated example, the second PAB device 40 is compared to the first PEB device 41 (E1). (A2) and the first development processing apparatus 30 (D1) are selected.

  Similarly, when the PEB component l′ 2 [k] and the other processing component l ″ 1 [k] are added as shown in FIG. 17, the second PEB device 41 (E2) and the first PAB device 40 (E1 Then, the resist pattern dimensions of all the processing paths are obtained for the second PEB apparatus 42 (E2) as shown in FIG. In addition, in the illustrated example, the first PAB apparatus can be selected with respect to the second PEB apparatus 41 (E2). 40 (A1) and the second development processing apparatus 30 (D2) are selected.

  According to the present embodiment, even when the resist pattern dimension l [k] for all the processing paths is not acquired in advance, the resist pattern dimension l [k] for all the processing paths can be estimated. Accordingly, since the optimum processing path can be selected from as many processing paths as possible, the in-plane uniformity of the resist pattern can be improved.

  In this case, for example, even when one PEB device 41 is replaced for maintenance or failure, if the wafer temperature measured by the alternative PEB device 41 is acquired, the optimum PEB device 41 for the alternative PEB device 41 is obtained. A processing path can be selected. Therefore, the efficiency of wafer processing can be improved.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various changes or modifications can be conceived within the scope of the idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood.

  In the above embodiment, the average temperature of the hot plate 330 in the PEB apparatus 41 is adjusted to make the resist pattern uniform in the surface. In this regard, the hot plate 330 may be partitioned into a plurality of regions, the above embodiment may be performed for each region, and the temperature may be adjusted for each region.

  The second method of using the reaction model c [t] described above will be described using specific data. The data shown in the present embodiment is virtual data.

  As shown in FIG. 19, a reaction model c [t] is derived in advance.

As shown in FIG. 20, the wafer temperature θ1 [k, t] in the first PEB apparatus is acquired. Then, θ1 _mean [t] is calculated as the in-plane average wafer temperature from the wafer temperature θ1 [k, t], and θ1 _mean [t] −θ1 _mean [0] is calculated. Then, the PEB component l′ 1 [k] is calculated using the reaction model c [t] shown in FIG. 19, and the in-plane average PEB component l′ 1 _mean is further calculated. Thus, the in-plane average PEB component l′ 1 _mean is calculated to be 113.6 nm.

The same process is performed for the second PEB apparatus. As shown in FIG. 21, the wafer temperature θ2 [k, t] in the second PEB apparatus is acquired. Then, θ2 _mean [t] is calculated as the in-plane average wafer temperature from the wafer temperature θ2 [k, t], and θ2 _mean [t] −θ2 _mean [0] is calculated. Then, the PEB component l′ 2 [k] is calculated using the reaction model c [t] shown in FIG. 19, and the in-plane average PEB component l′ 2 _mean is calculated. Thus, the in-plane average PEB component l′ 2 _mean is calculated to be 113.364 nm.

In this case, as shown in FIG. 22, the difference (= l′ 2 _mean −l′1 _mean ) in the in-plane average PEB component between the PEB apparatuses is −0.236 nm.

Next, using the following equation (3), the wafer temperature operation magnification G in the first PEB apparatus is calculated as 0.997378. That is, when the wafer temperature θ1 [k, t] is multiplied by 0.997378 in the first PEB apparatus, a value close to the wafer temperature θ2 [k, t] in the second PEB apparatus is obtained.

Next, using the following formula (6), the wafer temperature manipulated variable Δθ1 _mean in the first PEB apparatus is calculated as −0.20978 ° C. That is, when −0.20978 ° C. is added to the wafer temperature θ1 [k, t] in the first PEB apparatus, a value close to the wafer temperature θ2 [k, t] in the second PEB apparatus is obtained. In the present embodiment, the heating temperature θb of the PEB process in the first PEB apparatus is 100 ° C.

  Here, as shown in FIG. 23, the correlation between the operation amount of the hot plate temperature and the change amount of the wafer temperature in the PEB apparatus is obtained in advance. In this embodiment, a = 0.4317 for (wafer temperature change amount y) = (coefficient a) × (hot plate temperature manipulated variable x).

Then, using this correlation equation, −0.20978 ° C., which is the wafer temperature manipulated variable Δθ1 _mean , is divided by a coefficient a of 0.4317 as shown in FIG. 22 to obtain a hot plate temperature manipulated variable Δθb. When converted, Δθb is calculated to be −0.48593 ° C. Then, θb + Δθb is calculated, and the temperature of the hot plate in the first PEB apparatus is updated. As described above, in this embodiment, the temperature of the hot plate in the first PEB apparatus is updated from 100 ° C. to 99.5407 ° C.

DESCRIPTION OF SYMBOLS 1 Substrate processing system 12 Exposure apparatus 30 Development processing apparatus 32 Resist coating apparatus 40 PAB apparatus 41 PEB apparatus 42 POST apparatus 43 Heat processing apparatus 200 Control part 210 Dimension measurement apparatus 310 Heating part 311 Cooling part 330 Hot plate 334-338 Temperature sensor 350 Cooling Plate W Wafer

Claims (12)

A substrate processing method for performing a photolithography process on a substrate and forming a resist pattern on the substrate,
A temperature difference calculating step of measuring a substrate temperature over time in a plurality of heat treatment apparatuses that perform heat treatment in photolithography processing, and calculating a difference in substrate temperature between the heat treatment apparatuses;
Dimensional difference in which a photolithography process including heat treatment using the plurality of heat treatment apparatuses is performed on a substrate, a resist pattern is formed on the substrate, a resist pattern dimension is measured, and a difference in resist pattern dimension between the heat treatment apparatuses is calculated. A calculation process;
Using the difference between the substrate temperature and the difference between the resist pattern dimensions, a reaction rate for converting the substrate temperature into a resist pattern dimension is calculated, and a model derivation is performed that derives a reaction model that is a function of time for the reaction rate. Process,
A condition setting step for setting processing conditions for substrate processing using the reaction model,
In the model derivation step,
The reaction rate at the beginning and end of heat treatment is zero,
An optimization function is defined for the reaction model so that the reaction rate is continuous in the time direction, and the product sum of the substrate temperature difference and the reaction model is close to the resist pattern dimension difference. A substrate processing method for solving and determining the reaction model. The substrate processing method according to claim 1,
2. The substrate processing method according to claim 1, wherein in the model derivation step, the evaluation function is expressed by the following formula (1), and the reaction model is determined so that the evaluation function approaches zero.

Where F: evaluation function, C [t]: reaction model, Δθ [t, k]: difference in substrate temperature, Δl [k]: difference in resist pattern dimensions, t: elapsed time of heat treatment with zero start of heat treatment , T: time at the end of heat treatment, k: number of measurement points for substrate temperature (number of measurement points for resist pattern dimensions), K: total number of measurement points for substrate temperature (total number of measurement points for resist pattern dimensions), i : Total number of substrate temperature differences obtained from multiple heat treatment systems (total number of resist pattern dimension differences) The substrate processing method according to claim 1,
Sensitivity information indicating the rate of change of resist pattern dimensions with respect to the substrate temperature when the heat treatment is performed is acquired in advance,
In the model deriving step, an optimization problem is solved for the reaction model so that the time integral value of the reaction model is close to the sensitivity information, and the reaction model is determined. The substrate processing method according to claim 3,
In the model derivation step, the evaluation function is expressed by the following formula (2), and the reaction model is determined so that the evaluation function approaches zero.

Where F: evaluation function, C [t]: reaction model, Δθ [t, k]: difference in substrate temperature, Δl [k]: difference in resist pattern dimensions, t: elapsed time of heat treatment with zero start of heat treatment , T: time at the end of heat treatment, k: number of measurement points for substrate temperature (number of measurement points for resist pattern dimensions), K: total number of measurement points for substrate temperature (total number of measurement points for resist pattern dimensions), i : Total number of substrate temperature differences (total number of resist pattern dimension differences) acquired from multiple heat treatment apparatuses, γ: Sensitivity information The substrate processing method according to claim 1,
The processing condition set in the condition setting step is a heat treatment time,
After the cooling of the substrate is started, the heat treatment is finished excluding the time when the reaction model becomes zero. The substrate processing method according to claim 1,
The processing condition set in the condition setting step is a temperature operation amount of a hot plate of the heat treatment apparatus,
The condition setting step includes
Measuring the substrate temperature over time for each heat treatment apparatus, and calculating an in-plane average substrate temperature that is an in-plane average of the substrate temperature;
Calculate the sum of products of the reaction model and the substrate temperature measured for each heat treatment apparatus, and among the resist pattern dimensions, a heat treatment component that is a dimension component of a resist pattern formed due to heat treatment in the heat treatment apparatus And calculating an in-plane average heat treatment component that is an in-plane average of the heat treatment component, and
Using the in-plane average substrate temperature and the in-plane average heat treatment component in the first heat treatment apparatus, and the in-plane average substrate temperature and the in-plane average heat treatment component in the second heat treatment apparatus, at least the first Calculating the manipulated variable of the substrate temperature in the heat treatment apparatus or the second heat treatment apparatus;
And calculating the operation amount of the hot plate temperature based on the operation amount of the substrate temperature using the correlation between the hot plate temperature and the substrate temperature obtained in advance. The substrate processing method according to claim 6,
Based on the substrate temperature operation magnification obtained by the following equation (3), the operation amount of the substrate temperature in the first heat treatment apparatus is calculated.

Where G: substrate temperature operation magnification, l′ 1 _mean : in-plane average heat treatment component in the first heat treatment apparatus, l′ 2 _mean : in-plane average heat treatment component in the second heat treatment apparatus, C [t]: reaction model , Θ1 _mean [t]: In-plane average substrate temperature in the first heat treatment apparatus, t: Elapsed time of heat treatment with zero heat treatment start, T: Time at the end of heat treatment The substrate processing method according to claim 6,
Based on the substrate temperature operation magnification obtained by the following formula (4), the operation amount of the substrate temperature in the first heat treatment apparatus is calculated,
Based on the substrate temperature operation magnification obtained by the following equation (5), the operation amount of the substrate temperature in the second heat treatment apparatus is calculated.

Where G: substrate temperature operation magnification, l′ 1 _mean : in-plane average heat treatment component in the first heat treatment apparatus, l′ 2 _mean : in-plane average heat treatment component in the second heat treatment apparatus, C [t]: reaction model , Θ1 _mean [t]: In-plane average substrate temperature in the first heat treatment apparatus, θ2 _mean [t]: In-plane average substrate temperature in the second heat treatment apparatus, t: Elapsed time of heat treatment with the heat treatment start being zero, T: Time at the end of heat treatment The substrate processing method according to claim 1,
The photolithography process is performed using a plurality of types of processing apparatuses in addition to the heat treatment apparatus,
The processing condition set in the condition setting step is a selection method of the processing apparatus for the heat treatment apparatus,
The condition setting step includes
Performing a photolithography process using a first heat treatment apparatus and a first processing apparatus to form a first resist pattern, and then measuring a first resist pattern dimension;
The sum of products of the reaction model and the substrate temperature measured by the first heat treatment apparatus is calculated, and the first resist pattern dimension formed by the heat treatment in the first heat treatment apparatus is calculated. Estimating a first heat treatment component that is a dimensional component of one resist pattern;
A first resist pattern dimension component formed by subtracting the first heat treatment component from the first resist pattern dimension and resulting from a process other than the heat treatment in the first heat treatment apparatus. Estimating one other processing component;
Performing a photolithography process using a second heat treatment apparatus and a second processing apparatus to form a second resist pattern, and then measuring a second resist pattern dimension;
The sum of products of the reaction model and the substrate temperature measured by the second heat treatment apparatus is calculated, and the second resist pattern dimension is formed by the heat treatment performed by the second heat treatment apparatus. Estimating a second heat treatment component which is a dimensional component of the resist pattern of 2,
A second resist pattern dimension component formed by subtracting the second heat treatment component from the second resist pattern dimension and resulting from a process other than the heat treatment in the second heat treatment apparatus. Estimating two other processing components;
A third resist pattern dimension when a photolithography process is performed using the first heat treatment apparatus and the second treatment apparatus by adding the first heat treatment component and the second other treatment component together. A calculating step;
Comparing the first resist pattern dimension with the third resist pattern dimension and selecting the first processing apparatus or the second processing apparatus with respect to the first heat treatment apparatus;
A fourth resist pattern dimension when the second heat treatment component and the first other treatment component are added together and a photolithography process is performed using the second heat treatment apparatus and the first processing apparatus is obtained. A calculating step;
Comparing the second resist pattern dimension with the fourth resist pattern dimension and selecting the first processing apparatus or the second processing apparatus for the second heat treatment apparatus. . The substrate processing method according to claim 1,
The heat treatment is a heat treatment performed after the exposure process in the photolithography process and before the development process. Reading that stores a program that operates on a computer of a control unit that controls the substrate processing system so that the substrate processing system executes a substrate processing method for performing a photolithography process on the substrate and forming a resist pattern on the substrate. A possible computer storage medium,
The substrate processing method includes:
A temperature difference calculating step of measuring a substrate temperature over time in a plurality of heat treatment apparatuses that perform heat treatment in photolithography processing, and calculating a difference in substrate temperature between the heat treatment apparatuses;
Dimensional difference in which a photolithography process including heat treatment using the plurality of heat treatment apparatuses is performed on a substrate, a resist pattern is formed on the substrate, a resist pattern dimension is measured, and a difference in resist pattern dimension between the heat treatment apparatuses is calculated. A calculation process;
Using the difference between the substrate temperature and the resist pattern dimension, a reaction rate for converting the substrate temperature into the resist pattern dimension is calculated, and a model derivation for deriving a reaction model that is a function of time for the reaction rate Process,
A condition setting step for setting processing conditions for substrate processing using the reaction model,
In the model derivation step,
The reaction rate at the beginning and end of heat treatment is zero,
An optimization function is defined for the reaction model so that the reaction rate is continuous in the time direction, and the product sum of the substrate temperature difference and the reaction model is close to the resist pattern dimension difference. Solve and determine the reaction model. A substrate processing system for performing a photolithography process on a substrate and forming a resist pattern on the substrate,
A plurality of heat treatment apparatuses for performing heat treatment on the substrate;
A dimension measuring apparatus for measuring a resist pattern dimension on a substrate;
A control unit for setting processing conditions for substrate processing,
The controller is
A temperature difference calculating step of measuring a substrate temperature over time in the plurality of heat treatment apparatuses and calculating a difference in substrate temperature between the heat treatment apparatuses;
A photolithography process is performed on the substrate using the plurality of heat treatment apparatuses, a resist pattern is formed on the substrate, a resist pattern dimension is measured by the dimension measuring apparatus, and a difference in resist pattern dimension between the heat treatment apparatuses is calculated. Dimensional difference calculation process,
Using the difference between the substrate temperature and the difference between the resist pattern dimensions, a reaction rate for converting the substrate temperature into a resist pattern dimension is calculated, and a model derivation is performed that derives a reaction model that is a function of time for the reaction rate. Process,
Executing a condition setting step for setting processing conditions for substrate processing using the reaction model;
In the model derivation step,
The reaction rate at the beginning and end of heat treatment is zero,
An optimization function is defined for the reaction model so that the reaction rate is continuous in the time direction, and the product sum of the substrate temperature difference and the reaction model is close to the resist pattern dimension difference. Solve and determine the reaction model,
It is configured as follows.

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