JPWO2018051946A1 - Integrated circuit - Google Patents

Abstract

Provide an integrated circuit with low power consumption. The integrated circuit includes a plurality of first wirings each end of which is used as an input terminal, and a plurality of second wirings each end of which is used as an output terminal and which is connected to each of the first wirings. A plurality of switches for connecting a wire, a bias wire connected to each of the second wires and connected to a power supply or a ground, a first wire or bias wire, and a second wire, and a bias wire And a selection circuit for selecting an electrical connection with either the power supply or the ground.

Description

  The present invention relates to integrated circuits.

  As an example of integrated circuits, reconfigurable integrated circuits are used. The reconfigurable integrated circuit is configured into various logic circuits by rewriting internal setting information. Due to such characteristics, reconfigurable integrated circuits are used in various fields, such as being used to create prototypes and as circuits for image processing, communication, and the like.

  In addition, resistance change elements are being used as memory cells and switches included in integrated circuits. The variable resistance element is also called a variable resistance non-volatile element. The resistance change element transitions between a state of high resistance and a state of low resistance due to application of voltage or current. The resistance value of the variable resistance element is held in a non-volatile manner. By replacing memory cells and switches included in the integrated circuit with resistance change elements, chip area and power consumption can be reduced. A similar technique is also described in Non-Patent Document 1.

  Patent Document 1 describes an example of a reconfigurable circuit chip using a variable resistance element. In the example described in Patent Document 1, the variable resistance element is used as a routing switch or a memory.

  Further, Patent Documents 2 to 4 each describe an example of a variable resistance element. Patent Document 2 describes an example of a resistive random access memory (ReRAM). Patent Document 3 describes an example of a phase change random access memory (PRAM). In addition, Patent Document 4 describes a resistance change memory called NanoBridge (registered trademark) in which resistance value is changed by controlling generation / destruction of a bridge formed by a metal atom in a solid electrolyte with an applied voltage. .

International Publication No. 2015/198573 JP, 2006-340096, A JP 10-228780 A Japanese Patent Application Laid-Open No. 09-135358

Makoto Miyamura et al. Low-power programmable-logic cell arrays using non-volatile complementary atom switch, ISQED 2014, pp. 330-334. Xu Bai et al. Area-efficient nonvolatile carry chain based on pass-transistor / atom-switch hybrid logic, Jpn. J. Appl. Phys. 55 (4S), 04EF 01, 2016-03-01. Toshitsugu Sakamoto et al. , A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM, IEEE Micro, vol. 35, No. 06, pp. 13-23.

  The integrated circuit including the above-described reconfigurable integrated circuit preferably consumes less power. That is, further reduction in power consumption is required for integrated circuits using each prior art document.

  The present invention has been made to solve the above-mentioned problems, and its main object is to provide an integrated circuit with low power consumption.

  In the integrated circuit according to one aspect of the present invention, a plurality of first wirings each end of which is used as an input terminal, and an end each of which is used as an output terminal, and each is connected to each of the first wirings And a plurality of second wirings, a plurality of second wirings connected to each of the second wirings, and a plurality of bias wirings connected to the power supply or the ground, the first wiring or the bias wirings, and the second wirings. , A bias wiring, and a selection circuit which selects an electrical connection with either the power supply or the ground.

  According to the present invention, an integrated circuit with low power consumption can be provided.

FIG. 1 shows an integrated circuit in a first embodiment of the invention. FIG. 1 shows a reconfigurable integrated circuit comprising an integrated circuit according to a first embodiment of the invention. It is a figure showing an example in case a plurality of switches are realized by a resistance change element in an integrated circuit in a 1st embodiment of the present invention. It is a figure which shows the example of the crossbar switch circuit used as the comparative example of the integrated circuit in the 1st Embodiment of this invention. It is a figure which shows the example in case the leak current arises in the crossbar switch circuit used as the comparative example of the integrated circuit in the 1st Embodiment of this invention. It is a flowchart which shows an example of the design method of the circuit comprised in a reconfigurable integrated circuit containing the integrated circuit in the 1st Embodiment of this invention. It is a figure which shows the example of arrangement | positioning of the control memory of a reconfigurable integrated circuit containing the integrated circuit in the 1st Embodiment of this invention. FIG. 7 is a diagram showing another arrangement example of control memory of the reconfigurable integrated circuit including the integrated circuit in the first embodiment of the present invention. FIG. 7 is a diagram showing another arrangement example of control memory of the reconfigurable integrated circuit including the integrated circuit in the first embodiment of the present invention. FIG. 7 is a diagram showing another arrangement example of control memory of the reconfigurable integrated circuit including the integrated circuit in the first embodiment of the present invention. FIG. 7 is a diagram showing another arrangement example of control memory of the reconfigurable integrated circuit including the integrated circuit in the first embodiment of the present invention. It is a figure which shows the example of the circuit of the control memory which the integrated circuit in the 1st Embodiment of this invention has. It is a figure which shows the simulation result of the leakage current which arises in the integrated circuit in the 1st Embodiment of this invention, and the circuit used as a comparative example.

  Embodiments of the present invention will be described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a diagram showing an integrated circuit in a first embodiment of the present invention. FIG. 2 is a diagram showing a reconfigurable integrated circuit in which the integrated circuit in the first embodiment of the present invention is used.

  As shown in FIG. 1, the integrated circuit 100 according to the first embodiment of the present invention includes, as main elements, a plurality of first wirings 110, a plurality of second wirings 120, a bias wiring 130, and a plurality of elements. A switch 140 and a selection circuit 150 are provided. The plurality of first wirings 110, the plurality of second wirings 120, and the plurality of switches 140 constitute a crossbar switch.

  One end of each of the plurality of first wirings 110 is used as an input terminal of the crossbar switch. In the example illustrated in FIG. 1, two wirings of first wirings 110-1 and 110-2 are provided as the plurality of first wirings 110. One end of each of the first wires 110-1 and 110-2 is used as input terminals IN0 and IN1, respectively. Each of the plurality of second wires 120 is connected to each of the plurality of first wires 110 via a plurality of switches 140 described later, and one end of each is used as an output terminal of the crossbar switch. In the example illustrated in FIG. 1, three wirings of second wirings 120-1 to 120-3 are provided as the plurality of second wirings 120. One end of each of the second wires 120-1 to 120-3 is used as an output terminal OUT0 to OUT2, respectively. The bias wiring 130 is connected to each of the plurality of second wirings 120 via the power supply and the ground and a plurality of switches 140 described later. The bias wiring 130 has the potential of the power supply or the potential of the ground in accordance with the selection of the selection circuit 150. Each of the plurality of switches 140 connects each of the plurality of first wirings 110 and the bias wiring 130 with each of the plurality of second wirings 120. In the example illustrated in FIG. 1, nine switches 140-1 to 140-9 are provided as the plurality of switches 140. The selection circuit 150 selects an electrical connection between the bias wiring 130 and the power supply or the ground. In the example illustrated in FIG. 1, the selection circuit 150 includes a PMOS (Metal Oxide Semiconductor) transistor 151, an NMOS transistor 152, and a control memory 153. The PMOS transistor 151 or the NMOS transistor 152 and the control memory 153 are connected via the selection wiring 154.

  The integrated circuit 100 in the present embodiment is applied as part of a reconfigurable integrated circuit, as an example. The reconfigurable integrated circuit is an integrated circuit whose circuit configuration can be changed by the user, and is, for example, an FPGA (Field Programmable Gate Array).

  FIG. 2 shows an example of the reconfigurable integrated circuit 1. In the example shown in FIG. 2, the reconfigurable integrated circuit 1 is configured by arranging the routing block 11 and the logic block 12 regularly. In this embodiment, a unit of an integrated circuit including one routing block 11 and logic block is referred to as a cell 10. That is, the reconfigurable integrated circuit 1 is configured by regularly arranging a plurality of cells 10. The integrated circuit 100 in the present embodiment is used as the routing block 11 in the cell 10.

  The regular arrangement of the plurality of cells 10 as the reconfigurable integrated circuit 1 is shown as (1) in FIG. Each square part included in (1) of FIG. 2 shows one cell 10. In the example shown in (1) of FIG. 2, the reconfigurable integrated circuit 1 includes 36 cells 10. That is, in this example, the cells 10 in six rows in the row direction and six columns in the column direction are two-dimensionally arranged in an array. The number of cells 10 included in the reconfigurable integrated circuit 1 is not particularly limited.

  An example of the configuration of each cell 10 is shown as (2) in FIG. The routing block 11 is configured by a crossbar switch circuit. That is, the routing block 11 includes, as an example, one wiring group, another wiring group that intersects the one wiring group, and a switch that connects each of the wiring groups. Also, the logic block 12 includes, for example, a look up table (LUT), a flip flop, a multiplexer, and the like. By appropriately setting the connection relation of the routing block 11, the LUT, and the like, a circuit having a configuration desired by the user of the reconfigurable integrated circuit 1 is realized.

  Also, an example of a portion of the routing block 11 is shown as (3) in FIG. In this example, each of the two input signal lines and each of the two output signal lines are connected via a switch. When the integrated circuit 100 is used as the routing block 11, the input signal line is a plurality of first wires 110, the output signal line is a plurality of second wires 120, and a switch connecting the input signal line and the output signal line Respectively correspond to the switches 140. The switch included in the routing block 11 may be a resistance change element as shown in (4) of FIG.

  Subsequently, details of each component of the integrated circuit 100 according to the first embodiment of the present invention will be described.

  One end of each of the plurality of first wirings 110 is used as an input terminal. In the example shown in FIG. 1, two wirings of first wirings 110-1 and 110-2 are provided as the plurality of first wirings 110. Further, in this example, one end of the first wiring 110-1 is used as the input terminal IN0 of the crossbar switch, and one end of the first wiring 110-2 is used as the input terminal IN1 of the crossbar switch It is done.

  Each of the plurality of second wires 120 is connected to each of the first wires 110 and a switch 140 described later. Further, one end of each of the plurality of second wires 120 is used as an output terminal. In the example illustrated in FIG. 1, three wirings of second wirings 120-1 to 120-3 are provided as the plurality of second wirings 120. Each of the second wires 120-1 to 120-3 is connected to the first wires 110-1 and 110-2 through a switch 140 described later. Further, one ends of the second wires 120-1 to 120-3 are used as output terminals OUT0 to OUT2 of the crossbar switch, respectively. In the example shown in FIG. 1, each of the output terminals of the second wiring 120 is connected to a buffer 160 described later.

  The bias wiring 130 is connected to each of the plurality of second wirings 120 via a switch 140 described later. In addition, the bias wiring 130 is electrically connected to the power supply VDD or the ground GND via the PMOS transistor 151 or the NMOS transistor 152 included in the selection circuit 150 described later. As described later, the bias wiring 130 is connected to the power supply VDD or the ground GND so as to be at the potential of either the power supply VDD or the ground GND according to the selection of the selection circuit 150. Further, in accordance with the connection of the switch 140, each of the plurality of second wirings 120 can be set to the same potential as the potential of the bias wiring 130. That is, the provision of the bias wiring 130 prevents the output terminal of the second wiring 120 from being in a so-called floating state.

  Each of the plurality of switches 140 connects either the first wiring 110 or the bias wiring 130 to any of the second wirings 120. In the example shown in FIG. 1, nine switches 140 from switches 140-1 to 140-9 are provided. Each of switches 140-1 to 140-6 connects each of first wires 110 to each of second wires 120. Each of the switches 140-7 to 140-9 connects the second wire 120 and the bias wire 130.

  Each of the plurality of switches 140 may be a complementary metal oxide semiconductor (CMOS) switch or a resistance change element. As described above, the resistance change element transits between a state of high resistance and a state of low resistance due to the application of voltage or current. When a variable resistance element is used as the plurality of switches 140, the state where the resistance value is large is an open state (off state) as the switch, and the state where the resistance value is small is a closed state as an switch (on state ). By using resistance change elements as the plurality of switches 140, power consumption of the integrated circuit 100 can be reduced. FIG. 3 shows an example in which a variable resistance element 141 is used as the plurality of switches 140 of the integrated circuit 100.

  The selection circuit 150 selects a connection between the bias wiring 130 and the power supply VDD or the ground GND. In response to the selection by selection circuit 150, bias interconnection 130 is electrically connected to either power supply VDD or ground GND. That is, the potential of the bias wiring 130 becomes either a high potential or a low potential corresponding to the power supply or the ground, depending on the selection by the selection circuit 150.

  In the present embodiment, the selection circuit 150 includes a control memory 153, a PMOS transistor 151, and an NMOS transistor 152. The gate electrode of each of the PMOS transistor 151 or the NMOS transistor 152 and the control memory 153 are connected via the selection wiring 154. The PMOS transistor 151 is provided between the power supply VDD and the bias wiring 130. That is, the PMOS transistor 151 operates as a switch that switches the electrical connection between the bias wiring 130 and the power supply VDD.

  Also, the NMOS transistor 152 is provided between the bias wire 130 and the ground GND. That is, the NMOS transistor 152 operates as a switch that switches the electrical connection between the ground and the bias wiring 130.

  The PMOS transistor 151 and the NMOS transistor 152 may be collectively referred to as a selection switch that switches the connection between the bias wiring 130 and the power supply or the ground.

  The control memory 153 controls the opening and closing of the PMOS transistor 151 and the NMOS transistor 152 which are selection switches. That is, the control memory 153 controls the opening and closing of the PMOS transistor 151 and the NMOS transistor 152 so that the bias wiring 130 and either the power supply VDD or the ground GND are electrically connected. The value held in the control memory 153 is propagated to the gate electrode of each of the PMOS transistor 151 or the NMOS transistor 152 through the selection wiring 154. That is, according to the value held in the control memory 153, the opening and closing of the PMOS transistor 151 or the NMOS transistor 152 is controlled.

  For example, when the value held in the control memory 153 is “0” (low potential), the PMOS transistor 151 is connected and the NMOS transistor 152 is shut off. In this case, the bias wiring 130 has a high potential. When the value held in the control memory 153 is “1” (high potential), the NMOS transistor 152 is connected and the PMOS transistor 151 is shut off. In this case, the bias wiring 130 has a low potential. In the description of each embodiment, it is assumed that "0" corresponds to the low potential which is the potential of the ground GND and "1" corresponds to the high potential which is the potential of the power supply VDD.

  That is, the connection of the bias wiring 130 is changed according to the value (potential) held in the control memory 153. That is, in accordance with the value (potential) held in the control memory 153, the bias wiring 130 is electrically connected to either the power supply or the ground. As a result, the potential of the bias wiring 130 is either high or low.

  The configuration of the selection circuit 150 described above is an example, and circuits with other configurations may be used. The selection circuit 150 may be capable of control such that the bias wiring 130 and either the power supply or the ground are electrically connected. Also, the NMOS transistor 152 may be provided between the power supply VDD and the bias wiring 130, and the PMOS transistor 151 may be provided between the bias wiring 130 and the ground GND. Instead of each of the PMOS transistor 151 and the NMOS transistor 152, another element or the like that functions as a switch that connects the bias wiring 130 and either the power supply or the ground may be used. Further, the configuration of the circuit of the control memory 153 is not particularly limited. As long as control is possible such that one of the PMOS transistor 151 and the NMOS transistor 152 is electrically connected, a circuit having a configuration different from that of the memory may be used as the control memory 153. An example of the circuit of the control memory 153 will be described later.

(Operation of integrated circuit 100)
Subsequently, the operation of the selection circuit 150 will be mainly described with respect to the operation and the like of the integrated circuit 100 in the present embodiment. In the following description, as necessary, the operation of the integrated circuit 100 and the circuit in which the bias wiring 130 is directly connected to either the power supply or the ground (ie, a circuit without the circuit corresponding to the selection circuit 150) Compare with the movement etc.

  An example of the crossbar switch circuit which is a comparative example is shown in FIG. In the crossbar switch circuit shown in FIG. 4, each of two input-side wires whose one end is an input and each of three output-side wires whose one end is an output are connected via switches. In the example of FIG. 4, the input terminal is shown as "IN0" or "IN1". The output terminal is shown as "OUT0", "OUT1" or "OUT2". The wirings on the input side correspond to the plurality of first wirings 110 in the integrated circuit 100, and the wirings on the output side correspond to the plurality of second wirings 120 in the integrated circuit 100. Further, a switch connecting the wiring on the input side and the wiring on the output side corresponds to the plurality of switches 140 in the integrated circuit 100. In the example of FIG. 4, for example, a variable resistance element is used as a switch. However, the type of switch is not particularly limited.

  In the crossbar switch circuit shown in FIG. 4, the magnitudes of the switch and wire resistances are not zero. And, due to these resistances, the voltage of the signal from the output may decrease. So, in the example shown in FIG. 4, the buffer is connected to each output terminal. In the example shown in FIG. 4, the buffer is configured by connecting two inverter circuits in series. The buffer prevents the output terminal from outputting an incorrect value due to the voltage drop.

  On the other hand, in the crossbar switch circuit, there are cases where any of the switches connected to the wiring on the output side are turned off (that is, in an open state). In this case, the wiring may be in a floating state and the potential may be unstable.

  Therefore, as shown in FIG. 4, a bias wiring may be provided to the crossbar switch circuit. The bias wiring is connected to either the power supply VDD or the ground GND. That is, the bias wiring is at the potential of either the power supply VDD or the ground GND. Further, the bias wiring is connected to the wiring on the output side via the switch. Then, with respect to the wiring on the output side where all the switches connected to the wiring on the input side are off (open), the switch connected to the bias wiring is turned on (that is, in a closed state). By setting the opening and closing of the switch in this manner, the output of the above-described output side wiring is in either the high potential state or the low potential state. That is, the value of high potential or low potential is input to the buffer. Such an operation avoids the occurrence of the floating state.

  However, in the crossbar switch circuit shown in FIG. 4, leakage current may occur due to the presence of the bias wiring. FIG. 5 shows an example of the case where a leak current occurs.

  In the example shown in FIG. 5, as in the example shown in FIG. 4, each of the two input-side wires whose one end is an input and each of the three output-side wires whose one end is an output are switches. Connected through. In the example of FIG. 5, the input terminal is shown as "IN0" or "IN1". The output terminal is shown as "OUT0", "OUT1" or "OUT2". The wirings on the input side correspond to the plurality of first wirings 110 in the integrated circuit 100, and the wirings on the output side correspond to the plurality of second wirings 120 in the integrated circuit 100. It is assumed that a buffer (not shown) is connected to each of the output terminals. Further, the type of switch is not particularly limited, and is, for example, a variable resistance element.

  FIGS. 5A and 5B are examples in which the bias wiring is connected to the ground GND. In these examples, the bias wiring is at a low potential. Further, in these examples, it is assumed that the switches S01 and S12 are turned on. Therefore, a path from IN0 to OUT0 and a path from IN1 to OUT1 are configured. Moreover, in order to avoid the problem regarding the floating mentioned above, it assumes that switch S20 is turned on. As a result, the output OUT2 has a low potential.

  In this case, it is assumed that the value input from IN0 and IN1 is "1", that is, a high potential. In this case, a potential difference exists between the wiring on the input side and the bias wiring. Therefore, as shown in FIG. 5A, a leak current is generated through the switches S00, S10, S21 and S22 in the off state.

  On the other hand, it is assumed that the value input from IN0 and IN1 is "0", that is, a low potential. In this case, it can be considered that there is no potential difference between the wiring on the input side and the bias wiring. Therefore, as shown in FIG. 5B, no leak current occurs via the switches S00, S10, S21 and S22 in the off state.

  5C and 5D show an example in which the bias wiring is connected to the power supply VDD. In these examples, the bias wiring is at a high potential. Further, in these examples, it is assumed that the switches S01 and S12 are turned on as in the example described above. Therefore, a path from IN0 to OUT0 and a path from IN1 to OUT1 are configured. Moreover, in order to avoid the problem regarding the floating mentioned above, it assumes that switch S20 is turned on. As a result, the output OUT2 has a high potential.

  In this case, it is assumed that the value input from IN0 and IN1 is "1", that is, a high potential. In this case, it can be considered that there is no potential difference between the wiring on the input side and the bias wiring. Therefore, as shown in FIG. 5C, the leakage current does not occur through the switches S00, S10, S21 and S22 in the off state.

  On the other hand, it is assumed that the value input from IN0 and IN1 is "0", that is, a low potential. In this case, a potential difference is generated between the wiring on the input side and the bias wiring. Therefore, as shown in FIG. 5D, a leak current is generated through the switches S00, S10, S21 and S22 in the off state.

  That is, in the crossbar switch circuit shown in FIG. 5, a leak current may occur when there is a potential difference between the wiring on the input side and the bias wiring. More specifically, leakage current may occur when the bias line is connected to the power supply VDD and the input from the line on the input side is "0" (low potential). Also, when the bias wiring is connected to the ground and the input from the wiring on the input side is “1” (high potential), a leak current may occur.

  The integrated circuit 100 according to the present embodiment includes the selection circuit 150 to enable selection of whether the bias wiring 130 is electrically connected to the power supply or the ground as described above. Then, the selection circuit 150 is selected to reduce the possibility of the potential difference between the bias wiring 130 and the plurality of first wirings 110 corresponding to the signal on the input side in the above-described example. It is possible to reduce the current.

  Whether the selection circuit 150 selects the power supply or the ground is determined according to the value of the signal input to the plurality of first wirings 110 forming the crossbar switch, as an example.

  As an example, in the case where the input signal includes many “0s”, the selection circuit 150 selects the bias wiring 130 to be connected to the ground. That is, "1" is held in the control memory 153 of the selection circuit 150. When a large number of “1” s is included in the input signal, the selection circuit 150 selects the bias wiring 130 to be connected to the power supply. That is, "0" is held in the control memory of the selection circuit 150. By determining in this manner, it is possible to reduce the leakage current caused by the bias wiring 130.

(Method of Determining Potential Selected by Selection Circuit 150)
Subsequently, a method of determining whether the power supply or the ground is selected by the selection circuit 150, that is, a method of determining the potential selected by the selection circuit 150 will be described. More specifically, the method of determining the value held in the control memory 153 of the selection circuit 150 will be described.

  In the description of the method of determining which selection circuit 150 selects, it is assumed that integrated circuit 100 is used as routing block 11 included in cell 10 of reconfigurable integrated circuit 1. In this case, for example, together with the generation of the circuit realized by the reconfigurable integrated circuit 1, the value held in the control memory 153 of the selection circuit 150 is determined.

  In this case, values held in the control memory 153 are determined as shown in the flowchart of FIG. 6 as an example. The flowchart shown in FIG. 6 is performed using, for example, a design support tool of one or more circuits.

  First, a file describing a circuit implemented by the reconfigurable integrated circuit 1 is obtained (step S101). In this case, the circuit is described by a hardware description language such as, for example, Verilog-HDL (Hardware Description Language) or VHDL (VHSIC HDL).

  Next, logic synthesis is performed on the file acquired in step S101 by logic synthesis software or the like (step S102). As a result of logic synthesis, a netlist describing connection relationships between circuit elements is generated. In this case, as elements included in the net list, there are LUTs and flip-flops constituting the logic block 11. Also, the net list contains information on the truth value of the LUT contained in the logic block 12.

  Next, the physical arrangement and wiring in the reconfigurable integrated circuit 1 are determined by the placement and routing tool based on the net list generated in step S102 (step S103). That is, the placement and routing tool determines the physical arrangement of the circuit elements described in the netlist in the reconfigurable integrated circuit 1. Also, based on the information of the connection relationship between the circuit elements, the connection between the circuit elements whose physical arrangement has been determined using the resources of the wiring and the switch included in the reconfigurable integrated circuit 1 is determined. Ru. Also, a mapping file is output as the execution result of this step.

  The operations from step S101 to step S103 are performed in the same manner as processing of logic synthesis and placement and routing of a circuit realized by a general FPGA.

  Next, an HDL file used for simulation to be described later is generated (step S104). The HDL file is generated by converting the mapping file output as the execution result of step S103. The generated HDL file contains information on the input terminals of the plurality of first wires 110 constituting the crossbar switch. Also, the generated HDL file is used in the simulation executed in the subsequent step.

  Next, HDL simulation is performed using the HDL generated in the previous step S104 (step S105). HDL simulation is performed by a general HDL simulator.

  Next, using the result in step S105, the probability of occurrence of “0” or “1” included in the values input to the input terminals of the plurality of first wires 110 configuring the crossbar switch circuit Is performed (step S106). That is, the ratio of each of “0” or “1” to the entire value input to the input terminal of the plurality of first wirings 110 is obtained.

  When the reconfigurable integrated circuit 1 includes a plurality of cells 10, the identification of the probability is performed on each input terminal included in the integrated circuit 100 included in the cell 10, for example. Further, as described later, in the case where one selection circuit 150 is provided for a plurality of crossbar switches, identification of probability is performed in units of a plurality of input terminals to be controlled by the selection circuit 150. It will be.

  Finally, it is determined whether the selection circuit 150 selects the power supply or the ground (step S107). That is, the value held in the control memory 153 of the selection circuit 150 is determined.

  For example, when many “0” s are included in the signals input to the input terminals of the plurality of first wirings 110, the selection circuit 150 selects the bias wiring 130 so as to be connected to the ground. That is, it is determined that "1" is held in the control memory 153 of the selection circuit 150. Further, in the case where a large amount of “1” is included in the signals input to the input terminals of the plurality of first wirings 110, the selection circuit 150 selects the bias wiring 130 to be connected to the power supply. That is, it is determined that "0" is held in the control memory 153 of the selection circuit 150.

  FIG. 7 shows an example when it is determined by the selection circuit 150 whether to select the power supply or the ground, that is, when the value held in the control memory 153 is determined. FIG. 7 shows an example of the reconfigurable integrated circuit 1 in which 16 cells 10 of 4 rows horizontally and 4 columns vertically are provided from the cells 10-1 to 10-16. In each of the cells 10-1 to 10-16, it is assumed that the integrated circuit 100 in this embodiment is used as a crossbar switch circuit. That is, in the example shown in FIG. 7, sixteen control memories 153 from control memories 153-1 to 153-16 are provided. Then, the values stored in each of the control memories 153-1 to 153-16 are determined by the above-described procedure.

In the example shown in FIG. 7, the value contained in the value input to the input terminal of the crossbar switch circuit (that is, the input terminal of the plurality of first wires 110) included in each of the cells 10-1 to 10-16 The probability of occurrence of 0 "or" 1 "is described as P ₀ or P ₁ respectively.

In each of the cells 10-1 to 10-16, if the probability that "0" appears in the signal input to each input terminal is larger than the probability that "1" appears, P ₀ > P ₁ is written. Similarly, for each of the cells 10-1 to 10-16, if the probability that "1" appears in the signal input to each input terminal is greater than the probability that "0" appears, It is written that P ₀ <P ₁ .

Then, in the case where the probability of occurrence of “0” or “1” in the cell 10 has a relation of P ₀ > P ₁ , the value stored in the control memory 153 included in the cell 10 is “1”. It becomes. Further, regarding the cell 10, when the probability of occurrence of “0” or “1” is in a relation of P ₀ <P ₁ , the value stored in the control memory 153 included in the cell 10 is “0”. It becomes.

  In the example shown in FIG. 7, the value held in the control memory 153 included in the eleven cells 10 among the sixteen cells 10-1 to 10-16 is “1”. Further, the value held in the control memory 153 included in the remaining five cells 10 among the sixteen cells 10-1 to 10-16 is "0".

(Placement of control memory)
As mentioned above, the reconfigurable integrated circuit 1 shown in FIG. 2 is generally provided with a plurality of cells 10. That is, when the integrated circuit 100 in the present embodiment is used as a routing block included in the cell 10 of the reconfigurable integrated circuit 1, the reconfigurable integrated circuit 1 includes a plurality of integrated circuits 100. In this case, as in the example of FIG. 7 described above, the control memory 153 of the selection circuit 150 is provided for each of the plurality of integrated circuits 100.

  In the example shown in FIG. 7, when the control memory 153 is provided in each of the cells 10, the values held in the control memory 153 in response to the inputs to the respective crossbar switches constituting the routing block 11 of the cell 10. Is determined. That is, the potential of the bias wiring 130 is determined in accordance with the input to each crossbar switch. Therefore, the reduction effect of the leak current is increased. However, in the example shown in FIG. 7, each cell 10 is provided with the control memory 153. Therefore, the control memory 153 may be overhead in terms of area.

  Therefore, various examples different from the example of FIG. 7 are assumed as the arrangement of the control memory 153 of the selection circuit included in the circuit having a plurality of integrated circuits 100. That is, when a plurality of integrated circuits 100 are included, it is assumed that, for example, one control memory 153 is disposed for a plurality of integrated circuits 100.

  An arrangement example of the control memory 153 will be described with reference to FIGS. 8 to 11. In the examples shown in FIGS. 8 to 11, it is assumed that the reconfigurable integrated circuit 1 is configured by arranging 16 cells 10 in an array. In the examples shown in FIG. 8 to FIG. 11, one cell is explicitly shown as an example. Then, it is assumed that the integrated circuit 100 is used as the routing block 11 of the cell 10. That is, elements other than the control memory 153 of the integrated circuit 100 are included in each cell 10. In the examples shown in FIGS. 8 to 11, the number of cells 10 included in the reconfigurable integrated circuit 1 is not particularly limited.

  FIG. 8 shows an example where one control memory 153 is provided for each column of cells 10 included in the reconfigurable integrated circuit 1. That is, in the example shown in FIG. 8, four control memories 153 of control memories 153-1 to 153-4 are provided. The control memories 153-1 to 153-4 correspond to the PMOS transistor 151 and the NMOS transistor 152 of the integrated circuit 100 included in each of the cells 10 to be controlled via each of the selection wirings 154-1 to 154-4. Connected with That is, the PMOS transistor 151 and the NMOS transistor 152 of the integrated circuit 100 included in each of the cells 10 are controlled to open and close based on any value of the control memories 153-1 to 153-4. In this case, each control memory 153 is based on the probability of appearance of “0” or “1” included in the input to the crossbar switch of the cell 10 of each column to be controlled by the control memory 153. The value held in is determined.

  In the example shown in FIG. 8, “0” is held in the control memory 153 provided for the two leftmost or rightmost columns. Also, in this example, “1” is held in the control memory 153 provided for the central two columns.

  FIG. 9 shows an example in which one control memory 153 is provided for each row of cells 10 included in reconfigurable integrated circuit 1. Reconfigurable integrated circuit 1 shown in FIG. 9 has the same configuration as the reconfigurable integrated circuit shown in FIG. 8 except that control cells 153-1 to 153-4 are different in cells 10 to be controlled. Have. That is, the control memories 153-1 to 153-4 are connected to the PMOS transistor 151 and the NMOS transistor 152 included in each of the cells 10 to be controlled via each of the selection wirings 154-1 to 154-4. Connected Also in this case, based on the probability of appearance of “0” or “1” included in the input to the crossbar switch of the cell 10 of each row to be controlled by the control memory 153, the respective Values held in the control memory 153 are determined.

  Further, FIG. 10 shows an example in the case where one control memory 153 is provided for four adjacent cells 10 among the cells 10 included in the reconfigurable integrated circuit 1. Reconfigurable integrated circuit 1 shown in FIG. 10 is the same as the reconfigurable integrated circuit shown in FIG. 8 or FIG. 9 except that cells 10 to be controlled by control memories 153-1 to 153-4 are different. It has the same configuration. That is, the control memories 153-1 to 153-4 are connected to the PMOS transistor 151 and the NMOS transistor 152 included in each of the cells 10 to be controlled via each of the selection wirings 154-1 to 154-4. Connected Also in this case, the control memory 153 is held in each control memory 153 based on the probability of appearance of “0” or “1” contained in the input to the crossbar switch of the cell 10 to be controlled. Value is determined.

  Further, FIG. 11 shows an example in which one control memory 153 is provided for all the cells 10 included in the reconfigurable integrated circuit 1. The control memory 153 is connected to each of the PMOS transistor 151 and the NMOS transistor 152 of the integrated circuit 100 included in each of all the cells 10 included in the reconfigurable integrated circuit 1 through the selection wiring 154. That is, the PMOS transistor 151 and the NMOS transistor 152 of the integrated circuit 100 included in each of all the cells 10 are controlled to open and close based on the value of the control memory 153. In this case, the value held in each control memory 153 is determined based on the probability of occurrence of “0” or “1” included in the input to the crossbar switch included in all the cells 10.

  In the examples shown in FIGS. 8 to 11, assuming that the number of cells 10 included in the reconfigurable integrated circuit 1 is the same, the area required for the control memory 153 is reduced because the number of control memories 153 is reduced. It becomes smaller. On the other hand, as the number of control memories 153 decreases, the effect of reducing the leakage current tends to decrease. That is, the number and arrangement of the control memories 153 are determined according to the trade-off between the reduction of the leak current and the overhead of the area of the control memory 153. Also, the arrangement of the control memory 153 may be different from the example described above.

(Configuration of control memory)
As the control memory 153 of the selection circuit 150 included in the integrated circuit 100, circuits of various configurations are used. FIG. 12 shows a configuration example of the control memory 153.

  In the example shown in FIG. 12 (1), the control memory 153 is composed of two resistance change elements 1531-1 and 1531-2 and a buffer 1532.

  In this example, when resistance change element 1531-1 is turned on (state of small resistance value) and resistance change element 1531-2 is turned off (state of large resistance value), buffer 1532 and ground GND are electrically connected. Connected to In this case, the buffer 1532 holds the value "0". When the variable resistance element 1531-1 is turned off and the variable resistance element 1531-2 is turned on, the buffer 1532 and the power supply VDD are electrically connected. In this case, the buffer 1532 holds the value "1". Then, the value held in the buffer 1532 becomes the value held in the control memory 153.

  By using the circuit having the configuration shown in FIG. 12A, the control memory 153 can be realized with a relatively small area. However, when a defect occurs in which at least one of resistance change elements 1531-1 and 1531-2 is fixed on or off, a defect such as generation of through current or a floating problem with buffer 1532 may occur. .

  In the example shown in FIG. 12 (2), the control memory 153 is composed of a resistance change element 1531, two PMOS transistors 1533-1 and 1533-2, and two NOT gates 1534-1 and 1534-2. . The PMOS transistor 1533-1 is used as a precharge transistor. Further, a feedback loop is formed by the PMOS transistor 1533-2 and the NOT gate 1534-1, and is used as a self holding circuit.

  In this example, by applying a pulse signal to the gate terminal of the PMOS transistor 1533-1, the wiring n1 connecting the PMOS transistor 1533-1 and the NOT gate 1534-1 and the like is precharged. In this case, assuming that resistance change element 1531 is off (in a state where the resistance value is large), interconnection n1 remains at a high potential, and is self-holding composed of PMOS transistor 1533-2 and NOT gate 1534-1. The circuit holds "1". As a result, the output from the NOT gate 1534-2 is "1". This value is the output from the control memory 153.

  On the other hand, assuming that the variable resistance element 1531 is on (in a state where the resistance value is small), the wiring n1 is electrically connected to the ground GND and has a low potential. As a result, the self-holding circuit formed of the PMOS transistor 1533-2 and the NOT gate 1534-1 holds "0". As a result, the output from the NOT gate 1534-2 is "0".

  The circuit of the configuration shown in FIG. 12 (2) may have a larger area due to the increase in the number of transistors as compared with the circuit of the configuration shown in FIG. 12 (1). However, in the circuit of this configuration, even when the resistance change element 1531 is fixed to be turned on or off, problems such as through current and floating are less likely to occur. Therefore, the circuit having the configuration shown in FIG. 12 (2) is a circuit having high stability as compared with the circuit having the configuration shown in FIG. 12 (1).

(Example)
A simulation program with integrated circuit emphasis (HSPICE) simulation was performed on the integrated circuit 100 in the present embodiment.

  In the present embodiment, it is assumed that the switch 140 of the integrated circuit 100 is a variable resistance element, and the integrated circuit 100 is realized by a 65 nm (nanometer) CMOS / resistance variable element hybrid process. Then, the potential applied to the bias wiring 130 is changed according to the ratio of “0” or “1” included in the input to the input terminal of the crossbar switch included in the integrated circuit 100.

  Specifically, when “0” included in the input is 50% or more, the bias wiring 130 is electrically connected to the ground GND, and a low potential is applied. In addition, when “0” included in the input is smaller than 50%, the bias wiring 130 is electrically connected to the power supply VDD, and a high potential is applied.

  The comparative example is realized by the same process as the integrated circuit 100, and it is assumed that the potential applied to the bias wiring 130 is fixed. The comparative example (1) is a case where the bias wiring 130 is fixed at a low potential. Further, Comparative Example (2) is a case where the bias wiring 130 is fixed at a high potential.

  The leakage current in this case is as shown in FIG. In FIG. 13, the horizontal axis shows the proportion of "0" contained in the input to the input terminal of the crossbar switch. The vertical axis shows the magnitude of the leak current.

  As shown in FIG. 13, in the integrated circuit 100 according to the present embodiment, when “0” included in the input is smaller than 50%, the magnitude of the leak current is smaller than that of the comparative example (1). In addition, when “0” included in the input is 50% or more, the integrated circuit 100 in the present embodiment has a smaller magnitude of the leak current than the comparative example (2). That is, it was shown that the leak current can be reduced in the integrated circuit 100 in the present embodiment as compared with the case where the potential applied to the bias wiring 130 is fixed.

  As described above, the integrated circuit 100 in the present embodiment includes the selection circuit 150. The selection circuit 150 enables selection of the potential applied to the bias wiring 130 provided in the crossbar switch which is an element of the integrated circuit 100. That is, control is performed by the selection circuit 150 to select the potential applied to the bias wiring 130 in accordance with the ratio of “0” or “1” included in the input to the input terminal of the crossbar switch. By performing such control, the leak current due to the bias wiring 130 is reduced.

  Therefore, the integrated circuit 100 in this embodiment is an integrated circuit with low power consumption.

  Part or all of the present invention is also expressed as the following appendices, but is not limited to the following.

(Supplementary Note 1)
A plurality of first wires each end of which is used as an input terminal;
A plurality of second wires each having one end used as an output terminal and each connected to each of the first wires;
A bias line connected to each of the second lines and connected to a power supply or a ground;
A plurality of switches connecting the first wiring or the bias wiring and the second wiring;
An integrated circuit comprising: the bias wiring; and a selection circuit that selects an electrical connection with either the power supply or the ground.

(Supplementary Note 2)
The integrated circuit according to claim 1, wherein the switch is a variable resistance element.

(Supplementary Note 3)
The integration according to claim 1 or 2, wherein the selection circuit selects whether the bias wiring is electrically connected to either the power supply or the ground according to a value input to the input terminal. circuit.

(Supplementary Note 4)
The selection circuit electrically connects the bias wiring to the ground when the value input to the input terminal is more than 0, and the bias wiring is connected when the value input to the input terminal is more than 1 15. The integrated circuit of any one of clauses 1 to 3, selected to connect with the power supply.

(Supplementary Note 5)
The selection circuit according to any one of appendices 1 to 4, further comprising: a selection switch electrically connecting the bias wiring and either the power supply or the ground; and a control memory controlling opening / closing of the selection switch. Integrated circuit as described.

(Supplementary Note 6)
10. The integrated circuit according to any one of appendices 1 to 5, wherein the selection switch includes a PMOS transistor connecting the bias wiring and the power supply, and an NMOS transistor connecting the bias wiring and the ground.

(Appendix 7)
The control memory includes a first resistance change element having one end connected to the ground, and a second resistance change element having one end connected to the power supply and the other end connected to the first resistance change element. 15. The integrated circuit according to any one of appendices 1 to 6, further comprising: a buffer connected at one end to a wire connecting the first variable resistance element and the second variable resistance element.

(Supplementary Note 8)
The control memory includes a first PMOS (Metal Oxide Semiconductor) transistor having one end connected to the power supply, and a second PMOS connected at one end to the power supply and the other end connected to the first PMOS transistor. A transistor,
A first NOT gate whose input is connected to a line connecting the first PMOS transistor and the second PMOS transistor, and whose output is connected to the gate terminal of the second PMOS transistor;
A second NOT gate whose input is connected to the output of the first NOT gate;
In any one of Appendices 1 to 6, further including a variable resistance element having one end connected to a wire connecting the first PMOS transistor and the second PMOS transistor and the other end connected to the ground. Integrated circuit as described.

(Appendix 9)
Comprising a plurality of cell circuits arranged in an array;
Each of the plurality of cell circuits is
An integrated circuit according to any one of appendices 1 to 8;
A reconfigurable integrated circuit comprising: a logic block connected to the output terminal of the integrated circuit and having at least a look up table (LUT) and a flip flop.

(Supplementary Note 10)
A plurality of cell circuits and at least one control memory;
Each of the plurality of cell circuits is
A first wire including a plurality of first wires each end of which is used as an input terminal;
A plurality of second wires each having one end used as an output terminal and each connected to each of the first wires;
A bias line connected to each of the second lines and connected to a power supply or a ground;
A plurality of switches connecting the first wiring or the bias wiring and the second wiring;
A selection switch electrically connecting the bias wiring to either the power supply or the ground;
A logic block connected to the output terminal of the integrated circuit and having at least a look up table (LUT) and a flip flop;
Each of the control memories controls the opening and closing of the selection switch included in at least one of the cell circuits.
Reconfigurable integrated circuit.

(Supplementary Note 11)
A determination method for determining whether the selection circuit included in the reconfigurable integrated circuit according to appendix 9 or 10 selects an electrical connection between the bias wiring and the power supply or the ground,
Execute a simulation of the circuit realized by the reconfigurable integrated circuit,
Based on the result of the simulation, the probability of occurrence of 0 or 1 included in the value input to each of the input terminals provided in the reconfigurable integrated circuit is identified,
Determining whether the selection circuit selects an electrical connection with the power supply or the ground based on the identified probability.

  As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to the said embodiment. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. Further, the configurations in each embodiment can be combined with each other without departing from the scope of the present invention.

  This application claims priority based on Japanese Patent Application No. 2016-181942 filed on Sep. 16, 2016, the entire disclosure of which is incorporated herein.

Reference Signs List 1 reconfigurable integrated circuit 10 cell 11 routing block 12 logic block 100 integrated circuit 110 first wiring 120 second wiring 130 bias wiring 140 switch 141 resistance change element 150 selection circuit 151 PMOS transistor 152 NMOS transistor 153 control memory 1531 resistance Variable element 1532 Buffer 1533 PMOS transistor 1534 NOT gate 154 Selection wiring

Claims (11)

A plurality of first wires each end of which is used as an input terminal;
A plurality of second wires each having one end used as an output terminal and each connected to each of the first wires;
A bias line connected to each of the second lines and connected to a power supply or a ground;
A plurality of switches connecting the first wiring or the bias wiring to the second wiring;
An integrated circuit comprising: the bias wiring; and a selection circuit that selects an electrical connection with either the power supply or the ground.   The integrated circuit according to claim 1, wherein the switch is a variable resistance element.   The selection circuit according to claim 1 or 2, wherein the selection circuit selects whether the bias wiring is electrically connected to the power supply or the ground according to a value input to the input terminal. Integrated circuit.   The selection circuit electrically connects the bias wiring to the ground when the value input to the input terminal is more than 0, and the bias wiring is connected when the value input to the input terminal is more than 1 The integrated circuit according to any one of claims 1 to 3, which is selected to connect to the power supply.   The selection circuit according to any one of claims 1 to 4, further comprising: a selection switch electrically connecting the bias wiring to either the power supply or the ground; and a control memory controlling opening / closing of the selection switch. Integrated circuit as described in.   The integrated circuit according to any one of claims 1 to 5, wherein the selection switch has a PMOS transistor connecting the bias wiring and the power supply, and an NMOS transistor connecting the bias wiring and the ground. .   The control memory includes a first resistance change element having one end connected to the ground, and a second resistance change element having one end connected to the power supply and the other end connected to the first resistance change element. The integrated circuit according to any one of claims 1 to 6, further comprising: a buffer connected at one end to a wire connecting the first variable resistance element and the second variable resistance element. The control memory includes a first PMOS (Metal Oxide Semiconductor) transistor having one end connected to the power supply, and a second PMOS connected at one end to the power supply and the other end connected to the first PMOS transistor. A transistor,
A first NOT gate whose input is connected to a line connecting the first PMOS transistor and the second PMOS transistor, and whose output is connected to the gate terminal of the second PMOS transistor;
A second NOT gate whose input is connected to the output of the first NOT gate;
The resistance change element according to any one of claims 1 to 6, further comprising: a resistance change element having one end connected to a wire connecting the first PMOS transistor and the second PMOS transistor and the other end connected to the ground. Integrated circuit as described in. Comprising a plurality of cell circuits arranged in an array;
Each of the plurality of cell circuits is
An integrated circuit according to any one of claims 1 to 8;
A reconfigurable integrated circuit comprising: a logic block connected to the output terminal of the integrated circuit and having at least a look up table (LUT) and a flip flop. A plurality of cell circuits and at least one control memory;
Each of the plurality of cell circuits is
A first wire including a plurality of first wires each end of which is used as an input terminal;
A plurality of second wires each having one end used as an output terminal and each connected to each of the first wires;
A bias line connected to each of the second lines and connected to a power supply or a ground;
A plurality of switches connecting the first wiring or the bias wiring to the second wiring;
A selection switch electrically connecting the bias wiring to either the power supply or the ground;
A logic block connected to the output terminal of the integrated circuit and having at least a look up table (LUT) and a flip flop;
Each of the control memories controls the opening and closing of the selection switch included in at least one of the cell circuits.
Reconfigurable integrated circuit. A method of determining whether the selection circuit provided in the reconfigurable integrated circuit according to claim 9 or 10 selects an electrical connection between the bias wiring and the power supply or the ground.
Execute a simulation of the circuit realized by the reconfigurable integrated circuit,
Based on the result of the simulation, the probability of occurrence of 0 or 1 included in the value input to each of the input terminals provided in the reconfigurable integrated circuit is identified,
Determining whether the selection circuit selects an electrical connection with the power supply or the ground based on the identified probability.

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