JPWO2016020802A1 - Semiconductor device, conversion circuit and electronic device - Google Patents

Abstract

An object is to provide a novel semiconductor device, a semiconductor device capable of reducing power consumption, a semiconductor device capable of high-speed operation, or a semiconductor device capable of reducing the area. A first power storage circuit, a second power storage circuit, a first switch, and a second switch, wherein a conduction state of the first switch is controlled by the first signal; The conduction state of the switch is controlled by the second signal, the function of outputting the first potential from the first power storage circuit via the first switch, and the second switch from the second power storage circuit. The third potential is output via the second switch from the function of outputting the second potential through the first power storage circuit and the second power storage circuit connected in series.

Description

One embodiment of the present invention relates to a semiconductor device, a conversion circuit, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

As a circuit that converts a signal in an electronic device, a circuit that converts a digital signal into an analog signal (DA conversion circuit) and a circuit that converts an analog signal into a digital signal (AD conversion circuit) are widely used. Further, binary type and decoder type are known as DA conversion circuits.

When signal conversion is performed using a DA conversion circuit or an AD conversion circuit, it is necessary to generate a reference potential. For example, in a binary type or decoder type DA converter circuit, a method of generating a reference potential using a resistance element is used. Patent Document 1 describes a DA conversion circuit that generates a reference voltage using a plurality of resistance elements connected in series.

JP 2009-288526 A

When a reference potential is generated using a resistance element, current always flows through the resistance element, so that power consumption in the conversion circuit increases. In addition, when a reference potential is generated using a capacitor in a binary DA converter circuit or the like, a predetermined time is required to charge the capacitor, and the operation speed of the converter circuit is reduced.

In view of the above technical background, an object of one embodiment of the present invention is to provide a novel semiconductor device or a conversion circuit. Another object of one embodiment of the present invention is to provide a semiconductor device or a conversion circuit that can reduce power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or a conversion circuit that can operate at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device or a conversion circuit whose area can be reduced.

Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other issues from the description of the specification, drawings, claims, etc. .

A semiconductor device according to one embodiment of the present invention includes a first power storage circuit, a second power storage circuit, a first switch, and a second switch, and the conduction state of the first switch is: The conduction state of the second switch controlled by the first signal is controlled by the second signal, and outputs a first potential from the first power storage circuit via the first switch; The function of outputting the second potential from the second power storage circuit via the second switch, and the third power from the first power storage circuit and the second power storage circuit connected in series via the second switch. It has a function of outputting the potential.

Furthermore, in the semiconductor device according to one embodiment of the present invention, the first power storage circuit or the second power storage circuit may include a plurality of batteries, and the plurality of batteries may be connected in series.

Furthermore, in the semiconductor device according to one embodiment of the present invention, the first power storage circuit or the second power storage circuit includes a plurality of batteries and a third switch, and the third switch includes a plurality of batteries. The plurality of batteries are connected in series via a third switch, and the third switch may be a transistor including an oxide semiconductor in a channel formation region.

Further, in the semiconductor device according to one embodiment of the present invention, the plurality of batteries may be provided above the transistor.

Furthermore, in the semiconductor device according to one embodiment of the present invention, the charging of the plurality of batteries is performed by connecting the plurality of batteries in parallel, then applying the fourth potential to the first electrodes of the plurality of batteries, and Alternatively, the fifth potential may be supplied to each of the two electrodes.

A conversion circuit according to one embodiment of the present invention may include the above semiconductor device.

Further, an electronic device according to one embodiment of the present invention may include the semiconductor device or the conversion circuit, and a display device, a speaker, or a microphone.

According to one embodiment of the present invention, a novel semiconductor device or a conversion circuit can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a conversion circuit capable of reducing power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a conversion circuit capable of high-speed operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a conversion circuit whose area can be reduced can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

6A and 6B illustrate an example of a structure of a semiconductor device. 6A and 6B illustrate an example of a structure of a semiconductor device. FIG. 10 is a circuit diagram illustrating an example of a structure of a semiconductor device. FIG. 10 is a circuit diagram illustrating an example of a structure of a semiconductor device. 6A and 6B illustrate an example of a structure of a semiconductor device. FIG. 10 is a circuit diagram illustrating an example of a structure of a semiconductor device. FIG. 6 illustrates an example of a structure of an AD conversion circuit. FIG. 6 illustrates an example of a configuration of a phase synchronization circuit. FIG. 6 illustrates an example of a structure of a storage device. The figure explaining an example of a structure of a column selection driver. 6A and 6B illustrate an example of a structure of a semiconductor device. 6A and 6B illustrate an example of a structure of a semiconductor device. 6A and 6B illustrate an example of a structure of a semiconductor device. 6A and 6B illustrate an example of a structure of a semiconductor device. The figure explaining an example of a structure of a battery. The figure explaining an example of a structure of a battery. The figure explaining an example of a structure of a battery. The figure explaining an example of a structure of a battery. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

One embodiment of the present invention includes, in addition to the conversion circuit, any device including an RF (Radio Frequency) tag, a display device, an imaging device, and an integrated circuit. In addition, the display device includes a liquid crystal display device, a light-emitting device including a light-emitting element typified by an organic light-emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) including an integrated circuit such as Display) is included in the category.

Note that in describing the structure of the invention with reference to the drawings, the same reference numerals may be used in common in different drawings.

Further, in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, drawings or texts in which one or more active elements (transistors, etc.), wiring, passive elements (capacitance elements, etc.), conductive layers, insulating layers, semiconductor layers, components, devices, operating methods, manufacturing methods, etc. are described. In the above, it is possible to take out a part thereof to constitute one embodiment of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, some elements are arbitrarily extracted from a sentence that states that “A has B, C, D, E, or F”, and “A is B and E. , “A has E and F”, “A has C, E and F”, or “A has B, C, D and E” It is possible to constitute one aspect.

Further, in this specification and the like, when at least one specific example is described in a diagram or text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. To be understood. Therefore, in the case where at least one specific example is described in a drawing or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. One embodiment of the invention is clear.

Further, in this specification and the like, at least the contents described in the drawings (may be part of the drawings) are disclosed as one embodiment of the invention and can constitute one embodiment of the invention. It is. Therefore, if a certain content is described in the figure, even if it is not described using sentences, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention. Is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. And it can be said that one aspect of the invention is clear.

In addition, it is possible to constitute one aspect of the invention that stipulates that the contents not specified in the text and drawings in the specification are excluded. Or, when a numerical value range indicated by an upper limit value and a lower limit value is described for a certain value, the range is unified by arbitrarily narrowing the range or by removing one point in the range. One aspect of the invention excluding a part can be defined. Thus, for example, it can be defined that the prior art does not fall within the technical scope of one embodiment of the present invention.

Further, in this specification and the like, those skilled in the art will understand that the present invention can be applied to any terminal of an active element (such as a transistor) and passive element (such as a capacitor) without specifying the connection destination. It may be possible to configure aspects. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when there are a plurality of terminal connection destination candidates, it is not necessary to limit the terminal connection destination to a specific location. Therefore, it may be possible to configure one embodiment of the invention by specifying the connection destination of only some terminals of an active element (such as a transistor) and a passive element (such as a capacitor).

Further, in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection destination of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.

Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is connected to the fourth electrical path. There is no path, and the fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. Can be expressed. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

(Embodiment 1)
In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described. Specifically, a configuration example of a semiconductor device including a plurality of batteries and usable as a DA conversion circuit will be described.

FIG. 1 illustrates a configuration example of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a plurality of power storage circuits 20 and a plurality of switches S. Note that FIG. 1 illustrates a configuration in which the semiconductor device 10 includes three power storage circuits 20 (power storage circuits 20_1 to 20_3) and three switches S (switches S1 to S3). Is not limited to this, and can be an arbitrary number (n (n is a natural number)).

The power storage circuit 20 is a circuit having a function of accumulating charges. The power storage circuit 20 has a battery 21. The battery 21 is a secondary battery that can recover the continuous use time by charging. The battery 21 may be connected to a circuit for performing wireless charging, a regulator for always keeping a voltage or current input to the battery 21 constant, and the like. In addition to the battery 21, the power storage circuit 20 may include other elements such as a switch and a capacitor. Note that the plurality of batteries 21 included in each power storage circuit 20 can be manufactured in the same process.

The number of batteries 21 provided in the power storage circuit 20 can be freely set. Further, the number of the batteries 21 may be different in each power storage circuit 20. Here, as an example, a structure is shown in which one battery 21 is provided in the power storage circuit 20_1, two batteries 21 are provided in the power storage circuit 20_2, and four batteries 21 are provided in the power storage circuit 20_3.

In the power storage circuit 20 provided with a plurality of batteries 21, the batteries 21 are connected in series. In FIG. 1, two batteries 21 included in the power storage circuit 20_2 and four batteries 21 included in the power storage circuit 20_3 are connected in series. Therefore, the voltage V2 between both terminals of the power storage circuit 20_2 is twice the voltage V1 between both terminals of the power storage circuit 20_1, and the voltage V3 between both terminals of the power storage circuit 20_3 is four times V1. Therefore, the power storage circuits 20_1 to 20_3 each have a function of outputting different potentials depending on the number of the batteries 21.

The first terminal of the switch S1 is connected to the power supply line, the second terminal is connected to the first terminal of the power storage circuit 20_1, and the third terminal is the first terminal of the switch S2 and the second terminal of the power storage circuit 20_2. Is connected to the terminal. The first terminal of the switch S2 is connected to the third terminal of the switch S1, the second terminal is connected to the first terminal of the power storage circuit 20_2, and the third terminal is connected to the first terminal and the power storage of the switch S3. The second terminal of the circuit 20_3 is connected. The first terminal of the switch S3 is connected to the third terminal of the switch S2, the second terminal is connected to the first terminal of the power storage circuit 20_3, and the third terminal is connected to the terminal OUT. The second terminal of the power storage circuit 20_1 is connected to the power supply line. Note that the power supply line is a wiring having a function of transmitting a predetermined potential, and may be a high potential power supply line or a low potential power supply line. Here, a ground line which is a low potential power line is used as the power line.

When four or more power storage circuits 20 and switches S are provided, the fourth and subsequent power storage circuits 20 and switches S may be installed between the switch S3 and the terminal OUT in the same connection relationship as described above. .

The switch S1 has a function of controlling conduction / non-conduction between the storage circuit 20_1 and the storage circuit 20_2, and the switch S2 has a function of controlling conduction / non-conduction between the storage circuit 20_2 and the storage circuit 20_3. The switch S3 has a function of controlling conduction / non-conduction between the power storage circuit 20_3 and the terminal OUT. The conduction states of the switches S1 to S3 are controlled by a digital signal Vdata (Vdata1 to Vdata3) input from the outside.

FIG. 2 shows an example of the operation of the semiconductor device 10. Here, an example in which a 3-bit digital signal (Vdata1 to Vdata3) is input to the semiconductor device 10 will be described. In this case, the conduction state of the switch S1 is controlled by Vdata1, the conduction state of the switch S2 is controlled by Vdata2, and the conduction state of the switch S3 is controlled by Vdata3.

First, FIG. 2A shows a configuration when a 3-bit digital signal “000” (Vdata1 = Vdata2 = Vdata3 = “0”) is input. When “0” (low level signal) is input to the switch S1, the switch S1 operates so that the first terminal of the power storage circuit 20_1 and the second terminal of the power storage circuit 20_2 are in a non-conductive state. The line and the first terminal of the switch S2 become conductive. Further, when “0” (low level signal) is input to the switch S2, the switch S2 operates so that the first terminal of the power storage circuit 20_2 and the second terminal of the power storage circuit 20_3 are in a non-conduction state. The first terminal of the switch S2 and the first terminal of the switch S3 become conductive. In addition, when “0” (a low-level signal) is input to the switch S3, the switch S3 operates so that the first terminal of the power storage circuit 20_3 and the terminal OUT are in a non-conductive state, and the first switch S3 The terminal and the terminal OUT become conductive. Therefore, the output potential Vout = 0 (the potential of the ground line) is output to the terminal OUT. As described above, when the data input to the switch S is “0”, the potential is not supplied from the power storage circuit 20 to the terminal OUT.

Next, FIG. 2B shows a configuration when a 3-bit digital signal “111” (Vdata1 = Vdata2 = Vdata3 = “1”) is input. When “1” (a high-level signal) is input to the switch S1, the switch S1 operates so that the first terminal of the power storage circuit 20_1 and the second terminal of the power storage circuit 20_2 are in a conductive state. 20_1 and power storage circuit 20_2 are connected in series. Further, when “1” (a high level signal) is input to the switch S2, the switch S2 operates so that the first terminal of the power storage circuit 20_2 and the second terminal of the power storage circuit 20_3 are in a conductive state. The power storage circuit 20_2 and the power storage circuit 20_3 are connected in series. Further, when “1” (a high-level signal) is input to the switch S3, the switch S3 operates so that the first terminal of the power storage circuit 20_3 and the terminal OUT are brought into conduction. Therefore, the output potential Vout = V1 + V2 + V3 is output to the terminal OUT. As described above, when the data input to the switch S is “1”, the potential is supplied from the power storage circuit 20 to the terminal OUT.

Further, even when Vdata is other than “000” and “111”, the output potential Vout corresponding to Vdata is output to the terminal OUT. For example, when “010” is input as Vdata, Vout = V2. When “101” is input as Vdata, the power storage circuit 20_1 and the power storage circuit 20_3 are connected in series, and Vout = V1 + V3. As described above, the semiconductor device 10 illustrated in FIG. 2 can output eight potentials to the terminal OUT in accordance with Vdata1 to Vdata3 input to the switches S1 to S3. That is, a 3-bit digital signal can be converted into an analog signal. Therefore, the semiconductor device 10 can be used as a DA conversion circuit.

Note that although an example in which a 3-bit digital signal is input is shown in FIG. 2, a configuration in which a 4-bit or more digital signal is input may be employed. For example, in the case of converting an n-bit digital signal to an analog signal, n power storage circuits 20 (power storage circuits 20_1 to 20_n) and n switches S (S1 to Sn) are provided, and the power storage circuit 20_k (k is 1). (Natural number satisfying ≦ k ≦ n) may be provided with 2 ^k−1 batteries 21 connected in series.

As described above, in one embodiment of the present invention, a plurality of different potentials can be generated depending on the number of the batteries 21 included in the power storage circuit 20. In addition, the series connection of the storage circuits 20 can be controlled based on a digital signal input from the outside, and the digital signal can be converted into an analog signal.

Next, a more specific structural example of the semiconductor device according to one embodiment of the present invention is described. FIG. 3A illustrates a configuration of a semiconductor device 11 which is a configuration example of the semiconductor device 10. The configurations other than those described below are the same as those of the semiconductor device 10 in FIG. In addition, here, a configuration example in which three power storage circuits 20 and three switches S are provided as in FIG. 1 is shown, but the number of power storage circuits 20 and switches S is not limited to this.

The power storage circuit 20_1 includes a battery 21 and a switch 51. The first terminal of the switch 51 is connected to the first electrode of the battery 21, and the second terminal is connected to a power supply line (here, a ground line).

The power storage circuit 20_2 includes the first and second batteries 21, the switch 31, the switch 32, the switch 41, the switch 42, and the first and second switches 51. The first terminal of the switch 31 is connected to the first electrode of the first battery 21, and the second terminal is connected to the third terminal of the switch S1. The first terminal of the switch 32 is connected to the first electrode of the second battery 21, and the second terminal is connected to the first terminal of the switch 42. The first terminal of the switch 41 is connected to the second terminal of the switch S 1, and the second terminal is connected to the second electrode of the first battery 21. The first terminal of the switch 42 is connected to the second terminal of the switch 41, and the second terminal is connected to the second electrode of the second battery 21 and the second terminal of the switch S2. The first terminal of the first switch 51 is connected to the first electrode of the first battery 21, and the second terminal is connected to a power supply line (here, a ground line). The first terminal of the second switch 51 is connected to the first electrode of the second battery 21, and the second terminal is connected to a power supply line (here, a ground line).

The power storage circuit 20_3 includes first to fourth batteries 21, switches 33 to 36, switches 43 to 46, and first to fourth switches 51. The first terminal of the switch 33 is connected to the first electrode of the first battery 21, and the second terminal is connected to the third terminal of the switch S2. The first terminal of the switch 34 is connected to the first electrode of the second battery 21, and the second terminal is connected to the first terminal of the switch 44. The first terminal of the switch 35 is connected to the first electrode of the third battery 21, and the second terminal is connected to the first terminal of the switch 45. The first terminal of the switch 36 is connected to the first electrode of the fourth battery 21, and the second terminal is connected to the first terminal of the switch 46. The first terminal of the switch 43 is connected to the second terminal of the switch S <b> 2, and the second terminal is connected to the second electrode of the first battery 21. The first terminal of the switch 44 is connected to the second terminal of the switch 43, and the second terminal is connected to the second electrode of the second battery 21. The first terminal of the switch 45 is connected to the second terminal of the switch 44, and the second terminal is connected to the second electrode of the third battery 21. The first terminal of the switch 46 is connected to the second terminal of the switch 45, and the second terminal is connected to the second electrode of the fourth battery 21 and the second terminal of the switch S3. The first terminal of the first switch 51 is connected to the first electrode of the first battery 21, and the second terminal is connected to a power supply line (here, a ground line). The first terminal of the second switch 51 is connected to the first electrode of the second battery 21, and the second terminal is connected to a power supply line (here, a ground line). The first terminal of the third switch 51 is connected to the first electrode of the third battery 21, and the second terminal is connected to a power supply line (here, a ground line). The first terminal of the fourth switch 51 is connected to the first electrode of the fourth battery 21, and the second terminal is connected to a power supply line (here, a ground line).

The conduction states of the switches 31 and 32 are controlled by Vdata2, and the conduction states of the switches 33 to 36 are controlled by Vdata3. When the switches 31 and 32 are conductive, the two batteries 21 are connected in series in the power storage circuit 20_2, and when the switches 33 to 36 are conductive, the four batteries 21 are connected in series in the power storage circuit 20_3. .

The conduction states of the switches 41 to 46 and 51 are controlled by the potential Vcc supplied to the terminal CC. When the switches 41 to 46 are turned on, the potential Vc supplied to the terminal C is supplied to the second electrode of the battery 21. When the switch 51 is turned on, the potential of the power line connected to the switch 51 is supplied to the first electrode of the battery 21. Therefore, a predetermined voltage is applied between the first electrode and the second electrode of the battery 21, and the battery 21 is charged.

The switches 31 to 36, 41 to 46, and 51 can be configured using transistors or the like. There is no particular limitation on the material or structure of the transistor that can be used as the switches 31 to 36, 41 to 46, and 51; in particular, a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an OS transistor) is used. preferable.

Since an oxide semiconductor has a wider band gap and lower intrinsic carrier density than other semiconductors such as silicon, the off-state current of an OS transistor is extremely small. Therefore, by using an OS transistor, a semiconductor device that can hold charge for a long time can be formed.

Note that in this specification, unless otherwise specified, off-state current refers to drain current when a transistor is in a non-conduction state (also referred to as an off state or a cut-off state). Unless otherwise specified, the non-conducting state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage between the gate and the source in the p-channel transistor. A state in which Vgs is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification, the off-state current of a transistor having the channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. There may be a case where there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V There is a value of Vgs at which the off-state current of the transistor is less than or equal to Vds at which Vds guarantees the reliability of the semiconductor device including the transistor or Vds used in the semiconductor device or the like including the transistor. May be pointed to.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In this specification, the term “leakage current” may be used to mean the same as off-state current.

In this specification, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

FIG. 3B illustrates a structure in which transistors 31a, 41a, and 51a are used as the switches 31, 41, and 51, respectively. In the figure, a transistor with the symbol “OS” indicates an OS transistor. Note that, here, a configuration in which all of the switches 31, 41, and 51 are OS transistors is shown, but any one or only two of the switches 31, 41, and 51 may be OS transistors. Similarly, the switches 32 to 36 and 42 to 46 illustrated in FIG. 3A can also be formed using OS transistors. Similarly, the switches S1 to S3 can be configured by OS transistors.

One of the source and the drain of the transistor 31a is connected to the first electrode of the battery 21, one of the source and the drain of the transistor 41a is connected to the second electrode of the battery 21, and one of the source and the drain of the transistor 51a is the battery. 21 is connected to the first electrode. Vdata is input to the gate of the transistor 31a, and the potential Vcc supplied from the terminal CC is input to the gate of the transistor 41a and the gate of the transistor 51a.

Here, since the off-state current of the OS transistor is extremely small, the transistor 31a, the transistor 41a, or the transistor 51a is formed of the OS transistor, so that the battery 21 can Leakage of charges accumulated in the first electrode or the second electrode can be suppressed extremely small.

Further, when all of the switches 31 to 36, 41 to 46, and 51 are OS transistors, the switches included in the semiconductor device 10 can be manufactured in the same process, so that the number of processes can be reduced.

Note that transistors used as the switches 31 to 36, 41 to 46, and 51 are not limited to OS transistors. For example, a transistor in which a channel formation region is formed in part of a substrate including a single crystal semiconductor can be used. As the substrate having a single crystal semiconductor, a single crystal silicon substrate, a single crystal germanium substrate, or the like can be used. Since a transistor including a single crystal semiconductor in a channel formation region has high current supply capability, the operation speed of the semiconductor device 10 is improved by forming the switches 31 to 36, 41 to 46, and 51 using such a transistor. be able to.

The transistors used as the switches 31 to 36, 41 to 46, and 51 can also be formed using transistors other than OS transistors in which a channel formation region is formed in a semiconductor film. For example, a transistor including a non-single-crystal semiconductor in a channel formation region can be used. As the non-single-crystal semiconductor, non-single-crystal silicon such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon, or non-single-crystal germanium such as amorphous germanium, microcrystalline germanium, or polycrystalline germanium may be used. it can.

FIG. 3C shows a configuration example of the switch S1. The switch S1 includes a transistor 52 and a transistor 53. Here, the transistor 52 is a p-channel transistor and the transistor 53 is an n-channel transistor.

Vdata is input to the gate of the transistor 52 and the gate of the transistor 53. When “0” (low level) is input as Vdata, the transistor 52 is turned on, and the power supply line and the switch 31 are turned on. On the other hand, when “1” (high level) is input as Vdata, the transistor 53 is turned on, and the battery 21 and the switch 31 are turned on.

As the transistors 52 and 53, transistors similar to the switches 31 to 36, 41 to 46, and 51 can be used. Although the switch S1 includes a p-channel transistor and an n-channel transistor here, all the transistors included in the switch S1 may have the same polarity.

Note that the structure illustrated in FIG. 3C can also be used for the switches S2 and S3.

Next, an example of the operation of the semiconductor device 11 is shown in FIG. 4A shows a configuration when a digital signal “000” is input, FIG. 4B shows a configuration when a digital signal “111” is input, and FIG. In this configuration, the battery 21 is charged.

In FIG. 4A, the switches 41 to 46 and 51 are turned off by the potential Vcc supplied from the terminal CC. Here, when “0” (low level signal) is input as Vdata1 to Vdata3, the first terminal and the third terminal of the switches S1 to S3 are brought into conduction. As a result, the terminal OUT and the power supply line connected to the first terminal of the switch S1 become conductive, and the analog signal Vout = 0V corresponding to the digital signal “000” is output to the terminal OUT. The switches 31 and 32 are controlled to be non-conductive by Vdata2, and the switches 33 to 36 are controlled to be non-conductive by Vdata3.

On the other hand, as shown in FIG. 4B, when “1” (high-level signal) is input as Vdata1 to Vdata3, the third terminals and the second terminals of the switches S1 to S3 become conductive. . Accordingly, the storage circuits 20_1 to 20_3 are connected in series. The switches 31 and 32 are controlled to be in a conductive state by Vdata2, and the switches 33 to 36 are controlled to be in a conductive state by Vdata3. Accordingly, the batteries 21 included in the power storage circuits 20_1 to 20_3 are connected in series. Therefore, the analog signal Vout = V1 + V2 + V3 corresponding to the digital signal “111” is output to the terminal OUT.

Further, even when Vdata is other than “000” and “111”, the output potential Vout corresponding to Vdata is output to the terminal OUT. For example, when “010” is input as Vdata, the battery 21 included in the power storage circuit 20_2 is connected in series and Vout = V2. When “101” is input as Vdata, the power storage circuit 20_1 and the power storage circuit 20_3 are connected in series, and the battery 21 included in the power storage circuit 20_1 and the battery 21 included in the power storage circuit 20_3 are connected in series. Vout = V1 + V3. Therefore, by using the semiconductor device 11, a 3-bit digital signal can be converted into an analog signal.

Further, when the battery 21 is charged, as shown in FIG. 4C, the potential Vcc is supplied from the terminal CC, and the switches 41 to 46 and 51 are turned on. Thereby, the first electrode of the battery 21 is connected to the power supply line (ground line), and the second electrode is connected to the terminal C. That is, the batteries 21 included in the power storage circuits 20_1 to 20_3 are connected in parallel. Then, by supplying a high-level potential Vc from the terminal C, a voltage can be applied between the first electrode and the second electrode of the battery 21 to charge the battery 21. In this way, by connecting all the batteries 21 in parallel and charging them in a batch, the batteries 21 can be charged at high speed. Therefore, the operation speed of the semiconductor device 11 can be improved.

Note that when the battery 21 is charged, it is preferable that the switches S1 to S3 have the first terminal and the third terminal in a conductive state. Accordingly, the terminal OUT and the power supply line are brought into conduction, and the potential of the wiring connected to the terminal OUT is fixed. Therefore, the influence on the other elements and the wiring due to the fluctuation of the potential of the wiring connected to the terminal OUT can be suppressed.

As described above, in one embodiment of the present invention, a plurality of potentials can be generated using batteries connected in series. Therefore, when a predetermined potential is generated, unnecessary current can be prevented from flowing as in the case of using a resistance element, and power consumption can be reduced. In addition, by using an OS transistor as a switch connected to the battery, leakage of charges accumulated in the battery can be suppressed to be extremely small, and power consumption can be further reduced.

In one embodiment of the present invention, a plurality of batteries can be charged at once by connecting the batteries in parallel. Accordingly, the period for charging the battery can be shortened, and the operation speed of the semiconductor device can be improved.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments. Therefore, the contents described in this embodiment (may be a part of contents) may be different from the contents described in the embodiment (may be a part of contents) and / or one or more other contents. Application, combination, replacement, or the like can be performed on the contents described in the embodiment (may be part of the contents). Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment. In addition, a drawing (or a part) described in one embodiment may include another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment. The same applies to the following embodiments.

(Embodiment 2)
In this embodiment, another example of the structure of the semiconductor device according to one embodiment of the present invention will be described. Specifically, a configuration example of a semiconductor device that includes a plurality of batteries and can be used as an AD conversion circuit will be described.

FIG. 5 illustrates a configuration example of the semiconductor device 60 according to one embodiment of the present invention.

The semiconductor device 60 includes a plurality of batteries 21, a plurality of comparators 101, and an encoder 102. Note that, here, a configuration in which seven batteries 21 and seven comparators 101 are provided is shown, but the number of the batteries 21 and the comparators 101 is not limited thereto.

The plurality of batteries 21 are connected in series, and the potentials of the nodes N1 to N7 connected to the battery 21 are determined according to the capacity of the battery 21. Note that a high-level potential Vc is supplied to the terminal C, and the potentials of the nodes N1 to N7 become higher as they are closer to the terminal C. Then, the potentials of the nodes N1 to N7 are output to the comparator 101 as reference potentials Vref1 to Vref7, respectively. Thus, a plurality of reference potentials can be generated using the battery 21 connected in series. In this case, it is possible to prevent generation of unnecessary current that may occur when a reference potential is generated using a resistance element. Therefore, the power consumption of the semiconductor device 60 can be reduced.

The comparator 101 has a function of comparing the magnitude of Va, which is an analog signal, with the reference potentials Vref1 to Vref7 and determining the magnitude of Va. Specifically, Va and any one of the reference potentials Vref1 to Vref7 are input to the plurality of comparators 101, and Va and the reference potential are compared in magnitude. A high level or low level signal corresponding to the comparison result is output from the comparator 101. In this way, the potential of Va is determined by comparing the magnitudes of Va and all the reference potentials Vref1 to Vref7. Here, since seven types of reference potentials Vref1 to Vref7 are compared in magnitude, 8-value Va can be determined.

The encoder 102 is a circuit having a function of generating a multi-bit digital signal based on signals output from the plurality of comparators 101 and outputting the digital signal to a terminal OUT. Specifically, it has a function of generating a digital signal by performing encoding based on a high level or low level signal output from each of the plurality of comparators 101. Since the semiconductor device 60 includes the encoder 102, the analog signal Va can be converted into digital value data. Therefore, the semiconductor device 60 can be used as an AD conversion circuit.

Next, a specific configuration example of the semiconductor device 60 will be described. FIG. 6 illustrates a configuration of a semiconductor device 61 that is a configuration example of the semiconductor device 60. The configurations other than those described below are the same as those of the semiconductor device 60 in FIG. In addition, here, a configuration in which seven batteries 21 and seven comparators 101 are provided is shown, but the number of the batteries 21 and comparators 101 is not limited to this.

The semiconductor device 61 includes a plurality of batteries 21, a plurality of switches 71, a plurality of switches 72, and a plurality of switches 73.

The switch 71 is provided between two adjacent batteries 21. That is, the first terminal of the switch 71 is connected to one first electrode of the adjacent battery 21, and the second terminal is connected to the other second electrode of the adjacent battery 21. The switch 71 has a function of controlling the conduction state of the adjacent batteries 21.

The first terminal of the switch 72 is connected to the second electrode of the battery 21, and the second terminal is connected to the terminal C. The switch 72 has a function of controlling whether or not the potential Vc of the terminal C is supplied to the second electrode of the battery 21.

The first terminal of the switch 73 is connected to the first electrode of the battery 21, and the second terminal is connected to a power supply line (here, a ground line). The switch 73 has a function of controlling whether or not the potential of the power supply line is supplied to the first electrode of the battery 21.

Note that the switches 71 to 73 can be formed using the various transistors described in Embodiment 1. Here, it is preferable that at least one of the switches 71 to 73 connected to the battery 21 is formed of an OS transistor. By using the OS transistor, the leakage of the charge accumulated in the battery can be suppressed extremely small.

In the case where the switches 71 to 73 are formed using transistors, the first terminals of the switches 71 to 73 may be one of the source and the drain of the transistor, and the second terminal may be the other of the source and the drain of the transistor. In addition, a potential Vcc supplied from the terminal CC may be input to the gate of the transistor, and a conduction state of the transistor may be controlled by the potential Vcc.

In the operation of the semiconductor device 61, the conduction state of the switch 71 may be different from the conduction state of the switches 72 and 73. Therefore, when the switches 71 to 73 are configured by transistors having the same polarity, an inverted signal of the signal input to the gates of the transistors corresponding to the switches 72 and 73 is input to the gate of the transistor corresponding to the switch 71. A configuration is preferable. For example, it is preferable that the potential Vcc supplied from the terminal CC is supplied to one of the gate of the transistor corresponding to the switch 71 or the gate of the transistor corresponding to the switches 72 and 73 via an inverter. . In this case, the switches 71 to 73 and the inverter can be manufactured in the same process by forming the inverter with a transistor using a material similar to that of the transistors included in the switches 71 to 73.

The configurations and functions of the comparator 101 and the encoder 102 are the same as those of the encoder 102 in FIG.

The latch circuit 103 has a function of temporarily storing the digital signal input from the encoder 102. The latch circuit 103 can be configured by a flip-flop having a function of outputting stored data to the buffer 104 in accordance with a latch signal LAT input from the outside. Since the semiconductor device 61 includes the latch circuit 103, data can be output at an arbitrary timing. Note that the latch circuit 103 can be omitted.

The buffer 104 has a function of amplifying the data output from the latch circuit 103 and outputting the data to the terminal OUT as the output signal Vout. The buffer 104 can be configured by a circuit having an even number of inverters. By providing the buffer 104, the semiconductor device 61 can output a digital signal with reduced noise. Note that the buffer 104 can be omitted.

As described above, the semiconductor device 61 has a function of converting an analog signal into a digital signal. Therefore, the semiconductor device 61 can be used as an AD conversion circuit.

Next, an example of the operation of the semiconductor device 61 will be described.

First, when conversion from an analog signal to a digital signal is performed, the switch 71 is turned on and the switch 72 and the switch 73 are turned off by controlling the potential Vcc supplied to the terminal CC. Thereby, the battery 21 is connected in series, and the potentials of the nodes N1 to N7 are set to a predetermined potential. Then, the potentials of the nodes N1 to N7 become reference potentials Vref1 to Vref7, respectively, and are output to the comparator 101. In this way, by generating the reference potential by the battery 21, it is possible to prevent generation of unnecessary current that may occur when the reference potential is generated using the resistance element. Then, Va is determined by comparing the Va inputted as an analog signal and the reference potentials Vref1 to Vref7, and the encoder 102 converts Va into a digital signal.

On the other hand, when charging the battery 21, by controlling the potential Vcc supplied to the terminal CC, the switch 71 is turned off, and the switch 72 and the switch 73 are turned on. Thereby, the battery 21 is connected in parallel. Then, the potential of the power supply line is supplied to the first electrode of the battery 21, and the potential Vc supplied to the terminal C is supplied to the second electrode, so that all the batteries 21 are charged. In this way, by connecting all the batteries 21 in parallel and charging them in a batch, the batteries 21 can be charged at high speed.

As described above, in one embodiment of the present invention, a plurality of potentials can be generated using batteries connected in series. Therefore, when a predetermined potential is generated, unnecessary current can be prevented from flowing as in the case of using a resistance element, and power consumption can be reduced. In addition, by using an OS transistor as a switch connected to the battery, leakage of charges accumulated in the battery can be suppressed to be extremely small, and power consumption can be further reduced.

In one embodiment of the present invention, a plurality of batteries can be charged at once by connecting the batteries in parallel. Accordingly, the period for charging the battery can be shortened, and the operation speed of the semiconductor device can be improved.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a structure of an electronic circuit using the semiconductor device described in Embodiment 1 will be described.

<AD converter circuit>
FIG. 7A illustrates a configuration example of the AD conversion circuit 200 using the semiconductor device described in Embodiment 1.

The AD conversion circuit 200 includes a sample hold circuit 210, a comparison circuit 220, a successive approximation register 230, and a DA conversion circuit 240. A successive approximation type AD converter circuit is configured by using the comparison circuit 220, the successive approximation register 230, and the DA conversion circuit 240. Further, a reference data generation circuit is configured by using the successive approximation register 230 and the DA conversion circuit 240.

The AD conversion circuit 200 has a function of converting the analog signal Vin into a digital signal Vout.

The sample hold circuit 210 has a function of holding the input Vin and outputting it to the comparison circuit 220.

FIG. 7B illustrates a configuration example of the sample hold circuit 210. The sample hold circuit 210 includes a transistor 211, a capacitor 212, and an operational amplifier 213. The gate of the transistor 211 is connected to the wiring 214, one of the source and the drain is connected to the wiring to which the input signal Vin is supplied, and the other of the source and the drain is one electrode of the capacitor 212 and the non-inverting input terminal of the operational amplifier 213. Connected with. The other electrode of the capacitor 212 is connected to the wiring 215. The output terminal of the operational amplifier 213 is connected to the inverting input terminal of the operational amplifier 213 and the comparison circuit 220. A node connected to the other of the source and the drain of the transistor 211, one electrode of the capacitor 212, and the non-inverting input terminal of the operational amplifier 213 is a node A.

The transistor 211 is controlled to be on / off by a potential supplied to the wiring 214. When the transistor 211 is turned on, a potential corresponding to Vin is supplied to the node A, and when the transistor 211 is turned off, the potential of the node A is held. Here, when the transistor 211 is an OS transistor, the potential of the node A can be held for a long time.

The operational amplifier 213 has a function of amplifying the potential of the node A and outputting the amplified potential to the comparison circuit 220. Note that the operational amplifier 213 can be omitted in the case where the potential of the node A can be held in a period in which the transistor 211 is off even without the operational amplifier 213. Further, another element may be used instead of the operational amplifier 213.

The comparison circuit 220 has a function of sequentially comparing the analog signal input from the sample hold circuit 210 and the reference data input from the DA conversion circuit 240.

The successive approximation register 230 has a function of sequentially setting the value of the digital signal for each bit according to the result of the successive comparison of the comparison circuit 220.

The DA conversion circuit 240 has a function of sequentially converting the digital signal output from the successive conversion register 230 into an analog signal and outputting the analog signal to the comparison circuit 220 as reference data.

For the DA converter circuit 240, the semiconductor device 10 of FIG. 1 and the semiconductor device 11 of FIG. 3 can be used. In this case, since the power consumption of the DA converter circuit 240 can be reduced and the operation speed can be improved, a successive approximation AD converter circuit capable of high-speed operation with low power consumption can be configured.

<Phase synchronization circuit>
FIG. 8 illustrates a configuration example of a phase locked loop (PLL) 300 using the semiconductor device described in Embodiment 1.

A phase synchronization circuit 300 illustrated in FIG. 8 includes a phase comparator 310, a control circuit 320, a DA conversion circuit 330, a voltage controlled oscillation circuit (VCO) 340, and a frequency divider 350. The phase locked loop 300 has a function of outputting a signal _Sout having an oscillation frequency of _fout . The signal _Sout is input to another circuit as a clock signal.

The phase comparator 310 has a function of detecting a phase difference between two input signals and outputting a detection result as a voltage signal cmp. In the example of FIG. 8, the phase comparator 310 has a function of outputting a phase difference between a signal of frequency f _{in and} a signal of frequency f _out / N (N is an integer) as a voltage signal cmp.

The control circuit 320 can generate the K-bit digital signal D [K−1: 0] and the control signal slct of the voltage controlled oscillation circuit 340 based on the output signal cmp of the phase comparator 310.

The DA conversion circuit 330 has a function of generating the analog potential signal _Scnf . Specifically, the DA conversion circuit 330 has a function of converting the digital signal D [K−1: 0] input from the control circuit 320 into a signal _Scnf . K is an integer of 2 or more. The signal S _cnf is input to the voltage controlled oscillation circuit 340.

Voltage controlled oscillator circuit 340 has a function of outputting a signal _{S out} of the oscillation frequency _{f out} according to the voltage value of the signal _{S cnf.}

The frequency divider 350 has a function of generating a signal obtained by multiplying the frequency of the input AC signal by 1 / N. In the example of FIG. 8, the frequency divider 350 outputs a signal having a frequency f _out / N.

In FIG. 8, the semiconductor device 10 of FIG. 1 and the semiconductor device 11 of FIG. 3 can be used for the DA conversion circuit 330. In this case, since the power consumption of the DA converter circuit 330 can be reduced and the operation speed can be improved, a high-speed phase synchronization circuit with low power consumption can be configured.

Note that an electronic circuit including the semiconductor device described in Embodiment 1 is not limited to the above, and can be used for a variety of circuits such as a driver circuit included in a display device, an image sensor, a memory device, or the like.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 4)
In this embodiment, a structural example of a memory device according to one embodiment of the present invention will be described.

FIG. 9 illustrates a configuration example of the memory device 400 using the semiconductor device described in Embodiments 1 and 2.

The memory device 400 includes a memory cell array 420 provided with a plurality of memory cells 410, a row selection driver 430, a column selection driver 440, and an AD conversion circuit 450. Note that the memory device 400 includes memory cells 410 provided in a matrix of m rows and n columns.

The memory cell array 420 includes memory cells 410 provided in a matrix. In addition, the memory cell 410 includes a transistor 411, a transistor 412, and a capacitor 413.

The transistor 411 has a gate connected to the write word line WWL. In the transistor 411, the bit line BL is connected to one of a source and a drain. In the transistor 411, the floating node FN is connected to the other of the source and the drain.

The transistor 412 has a gate connected to the floating node FN. In the transistor 412, the bit line BL is connected to one of a source and a drain. In the transistor 412, the power supply line SL is connected to the other of the source and the drain.

In the capacitor 413, the floating node FN is connected to one electrode. In the capacitor 413, the read word line RWL is connected to the other electrode.

A word signal is applied to the write word line WWL.

The word signal is a signal for turning on the transistor 411 in order to apply the voltage of the bit line BL to the floating node FN.

By controlling a word signal applied to the write word line WWL and setting the potential of the floating node FN to a potential corresponding to the voltage of the bit line BL, data can be written to the memory cell. Further, data from the memory cell can be read by controlling a read signal applied to the read word line RWL and setting the voltage of the bit line BL to a voltage corresponding to the potential of the floating node FN.

Multi-value data is given to the bit line BL. The bit line BL is _{supplied with a} precharge voltage V _precharge and an initialization voltage V _initial for reading data.

Multi-value data is k-bit data (k is a natural number of 2 or more). Specifically, if it is 2-bit data, it is quaternary data, and is a signal having any one of four voltage levels.

Precharge voltage _{V Precharge,} in order to read data, a voltage applied to the bit line BL. Further, after the pre-charge voltage _{V Precharge} is applied, the bit line BL becomes electrically floating state.

The initialization voltage V _initial is a voltage that is applied to initialize the voltage of the bit line BL.

A read signal is supplied to the read word line RWL.

The read signal is a signal given to the other electrode of the capacitor 413 in order to selectively read data from the memory cell.

The floating node FN corresponds to any node on a wiring connected to one electrode of the capacitor 413, the other source or drain electrode of the transistor 411, and the gate of the transistor 412.

Note that the potential of the floating node FN is a potential based on multi-value data supplied to the bit line BL. In addition, the floating node FN is electrically floated when the transistor 411 is turned off. Therefore, when the voltage of the read signal applied to the read word line RWL is changed, the potential of the floating node FN is a potential obtained by adding the change in the voltage of the read signal to the original potential. This change in potential is due to capacitive coupling of the capacitor 413, which occurs when the read signal applied to the read word line RWL changes.

The power supply line SL is _{supplied with} a discharge voltage V _discharge that is lower than the precharge voltage V precharge applied to the bit line BL.

The discharge voltage V _discharge applied to the power supply line SL is a voltage that changes the voltage applied to the bit line BL by discharging through the transistor 412.

The transistor 411 functions as a switch that controls writing of data by switching between a conductive state and a non-conductive state. In addition, it has a function of holding a potential based on written data by holding the non-conduction state. Note that the transistor 411 is also referred to as a first transistor. The transistor 411 is described as an n-channel transistor.

When the transistor 411 is off, the potential corresponding to the written data is held in the floating node FN. Therefore, the transistor 411 is preferably a transistor with low off-state current in order to suppress a change in potential of the floating node FN. Therefore, an OS transistor is preferably used as the transistor 411.

By using an OS transistor as the transistor 411, the memory cell 410 can be a nonvolatile memory. Thus, data once written in the memory cell 410 can be kept in the floating node FN until the transistor 411 is turned on again.

The transistor 412 has a function of flowing a current Id between the source and the drain in accordance with the potential of the floating node FN. A current Id flowing between the source and the drain of the transistor 412 is a current flowing between the bit line BL and the power supply line SL. Note that the transistor 412 is also referred to as a second transistor. The transistor 412 is described as a p-channel transistor.

Note that a transistor with small variation in threshold voltage is preferably used as the transistor 412. Here, a transistor having a small variation in threshold voltage refers to a transistor that can be formed with an allowable threshold voltage difference within 20 mV when the transistors are manufactured in the same process. For example, the transistor 412 can be a transistor including a single crystal semiconductor in a channel formation region. Note that an OS transistor can be used as the transistor 412.

In FIG. 9, as the write word line WWL, the read word line RWL, the bit line BL, and the power supply line SL, the write word line WWL [m−1] in the (m−1) th row and the read word line RWL [m− 1], write word line WWL [m] in the m-th row, read word line RWL [m], bit line BL [n−1] in the (n−1) th column, bit line BL [n] in the nth column , And a power line SL.

Note that the memory cell array 420 has a configuration in which the power supply line SL is shared by adjacent memory cells. By adopting this configuration, the area occupied by the power supply line SL can be reduced. Therefore, in a semiconductor device employing this configuration, the storage capacity per unit area can be improved.

The row selection driver 430 is a circuit having a function of selectively turning on the transistors 411 in each row of the memory cells 410 and a function of selectively changing the potential of the floating node FN in each row of the memory cells 410. . Specifically, it is a circuit that gives a word signal to the write word line WWL and gives a read signal to the read word line RWL. With the row selection driver 430, the memory device 400 can select and write data to and from the memory cell 410 for each row.

The column selection driver 440 has a function of selectively writing data to the floating node FN in each column of the memory cells 410, a function of precharging the potential of the bit line BL, a function of initializing the potential of the bit line BL, and a bit line. This is a circuit having a function of bringing BL into an electrically floating state. Specifically, a circuit for providing potential, the precharge voltage _{V Precharge} the bit BL or initializing voltage _{V initial,} corresponding to multilevel data bit BL. With the column selection driver 440, the memory device 400 can select and write data to and from the memory cell 410 for each column.

The AD conversion circuit 450 is a circuit having a function of converting the potential of the bit line BL, which is an analog value, into a digital value and outputting the digital value to the outside. With the AD conversion circuit 450, the memory device 400 can output the potential of the bit line BL corresponding to the data read from the memory cell 410 to the outside.

Note that various AD conversion circuits of a flash type, a multi-slope type, and a delta sigma type can be used as the AD conversion circuit 450. In particular, the semiconductor device 60 in FIG. 5 or the semiconductor device 61 in FIG. 6 is used. Is preferred. In this case, the power consumption of the AD conversion circuit 450 can be reduced and the operation speed can be improved, so that a memory device that can operate at high speed with low power consumption can be formed.

FIG. 10 shows a configuration example of the column selection driver 440.

A column selection driver 440 illustrated in FIG. 10 includes a decoder 441, a latch circuit 442, a DA conversion circuit 443, a switch circuit 444, a transistor 445, and a transistor 446. The above circuits and transistors are provided for each column. In addition, the switch circuit 444, the transistor 445, and the transistor 446 in each column are connected to the bit line BL.

The decoder 441 is a circuit having a function of selecting a column in which the bit line BL is provided, and sorting and outputting input data. Specifically, the address signal Address and the data Data are input, and the data Data is output to the latch circuit 442 in any row in accordance with the address signal Address. By including the decoder 441, the column selection driver 440 can select an arbitrary column and write data.

Note that the data Data input to the decoder 441 is k-bit digital data. The k-bit digital data is a signal represented by binary data of “1” or “0” for each bit. Specifically, in the case of 2-bit digital data, the data is represented by “00”, “01”, “10”, “11”.

The latch circuit 442 is a circuit having a function of temporarily storing input data Data. Specifically, it is a flip-flop circuit that receives a latch signal W_LAT and outputs data Data stored in accordance with the latch signal W_LAT to the DA converter circuit 443. With the latch circuit 442, the column selection driver 440 can write data at an arbitrary timing.

The DA conversion circuit 443 is a circuit having a function of converting input digital value data Data into analog value data V _data . Specifically, the DA conversion circuit 443 is a circuit that converts the data Data into eight potentials and outputs the potential to the switch circuit 444 if the number of bits of the data Data is three. By including the DA conversion circuit 443, the column selection driver 440 can set the data written to the memory cell 100 to a potential corresponding to multi-value data.

Note that V _data output from the DA conversion circuit 443 is data represented by different voltage values. Speaking of 2-bit data, it becomes four-value data of 0.5 V, 1.0 V, 1.5 V, and 2.0 V, and can be said to be data represented by any voltage value.

Here, it is preferable to use the semiconductor device 10 in FIG. 1 or the semiconductor device 11 in FIG. 3 as the DA conversion circuit 443. In this case, since the power consumption of the DA converter circuit 443 can be reduced and the operation speed can be improved, a memory device that can operate at high speed with low power consumption can be configured.

The switch circuit 444 is a circuit having a function of _supplying input data V _data to the bit line BL and a function of electrically floating the bit line BL. Specifically, this is a circuit that includes an analog switch and an inverter, and is electrically floated by applying data V _data to the bit line BL under control by the switch control signal Write_SW and then turning off the analog switch. By providing the switch circuit 444, the column selection driver 440 can hold the bit line BL in an electrically floating state after _supplying the data V _data to the bit line BL.

The transistor 445 is a circuit having a function of applying the precharge voltage V _precharge to the bit line BL and a function of electrically floating the bit line BL. Specifically, the switch is a switch that _{applies the} precharge voltage V _precharge to the bit line BL under the control of the precharge control signal Pre_EN, and then causes the bit line BL to be in an electrically floating state. By including the transistor 445, the column selection driver 440 can hold the bit line BL in an electrically floating state after _{applying the} precharge voltage V _precharge to the bit line BL.

The transistor 446 is a circuit having a function of applying the initialization voltage V _initial to the bit line BL and a function of electrically floating the bit line BL. Specifically, it is a switch that applies an initialization voltage V _initial to the bit line BL under the control of the initialization control signal Init_EN, and then makes the bit line BL electrically floating. With the transistor 446, the column selection driver 440 can hold the bit line BL in an electrically floating state after applying the initialization voltage V _initial to the bit line BL.

As described above, by using the semiconductor device according to one embodiment of the present invention for the memory device 400, a memory device that can operate at high speed with low power consumption can be formed.

Note that the semiconductor device described in Embodiments 1 and 2 is not limited to the above memory device, and can be used for various circuits such as a driver circuit included in a display device, an image sensor, or the like.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 5)
In this embodiment, structures of a transistor and a battery that can be used for the semiconductor device according to one embodiment of the present invention will be described.

<Configuration example 1>
FIG. 11 is a cross-sectional view of a semiconductor device 1000 including a first transistor 720, a second transistor 730, and a battery 740 manufactured over the same substrate. The first transistor 720 is provided over the substrate 700, the second transistor 730 is provided over the first transistor 720, and the battery 740 is provided over the second transistor 730.

The semiconductor device 1000 includes a substrate 700, a first transistor 720, an element isolation layer 727, an insulating film 731, a second transistor 730, an insulating film 732, an insulating film 741, a battery 740, and an insulating film. 742, plugs 701, 703, 704, and 706, wirings 702 and 705, and a wiring 707. The first transistor 720 includes a gate electrode 726, a gate insulating film 724, a sidewall insulating layer 725, and the like. , An impurity region 721 that functions as a source region or a drain region, an impurity region 722 that functions as an LDD (Lightly Doped Drain) region or an extension region, and a channel formation region 723.

The transistors 720 and 730 can be used as switches and transistors in Embodiments 1 to 3. The battery 740 can be used as the battery 21 in the first and second embodiments.

The impurity concentration of the impurity region 721 is higher than that of the impurity region 722. With the use of the gate electrode 726 and the sidewall insulating layer 725 as a mask, the impurity region 721 and the impurity region 722 can be formed in a self-aligned manner.

As the substrate 700, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon on Insulator) substrate, or the like can be used. A transistor formed using a semiconductor substrate can easily operate at high speed. Note that in the case where a p-type single crystal silicon substrate is used as the substrate 700, an n-type well is formed by adding an impurity element imparting n-type to part of the substrate 700, whereby the n-type well is formed. It is also possible to form a p-type transistor in the region. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B) or the like can be used.

The substrate 700 may be a conductor substrate or an insulating substrate provided with a semiconductor film. Examples of the conductive substrate include a metal substrate, a stainless steel / still substrate, a substrate having stainless steel / still foil, a tungsten substrate, and a substrate having tungsten / foil. Examples of the insulating substrate include a glass substrate, a quartz substrate, a plastic substrate, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

Note that a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. Examples of substrates on which semiconductor elements are transferred include paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp)) , Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrate, rubber substrate, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

The first transistor 720 is separated from other transistors formed on the substrate 700 by an element isolation layer 727.

A transistor having silicide (salicide) or a transistor having no sidewall insulating layer may be used as the first transistor 720. When the structure has silicide (salicide), the resistance of the source region and the drain region can be further reduced, and the speed of the semiconductor device can be increased. In addition, since the semiconductor device can operate at a low voltage, power consumption of the semiconductor device can be reduced.

The second transistor 730 is an OS transistor. Details of the second transistor 730 will be described in Embodiment 7 to be described later.

Here, in the case where a silicon-based semiconductor material is used for the first transistor 720 provided in the lower layer, hydrogen in the insulating film provided in the vicinity of the semiconductor film of the first transistor 720 terminates a dangling bond of silicon, There is an effect of improving the reliability of the first transistor 720. On the other hand, in the case where an oxide semiconductor is used for the second transistor 730 provided in the upper layer, hydrogen in the insulating film provided in the vicinity of the semiconductor film of the second transistor 730 is a factor that generates carriers in the oxide semiconductor. Therefore, the reliability of the second transistor 730 may be reduced. Accordingly, in the case where the second transistor 730 using an oxide semiconductor is stacked over the first transistor 720 using a silicon-based semiconductor material, an insulating film having a function of preventing diffusion of hydrogen therebetween Providing 731 is particularly effective. In addition to improving the reliability of the first transistor 720 by confining hydrogen in the lower layer by the insulating film 731, the reliability of the second transistor 730 is suppressed by suppressing diffusion of hydrogen from the lower layer to the upper layer. Can be improved at the same time.

As the insulating film 731, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

In addition, an insulating film 732 having a function of preventing hydrogen diffusion is preferably formed over the second transistor 730 so as to cover the second transistor 730 including an oxide semiconductor film. As the insulating film 732, a material similar to that of the insulating film 731 can be used, and aluminum oxide is particularly preferably used. The aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the insulating film 732 that covers the second transistor 730, oxygen is prevented from being released from the oxide semiconductor film included in the second transistor 730, and the oxide semiconductor film Mixing of water and hydrogen can be prevented.

Plugs 701, 703, 704 and 706 and wirings 702, 705 and 707 are made of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti ), Tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), or a simple substance or an alloy thereof, or these A single layer or a stacked layer of a conductive film containing a compound as a main component is preferable. In particular, when a Cu—Mn alloy is used for the plugs 701, 703, 704, and 706 and the wirings 702, 705, and 707, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide diffuses Cu. Since it has the function to suppress, it is preferable.

The battery 740 is a secondary battery capable of recovering continuous use time by charging, and is an all-solid battery including a solid electrolyte. Further, the battery 740 may be connected to a wireless reception unit via a regulator and a switch so that wireless charging is possible.

The battery 740 can be manufactured using a semiconductor manufacturing process. The semiconductor manufacturing process is a general method used when manufacturing semiconductor devices such as a film forming process, a crystallization process, a plating process, a cleaning process, a lithography process, an etching process, a polishing process, an impurity implantation process, and a heat treatment process. Represents.

The details of the battery 740 will be described in Embodiment 6 described later.

The insulating film 741 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide, tantalum oxide, or One or more kinds of magnesium oxide may be selected and used in a single layer or a stacked layer.

In the case where the battery 740 contains lithium, the insulating film 741 preferably has a function of preventing (blocking) diffusion of lithium. When lithium contained in the battery 740 enters the semiconductor element (the first transistor 720 or the second transistor 730) as movable ions, the semiconductor element is deteriorated. When the insulating film 741 blocks lithium ions, a highly reliable semiconductor device can be provided.

In the case where the battery 740 contains lithium, the insulating film 741 preferably contains a halogen such as fluorine, chlorine, bromine, or iodine. When the insulating film 741 contains a halogen, it can be easily bonded to lithium that is an alkali metal, lithium can be fixed in the insulating film 741, and lithium can be prevented from diffusing out of the insulating film 741.

For example, in the case where silicon nitride is formed as the insulating film 741 by a CVD (Chemical Vapor Deposition) method, a gas containing halogen of 3% to 6%, for example, about 5% by volume is mixed in the source gas. Then, halogen is taken into the obtained silicon nitride film. The halogen element contained in the insulating film 741 has a concentration obtained by secondary ion mass spectrometry (SIMS) of 1 × 10 ¹⁷ atoms / cm ³ or more, preferably 1 × 10 ¹⁸ atoms / cm ^3. As described above, more preferably, 1 × 10 ¹⁹ atoms / cm ³ or more.

The insulating film 742 has a function of protecting the battery 740. As the insulating film 742, for example, an insulating material such as resin (polyimide resin, polyamide resin, acrylic resin, siloxane resin, epoxy resin, phenol resin, or the like), glass, an amorphous compound, or ceramics can be used. Further, a layer having calcium fluoride or the like as a water absorption layer may be provided between resin layers. The insulating film 742 can be formed by a spin coating method, an inkjet method, or the like. The insulating film 742 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide, and oxide. One or more of tantalum or magnesium oxide may be selected to produce a single layer or a stacked layer.

The semiconductor device 1000 may further include a semiconductor element on the battery 740. In this case, like the insulating film 741, the insulating film 742 preferably has a function of preventing (blocking) diffusion of lithium. With the insulating film 742 blocking lithium, a highly reliable semiconductor device can be provided.

In the case where a semiconductor element is manufactured over the battery 740, the insulating film 742 preferably contains a halogen such as fluorine, chlorine, bromine, or iodine, like the insulating film 741. When the insulating film 742 contains a halogen, it can be easily bonded to lithium which is an alkali metal, and lithium can be prevented from diffusing out of the insulating film 742.

Note that, in FIG. 11, a region to which no sign or hatching pattern is given represents a region made of an insulator. The region includes aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, An insulator including one or more selected from tantalum oxide and the like can be used. In addition, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used for the region.

The semiconductor device 1000 in FIG. 11 preferably has a cooling device such as a heat sink, a water-cooled cooler, or a cooling fan above the battery 740. By providing the cooling device, malfunction of the semiconductor device 1000 due to heat generation of the battery 740 can be prevented.

The semiconductor device 1000 in FIG. 11 may have an air gap (vacuum layer gap) between the battery 740 and the first transistor 720 and the second transistor 730. By providing the air gap, heat generated from the battery 740 can be prevented from being transmitted to the first transistor 720 and the second transistor 730, and malfunction of the first transistor 720 and the second transistor 730 due to heat can be prevented. Can be prevented.

Although the battery 740 is provided over the first transistor 720 and the second transistor 730 in FIG. 11, the battery 740 may be provided between the first transistor 720 and the second transistor 730. In that case, elements are formed in the order of the first transistor 720, the battery 740, and the second transistor 730. In particular, when the battery 740 is manufactured, in the case where heat treatment at such a high temperature that the second transistor 730 is broken is necessary, it is preferable that the second transistor 730 be formed after the battery 740 is formed.

A semiconductor in which a switch and a battery are stacked by using the first transistor 720 and the second transistor 730 for the switch in FIGS. 1, 3, 6 and the like and the battery 740 for the battery 21 in FIGS. A device can be configured. Thereby, the area of the semiconductor device can be reduced. Further, by forming the switch and the battery on the same substrate, the semiconductor device can be downsized or thinned.

<Configuration example 2>
Although FIG. 11 illustrates the case where the first transistor 720 is a planar transistor, the shape of the first transistor 720 is not limited thereto. For example, the first transistor 720 can be a FIN (fin) transistor, a TRI-GATE (trigate) transistor, or the like. An example of a cross-sectional view in that case is shown in FIG.

A semiconductor device 1100 illustrated in FIG. 12 is different from the semiconductor device 1000 in FIG. 11 in that the semiconductor device 1100 includes a FIN transistor 750 provided over a substrate 700. In FIG. 12, a transistor 750 illustrated on the left side is a cross-sectional view in the channel length direction of the transistor, and a transistor 750 illustrated on the right side is a cross-sectional view in the channel width direction of the transistor.

In FIG. 12, an insulating film 757 is provided over the substrate 700. The substrate 700 has a protruding portion (also referred to as a fin) with a thin tip. Note that an insulating film may be provided on the convex portion. The insulating film functions as a mask for preventing the substrate 700 from being etched when the convex portion is formed. In addition, the convex part does not need to have a thin tip, for example, it may be a substantially rectangular parallelepiped convex part or a thick convex part. A gate insulating film 754 is provided over the convex portion of the substrate 700, and a gate electrode 756 and a sidewall insulating layer 755 are provided thereon. In the substrate 700, an impurity region 751 functioning as a source region or a drain region, an impurity region 752 functioning as an LDD region or an extension region, and a channel formation region 753 are formed. Note that although the example in which the substrate 700 includes a convex portion is described here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

Other components of the semiconductor device 1100 are the same as those of the semiconductor device 1000.

<Configuration example 3>
A semiconductor device 1200 illustrated in FIG. 13 is different from the semiconductor device 1000 in FIG. 11 in that the first transistor 720 and the battery 740 are provided in the same level (the first transistor 720 and the battery 740 do not overlap with each other). Is different.

The semiconductor device 1200 can have the structure illustrated in FIG. 13, whereby the first transistor 720 and the plug and the wiring connected to the battery 740 can be manufactured at the same time, so that the process can be simplified. Further, when the battery 740 is manufactured, if a high-temperature treatment that destroys the plug 701 or the wiring 702 is necessary, it is necessary to form the plug 701 and the wiring 702 after the battery 740 is formed. In that case, it is preferable to provide the first transistor 720 and the battery 740 in the same layer as shown in FIG.

Note that in FIG. 13, the battery 740 is formed after the first transistor 720 is formed; however, the first transistor 720 may be formed after the battery 740 is formed first. In particular, in the case where the battery 740 is formed, in the case where high temperature treatment is required to destroy the first transistor 720, it is preferable to form the battery 740 first and then form the first transistor 720. .

Other components of the semiconductor device 1200 are the same as those of the semiconductor device 1000. The

<Configuration example 4>
A semiconductor device 1300 illustrated in FIG. 14 is different from the semiconductor device 1000 in FIG. 11 in that the transistor 720 is not provided.

In the case where all the switches illustrated in FIGS. 1, 3, 6, and the like are formed using OS transistors, a semiconductor device can be formed without forming the first transistor 720. In this case, as illustrated in FIG. 14, the semiconductor device is formed using a stacked structure of the second transistor 730 and the battery 740, and the number of steps for forming the first transistor 720 can be reduced. Accordingly, it is possible to reduce the manufacturing process and cost of the semiconductor device.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 6)
In this embodiment, structural examples of the battery described in the above embodiment will be described.

<Configuration example 1>
FIG. 15A is a top view of the battery 800, and FIG. 15B is a cross-sectional view taken along the dashed-dotted line XY in FIG. Note that in FIG. 15A, some elements are enlarged, reduced, or omitted for clarity of illustration.

A battery 800 illustrated in FIG. 15 includes an insulating film 801, a positive electrode current collector layer 802 formed over the insulating film 801, a positive electrode active material layer 803 formed over the positive electrode current collector layer 802, and a positive electrode active material. A solid electrolyte layer 804 formed on the layer 803, a negative electrode active material layer 805 formed on the solid electrolyte layer 804, and a negative electrode current collector layer 806 formed on the negative electrode active material layer 805. The positive electrode current collector layer 802 and the positive electrode active material layer 803 function as a positive electrode, and the negative electrode current collector layer 806 and the negative electrode active material layer 805 function as a negative electrode. Further, an insulating film 807 is formed over at least the negative electrode current collector layer 806, and a wiring 808 is formed in the opening of the insulating film 807. The wiring 808 is formed using the positive electrode current collector layer 802 or the negative electrode current collector. Connected to the layer 806.

Although not shown, a lithium layer may be formed at the interface between the solid electrolyte layer 804 and the positive electrode active material layer 803 or at the interface between the solid electrolyte layer 804 and the negative electrode active material layer 805. This lithium layer is a layer for supplying lithium serving as a carrier to the positive electrode active material layer or the negative electrode active material layer (also referred to as pre-doping) in the battery 800. Note that the lithium layer may be formed on the entire formation surface. Further, a copper layer or a nickel layer may be formed in contact with the lithium layer. The shape of the copper layer or nickel layer may be substantially the same as that of the lithium layer. The copper layer or nickel layer can function as a current collector when lithium is pre-doped from the lithium layer to the positive electrode active material layer or the negative electrode active material layer.

Note that all lithium in the lithium layer may be doped into the positive electrode active material layer or the negative electrode active material layer by the pre-doping, or the lithium layer may remain. Since the lithium layer remains after pre-doping in this way, it can be used to replenish lithium that has disappeared due to irreversible capacity due to charging / discharging of the battery.

For the details of the insulating film 801, the description of the insulating film 741 in Embodiment 5 may be referred to.

The positive electrode current collector layer 802, the positive electrode active material layer 803, the negative electrode active material layer 805, and the negative electrode current collector layer 806 can be formed by a sputtering method, a CVD method, a nanoimprint method, a vapor deposition method, or the like. When the sputtering method is used, it is preferable to form a film using a DC power source instead of RF. The sputtering method using a DC power source is preferable because the film forming rate is high and the tact time is shortened. The film thicknesses of the positive electrode current collector layer 802, the positive electrode active material layer 803, the negative electrode active material layer 805, and the negative electrode current collector layer 806 may be, for example, 100 nm or more and 100 μm or less.

As the positive electrode current collector layer 802, one or more of titanium (Ti), aluminum (Al), gold (Au), and platinum (Pt) may be selected and used in a single layer or a stacked layer. Alternatively, the metal alloy or the conductive film containing a compound containing these as a main component may be used as a single layer or a stacked layer.

As the positive electrode active material layer 803, one or more of lithium cobaltate, lithium iron phosphate, lithium manganate, lithium nickelate, and vanadium oxide may be selected and used in a single layer or a stacked layer.

For the positive electrode active material layer 803, a lithium-containing composite phosphate having an olivine structure can be used. As representative examples of lithium-containing composite phosphates (general formula LiMPO ₄ (M is one or more of Fe (II), Mn (II), Co (II), Ni (II))), LiFePO ₄ , LiNiPO ₄ , LiCoPO ₄ , LiMnPO ₄ , LiFe _a Ni _b PO ₄ , LiFe _a Co _b PO ₄ , LiFe _a Mn _b PO ₄ , LiNi _a Co _b PO ₄ , LiNi _a Mn _b PO ₄ (a + b is 1 or less, 0 <a _{<1,0 <b <1),} LiFe c Ni d Co e PO 4, LiFe c Ni d Mn e PO 4, LiNi c Co d Mn e PO 4 (c + d + e ≦ 1, 0 <c <1,0 < _{d <1,0 <e <1)} , LiFe f Ni g Co h Mn i PO 4 (f + g + h + i is 1 or less, 0 <f <1,0 <g <1,0 <h <1,0 <i <1 And the like.

As the solid electrolyte layer 804, an inorganic solid electrolyte that can be formed by sputtering, vapor deposition, or CVD is used. As the inorganic solid electrolyte, a sulfide solid electrolyte or an oxide solid electrolyte can be used.

Examples of the sulfide-based solid electrolyte include Li ₇ P ₃ S ₁₁ , Li _3.25 P _0.95 S ₄ , Li ₁₀ GeP ₂ S ₁₂ , Li _3.25 Ge _0.25 P _0.75 S ₄ , _{Li 2 S-P 2 S 5} , Li 2 S-GeS 2, Li 2 S-SiS 2 -Li 3 PO 4, Li 2 S-SiS 2 -Ga 2 S 3, Li 2 S-SiS 2 -Li 4 SiO _{4, LiI-Li 2 S-} P 2 S 5, LiI-Li 2 S-B 2 S 3, LiI-Li 2 S-SiS 2, and lithium composite sulfide material such as is.

In addition, as the oxide-based solid electrolyte, Li _1.3 Al _0.3 Ti _1.7 (PO ₄ ) ₃ , Li _1.07 Al _0.69 Ti _1.46 (PO ₄ ) ₃ , Li ₄ SiO _{4 -Li 3 BO 3, Li 2.9 PO} 3.3 N 0.46, Li 3.6 Si 0.6 P 0.4 O 4, Li 1.5 Al 0.5 Ge 1.6 (PO 4) ₃ , Li ₂ O, Li ₂ CO ₃ , Li ₂ MoO ₄ , Li ₃ PO ₄ , Li ₃ VO ₄ , Li ₄ SiO ₄ , LLT (La _{2 / 3-x} Li _3x TiO ₃ ), LLZ (Li ₇ La _And lithium composite oxides such as ₃ Zr ₂ O ₁₂ ) and lithium oxide materials.

Further, for the solid electrolyte layer 804, a polymer solid electrolyte such as PEO (polyethylene oxide) formed by a coating method or the like may be used. Furthermore, you may use the composite solid electrolyte containing the inorganic type solid electrolyte and polymer solid electrolyte mentioned above.

The negative electrode active material layer 805 includes carbon (C), silicon (Si), germanium (Ge), tin (Sn), aluminum (Al), lithium (Li), lithium titanate, lithium niobate, niobium oxide, and tantalum oxide. One or more types of silicon oxide may be selected and used in a single layer or a stacked layer.

The negative electrode current collector layer 806 is selected from one or more of titanium (Ti), copper (Cu), stainless steel, iron (Fe), gold (Au), platinum (Pt), and nickel (Ni). What is necessary is just to use it by lamination | stacking. Alternatively, the metal alloy or the conductive film containing a compound containing these as a main component may be used as a single layer or a stacked layer.

Note that the positive electrode active material layer and the negative electrode active material layer may include a binder (binder) for improving the adhesion of the active material, as necessary.

For example, the binder preferably contains a water-soluble polymer. For example, polysaccharides can be used as the water-soluble polymer. As the polysaccharide, carboxymethyl cellulose (CMC), methyl cellulose, ethyl cellulose, hydroxypropyl cellulose, diacetyl cellulose, cellulose derivatives such as regenerated cellulose, starch, and the like can be used.

The binder is preferably a rubber material such as styrene-butadiene rubber (SBR), styrene / isoprene / styrene rubber, acrylonitrile / butadiene rubber, butadiene rubber, ethylene / propylene / diene copolymer. These rubber materials are more preferably used in combination with the water-soluble polymer described above.

Or as binder, polystyrene, polymethyl acrylate, polymethyl methacrylate (PMMA), sodium polyacrylate, polyvinyl alcohol (PVA), polyethylene oxide (PEO), polypropylene oxide, polyimide, polyvinyl chloride, polytetrafluoro It is preferable to use materials such as ethylene, polyethylene, polypropylene, isobutylene, polyethylene terephthalate, nylon, polyvinylidene fluoride (PVdF), polyacrylonitrile (PAN), and the like.

You may use a binder in combination of 2 or more types among the above.

In addition, the positive electrode active material layer and the negative electrode active material layer may have a conductive auxiliary agent for increasing the conductivity of the active material layer.

As the conductive assistant, for example, artificial graphite such as natural graphite or mesocarbon microbeads, carbon fiber, or the like can be used. As the carbon fibers, for example, carbon fibers such as mesophase pitch-based carbon fibers and isotropic pitch-based carbon fibers can be used. Moreover, carbon nanofiber, a carbon nanotube, etc. can be used as carbon fiber. Carbon nanotubes can be produced by, for example, a vapor phase growth method. Further, as the conductive assistant, for example, a carbon material such as carbon black (acetylene black (AB) or the like) or graphene can be used. Further, for example, metal powder such as copper, nickel, aluminum, silver, gold, metal fiber, conductive ceramic material, or the like can be used.

Flaky graphene has excellent electrical properties such as high electrical conductivity, and excellent physical properties such as flexibility and mechanical strength. Therefore, by using graphene as a conductive additive, the contact point and the contact area between the active materials can be increased.

Note that in this specification, graphene includes single-layer graphene or multilayer graphene of two to 100 layers. Single-layer graphene refers to a sheet of one atomic layer of carbon molecules having a π bond. The graphene oxide refers to a compound obtained by oxidizing the graphene. Note that in the case of reducing graphene oxide to form graphene, all oxygen contained in the graphene oxide is not desorbed and part of oxygen remains in the graphene. When oxygen is contained in graphene, the proportion of oxygen is 2% or more and 20% or less, preferably 3% or more and 15% or less of the entire graphene when measured by XPS (X-ray photoelectron spectroscopy).

Moreover, you may provide a separator so that a positive electrode and a negative electrode may not short-circuit in a solid electrolyte layer as needed. As the separator, an insulator provided with holes is preferably used. For example, cellulose, glass fiber, ceramics, nylon (polyamide), vinylon (polyvinyl alcohol fiber), polyester, acrylic, polyolefin, synthetic fiber using polyurethane, or the like can be used.

For the details of the insulating film 807, the description of the insulating film 742 in Embodiment 5 may be referred to.

For the details of the wiring 808, the description of the wiring 707 in Embodiment 5 may be referred to.

Note that the battery 800 may interchange the vertical relationship between the positive electrode and the negative electrode illustrated in FIG. That is, you may produce the negative electrode collector layer 806, the negative electrode active material layer 805, the solid electrolyte layer 804, the positive electrode active material layer 803, and the positive electrode collector layer 802 in order from the bottom.

For example, when LiFePO ₄ having a thickness of 1 μm is used for the positive electrode active material layer 803, a capacity of approximately 60 μAh / cm ² is obtained when the capacity of the battery 800 is calculated.

For example, when LiCoO ₂ having a thickness of 1 μm is used for the positive electrode active material layer 803, when the capacity of the battery 800 is calculated, a capacity of approximately 70 μAh / cm ² is obtained.

For example, when iMn ₂ O ₄ having a thickness of 1 μm is used for the positive electrode active material layer 803, a capacity of approximately 60 μAh / cm ² is obtained when the capacity of the battery 800 is calculated.

Note that all the above calculations assume lithium in the negative electrode active material layer 805, and the theoretical capacity values of the respective positive electrode active materials (LiFePO ₄ is 170 mAh / g, LiCoO ₂ is 137 mAh / g, LiMn ₂ O ₄ is 148 mAh / Calculations were made using g).

The area and capacity of the battery 800 may be determined in accordance with the amount of power necessary for the semiconductor device or electronic device to be connected. For example, when LiFePO ₄ is used for the positive electrode active material layer 803, the area of the battery 800 (the area where the positive electrode active material layer 803 and the negative electrode active material layer 805 overlap) is 1 cm ² or more when the above calculation result is used. By accommodating it in 100 cm ² or less, the capacity of the battery 800 can be set to 60 μAh or more and 6 mAh or less.

In addition, a plurality of batteries 800 may be connected in series and / or in parallel depending on the amount of power required for the semiconductor device or electronic device connected to the battery. In particular, it is preferable to connect a plurality of stacked batteries 800 in series and / or in parallel so that the energy density of the battery can be increased and the occupied area can be reduced.

<Configuration example 2>
FIG. 16 illustrates an example of a battery included in one embodiment of the present invention. FIG. 16A is a top view of the battery 810, and FIG. 16B is a cross-sectional view taken along the dashed-dotted line X-Y in FIG. Note that in FIG. 16A, some elements are enlarged, reduced, or omitted for clarity.

A battery 810 illustrated in FIG. 16B includes an insulating film 801, a positive electrode current collector layer 802 and a negative electrode current collector layer 806 which are formed on the same plane over the insulating film 801, and the positive electrode current collector layer 802. A positive electrode active material layer 803, a negative electrode active material layer 805 on the negative electrode current collector layer 806, and a solid electrolyte layer 804 in contact with at least the positive electrode active material layer 803 and the negative electrode active material layer 805. The body layer 802 and the positive electrode active material layer 803 function as a positive electrode, and the negative electrode current collector layer 806 and the negative electrode active material layer 805 function as a negative electrode. Further, an insulating film 807 is formed at least on the solid electrolyte layer 804, and a wiring 808 is formed in the opening of the insulating film 807. The wiring 808 is connected to the positive electrode current collector layer 802 or the negative electrode current collector layer 806. Has been.

A battery 810 is different from the battery 800 in FIG. 15 in that the positive electrode current collector layer 802 and the negative electrode current collector layer 806 are formed on the same plane, and the positive electrode and the negative electrode are present in the XY directions in FIG. . When the battery 810 has the structure illustrated in FIG. 16B, a certain distance can be provided between the positive electrode and the negative electrode, and a short circuit between the positive electrode and the negative electrode can be prevented.

For details on each component of the battery 810, the description of the battery 800 in FIG. 15 may be referred to.

Note that the positive electrode current collector layer 802 and the negative electrode current collector layer 806 of the battery 810 may be formed using the same material at the same time. By simultaneously forming the current collector layers of the positive electrode and the negative electrode with the same material, the manufacturing process can be simplified.

<Configuration example 3>
FIG. 17 illustrates an example of a battery included in one embodiment of the present invention. FIG. 17A is a top view of the battery 820, and FIG. 17B is a cross-sectional view taken along dashed-dotted line XY in FIG. Note that in FIG. 17A, some elements are enlarged, reduced, or omitted for clarity.

A battery 820 illustrated in FIG. 17B includes an insulating film 801, a positive electrode current collector layer 802 and a negative electrode current collector layer 806 that are formed on the same plane over the insulating film 801, and the positive electrode current collector layer 802. A positive electrode active material layer 803, a solid electrolyte layer 804 formed on at least the positive electrode active material layer 803, the insulating film 801, and the negative electrode current collector layer 806, and a positive electrode active material via the solid electrolyte layer 804 And a negative electrode active material layer 805 formed over the solid electrolyte layer 804 and the negative electrode current collector layer 806. The positive electrode current collector layer 802 and the positive electrode active material layer 803 serve as a positive electrode. The negative electrode current collector layer 806 and the negative electrode active material layer 805 function as a negative electrode. Further, an insulating film 807 is formed at least over the negative electrode active material layer 805, and a wiring 808 is formed in the opening of the insulating film 807. The wiring 808 is connected to the positive electrode current collector layer 802 or the negative electrode current collector layer 806. Has been.

A battery 820 illustrated in FIG. 17B is different from the battery 810 illustrated in FIG. 16B in that a negative electrode active material layer 805 is formed over the solid electrolyte layer 804. With the structure of the battery 820 illustrated in FIG. 17B, a certain distance can be provided between the positive electrode current collector layer 802 and the negative electrode current collector layer 806 in order to prevent a short circuit. In order to efficiently move, the distance between the positive electrode active material layer 803 and the negative electrode active material layer 805 can be reduced.

Details regarding each component of the battery 820 may be referred to the description of the battery 800 in FIG.

Note that the battery 820 may interchange the vertical relationship between the positive electrode and the negative electrode. That is, the negative electrode active material layer 805, the solid electrolyte layer 804, and the positive electrode active material layer 803 may be formed sequentially from the bottom.

Alternatively, the positive electrode current collector layer 802 and the negative electrode current collector layer 806 of the battery 820 may be formed using the same material at the same time. By simultaneously forming the current collector layers of the positive electrode and the negative electrode with the same material, the manufacturing process can be simplified.

<Configuration example 4>
FIG. 18 illustrates an example of a battery included in one embodiment of the present invention. FIG. 18A is a cross-sectional view of the battery 830.

A battery 830 illustrated in FIG. 18A includes an insulating film 801, a positive electrode current collector layer 802 formed over the insulating film 801, a positive electrode active material layer 803 formed over the positive electrode current collector layer 802, A solid electrolyte layer 804 formed on the positive electrode active material layer 803; an insulating film 811 formed on the solid electrolyte layer 804; a negative electrode active material layer 805 formed on the solid electrolyte layer 804 and the insulating film 811; A negative electrode current collector layer 806 formed on the negative electrode active material layer 805, the positive electrode current collector layer 802 and the positive electrode active material layer 803 function as a positive electrode, and the negative electrode current collector layer 806 and the negative electrode active material The layer 805 functions as a negative electrode. Further, an insulating film 807 is formed over at least the negative electrode current collector layer 806. Although not shown, the positive electrode current collector layer 802 and the negative electrode current collector layer 806 are connected to the outside through wiring.

In the battery 830 illustrated in FIG. 18A, a region where the solid electrolyte layer 804 and the negative electrode active material layer 805 are in contact functions as a battery, and a region where the solid electrolyte layer 804 does not function as the battery is an insulating film 811 formed of the solid electrolyte layer 804 and the negative electrode active material layer. By being between 805, a short circuit between the positive electrode and the negative electrode can be prevented.

For the insulating film 811, for example, an organic resin or an inorganic insulating material can be used. As the organic resin, for example, polyimide resin, polyamide resin, acrylic resin, siloxane resin, epoxy resin, phenol resin, or the like can be used. As the inorganic insulating material, silicon oxide, silicon oxynitride, or the like can be used. In particular, a photosensitive resin is preferably used because the insulating film 811 can be easily manufactured. The formation method of the insulating film 811 is not particularly limited, and for example, a photolithography method, a sputtering method, a vapor deposition method, a droplet discharge method (inkjet method or the like), a printing method (screen printing, offset printing, or the like) may be used. .

For details regarding other components of the battery 830, the description of the battery 800 in FIG. 15 may be referred to.

Note that the battery 830 may include an insulating film 811 over the positive electrode active material layer 803 as illustrated in FIG.

Note that in the battery 830 illustrated in FIGS. 18A and 18B, the vertical relationship between the positive electrode and the negative electrode may be interchanged. That is, you may produce the negative electrode collector layer 806, the negative electrode active material layer 805, the solid electrolyte layer 804, the positive electrode active material layer 803, and the positive electrode collector layer 802 in order from the bottom.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 7)
In this embodiment, an example of the structure of the OS transistor described in the above embodiment will be described. Note that the OS transistor described in this embodiment is an example, and the shape of the transistor that can be used in the present invention is not limited thereto.

<Configuration example of OS transistor>
19A to 19D are a top view and a cross-sectional view of the transistor 900. FIG. 19A is a top view, a cross section in the direction of dashed-dotted line Y1-Y2 in FIG. 19A corresponds to FIG. 19B, and the direction in dashed-dotted line X1-X2 in FIG. A cross section corresponds to FIG. 19C, and a cross section in the direction of dashed-dotted line X3-X4 in FIG. 19A corresponds to FIG. Note that in FIGS. 19A to 19D, some elements are illustrated in an enlarged, reduced, or omitted manner for clarity. The direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line X1-X2 may be referred to as a channel width direction.

Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

The transistor 900 includes an insulating film 952 over a substrate 940, a stack in which the first oxide semiconductor 961 and the second oxide semiconductor 962 are formed in this order over the insulating film 952, and a part of the stack is connected to the transistor 900. Source electrode 971 and drain electrode 972, part of the stack, part of source electrode 971, part of drain electrode 972, third oxide semiconductor 963 covering the part of stack, part of stack, source electrode 971, part of drain electrode 972, gate insulating film 953 and gate electrode 973 overlapping with third oxide semiconductor 963, source electrode 971 and drain electrode 972, and insulating film 954 over gate electrode 973; An insulating film 955 over the insulating film 954 is provided. Note that the first oxide semiconductor 961, the second oxide semiconductor 962, and the third oxide semiconductor 963 are collectively referred to as an oxide semiconductor 960.

Note that at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed from a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , Surface, side surface, upper surface, and / or at least part (or all) of the lower surface.

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , Surface, side surface, upper surface, and / or at least part (or all) of the lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). At least a part (or all) is in contact.

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , The front surface, the side surface, the upper surface, and / or at least a part (or all) of the lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). Some (or all) are connected.

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , Surface, side surface, upper surface, and / or at least part (or all) of the lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). Some (or all) of them are arranged close to each other.

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , The surface, the side surface, the upper surface, and / or the lateral surface of at least a part (or all) of the lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). It is arranged on the side of some (or all).

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , At least a part (or all) of the front surface, side surface, upper surface, and / or lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). It is arranged on a part (or all) of the diagonally upper side.

Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). , The surface, the side surface, the upper surface, and / or the upper surface of at least a part (or all) of the lower surface. Alternatively, at least part (or all) of the source electrode 971 (and / or the drain electrode 972) is formed of a semiconductor layer such as the second oxide semiconductor 962 (and / or the first oxide semiconductor 961). It is arranged on a part (or all) of the upper side.

Note that the functions of the “source” and “drain” of the transistor may be interchanged when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

The transistor of one embodiment of the present invention has a top-gate structure with a channel length of 10 nm to 1000 nm, preferably a channel length of 20 nm to 500 nm, more preferably a channel length of 30 nm to 300 nm.

Hereinafter, components included in the semiconductor device of the present embodiment will be described in detail.

<Board>
The substrate 940 is not limited to a simple support material, and may be a substrate on which other devices such as transistors are formed. In this case, one of the gate electrode 973, the source electrode 971, and the drain electrode 972 of the transistor 900 may be connected to the other device.

<Base insulating film>
The insulating film 952 can serve to prevent diffusion of impurities from the substrate 940 and can supply oxygen to the oxide semiconductor 960. Therefore, the insulating film 952 is preferably an insulating film containing oxygen, and more preferably an insulating film containing oxygen larger than the stoichiometric composition. For example, a film having an oxygen release amount of 1.0 × 10 ¹⁹ atoms / cm ³ or more converted to oxygen atoms by a TDS method (Thermal Desorption Spectroscopy). The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C. In addition, in the case where the substrate 940 is a substrate on which another device is formed as described above, the insulating film 952 is preferably subjected to planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like so that the surface becomes flat. .

The insulating film 952 includes oxide insulating materials such as aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. It can be formed using a film, a nitride insulating film such as silicon nitride, silicon nitride oxide, or aluminum nitride oxide, or a film in which the above materials are mixed.

<Oxide semiconductor>
The oxide semiconductor 960 typically includes an In—Ga oxide, an In—Zn oxide, an In—M—Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, an In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) is preferably used as the oxide semiconductor 960.

Note that the oxide semiconductor 960 is not limited to the oxide containing indium. The oxide semiconductor 960 may be, for example, a Zn—Sn oxide or a Ga—Sn oxide.

In-M-Zn oxide in which the oxide semiconductor 960 is an In-M-Zn oxide manufactured by a sputtering method (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) It is preferable that the atomic ratio of the metal element of the target used for forming the film satisfies In ≧ M and Zn ≧ M. As the atomic ratio of the metal element of such a target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2 In: M: Zn = 2: 1: 3 is preferable. Note that the atomic ratio of the oxide semiconductor 960 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.

Next, FIG. 20B illustrates functions and effects of the oxide semiconductor 960 including the stack of the first oxide semiconductor 961, the second oxide semiconductor 962, and the third oxide semiconductor 963. This will be described using the energy band structure diagram shown. 20A is an enlarged view of the channel portion of the transistor 900 illustrated in FIG. 19B, and FIG. 20B is an energy band of the portion indicated by the chain line A1-A2 in FIG. 20A. The structure is shown. FIG. 20B illustrates an energy band structure of a channel formation region of the transistor 900.

In FIG. 20B, Ec952, Ec961, Ec962, Ec963, and Ec953 are an insulating film 952, a first oxide semiconductor 961, a second oxide semiconductor 962, a third oxide semiconductor 963, and a gate insulating film, respectively. The energy at the lower end of the conduction band of the film 953 is shown.

Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

Note that an In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 2 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 4 has an energy gap of about 3.4 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 6 has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 2 has an energy gap of about 3.9 eV and an electron affinity of about 4.3 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 8 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.4 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 10 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 1: 1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 3: 1: 2 has an energy gap of about 2.8 eV and an electron affinity of about 5.0 eV. .

Since the insulating film 952 and the gate insulating film 953 are insulators, Ec953 and Ec952 are closer to the vacuum level (having a lower electron affinity) than Ec961, Ec962, and Ec963.

Ec961 is closer to the vacuum level than Ec962. Specifically, Ec961 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec962. It is preferable that it is close to.

Ec963 is closer to the vacuum level than Ec962. Specifically, Ec963 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec962. It is preferable that it is close to.

In addition, mixed regions are formed in the vicinity of the interface between the first oxide semiconductor 961 and the second oxide semiconductor 962 and in the vicinity of the interface between the second oxide semiconductor 962 and the third oxide semiconductor 963. Therefore, the energy at the lower end of the conduction band changes continuously. That is, there are almost no levels at these interfaces.

Accordingly, electrons move mainly in the second oxide semiconductor 962 in the stacked structure having the energy band structure. Therefore, even if a level exists at the interface between the first oxide semiconductor 961 and the insulating film 952 or the interface between the third oxide semiconductor 963 and the gate insulating film 953, the level does not move electrons. Hardly affected. In addition, there are no or almost no levels at the interface between the first oxide semiconductor 961 and the second oxide semiconductor 962 and the interface between the third oxide semiconductor 963 and the second oxide semiconductor 962. Therefore, movement of electrons in the region is not hindered. Therefore, the transistor 900 having the stacked structure of the oxide semiconductor can achieve high field effect mobility.

Note that as illustrated in FIG. 20, in the vicinity of the interface between the first oxide semiconductor 961 and the insulating film 952 and in the vicinity of the interface between the third oxide semiconductor 963 and the gate insulating film 953, trap states caused by impurities and defects are present. Although the position Et900 can be formed, the presence of the first oxide semiconductor 961 and the third oxide semiconductor 963 enables the second oxide semiconductor 962 and the trap level to be separated from each other.

In particular, in the transistor 900 illustrated in this embodiment, the top surface and the side surface of the second oxide semiconductor 962 are in contact with the third oxide semiconductor 963 in the channel width direction, and the bottom surface of the second oxide semiconductor 962 is It is formed in contact with the first oxide semiconductor 961 (see FIG. 19C). In this manner, with the structure in which the second oxide semiconductor 962 is covered with the first oxide semiconductor 961 and the third oxide semiconductor 963, the influence of the trap states can be further reduced.

However, in the case where the energy difference between Ec961 or Ec963 and Ec962 is small, the electrons of the second oxide semiconductor 962 may reach the trap level exceeding the energy difference. By trapping electrons in the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the energy difference between Ec961, Ec963, and Ec962 is 0.1 eV or more, preferably 0.15 eV or more, variation in the threshold voltage of the transistor is reduced, and the electrical characteristics of the transistor are good. Therefore, it is preferable.

The band gaps of the first oxide semiconductor 961 and the third oxide semiconductor 963 are preferably wider than the band gap of the second oxide semiconductor 962.

For the first oxide semiconductor 961 and the third oxide semiconductor 963, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf is higher than the second oxide semiconductor 962 A material containing an atomic ratio can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. The above element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide semiconductor. That is, it can be said that the first oxide semiconductor 961 and the third oxide semiconductor 963 are less likely to have oxygen vacancies than the second oxide semiconductor 962.

Note that the first oxide semiconductor 961, the second oxide semiconductor 962, and the third oxide semiconductor 963 include at least indium, zinc, and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, In the case of an In-M-Zn oxide containing a metal such as Ce or Hf, the first oxide semiconductor 961 is formed of In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], second The oxide semiconductor 962 of In: M: Zn = x ₂ : y ₂ : z ₂ [atomic ratio] and the third oxide semiconductor 963 is In: M: Zn = x ₃ : y ₃ : z ₃ [atomic Number ratio], y ₁ / x ₁ and y ₃ / x ₃ are preferably larger than y ₂ / x ₂ . y ₁ / x ₁ and y ₃ / x ₃ are 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than y ₂ / x ₂ . At this time, in the second oxide semiconductor 962, when y ₂ is greater than or equal to x ₂ , the electrical characteristics of the transistor can be stabilized. However, when y ₂ is 3 times or more of x ₂ , the field-effect mobility of the transistor is lowered. Therefore, y ₂ is preferably less than 3 times x ₂ .

The atomic ratio of In and M excluding Zn and O in the first oxide semiconductor 961 and the third oxide semiconductor 963 is preferably that In is less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic% and M is higher than 75 atomic%. The atomic ratio of In and M excluding Zn and O in the second oxide semiconductor 962 is preferably that In is higher than 25 atomic%, M is lower than 75 atomic%, and more preferably In is higher than 34 atomic%. , M is less than 66 atomic%.

The thicknesses of the first oxide semiconductor 961 and the third oxide semiconductor 963 are 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the second oxide semiconductor 962 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm. The second oxide semiconductor 962 is preferably thicker than the first oxide semiconductor 961 and the third oxide semiconductor 963.

Note that in order to impart stable electrical characteristics to a transistor including an oxide semiconductor as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor so that the oxide semiconductor is intrinsic or substantially intrinsic. . Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × 10 10. It indicates less than ¹³ / cm ³ .

In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of the first oxide semiconductor 961, the second oxide semiconductor 962, and the third oxide semiconductor 963 and at the respective interfaces.

In order to make an oxide semiconductor intrinsic or substantially intrinsic, in SIMS analysis, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the silicon concentration is set to 1 × 10 ¹⁹ atoms / Less than cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . The hydrogen concentration is, for example, 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region where the oxide semiconductor is present. It is preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. The nitrogen concentration is, for example, less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region where the oxide semiconductor is present. It is preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, in the case where the oxide semiconductor includes crystals, the crystallinity of the oxide semiconductor may be reduced if silicon or carbon is included at a high concentration. In order not to decrease the crystallinity of the oxide semiconductor, for example, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor. It suffices to have a portion that is less than × 10 ¹⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . In addition, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the carbon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably May have a portion less than 1 × 10 ¹⁸ atoms / cm ³ .

Further, the off-state current of the transistor in which the oxide semiconductor purified as described above is used for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor is reduced from several yA / μm to several zA / μm. It becomes possible.

In the transistor 900 exemplified in this embodiment, the gate electrode 973 is formed so as to electrically surround the channel width direction of the oxide semiconductor 960; thus, the gate electric field from the vertical direction with respect to the oxide semiconductor 960 is formed. In addition, a gate electric field from the side surface direction is applied. That is, a gate electric field is applied to the entire oxide semiconductor, so that current flows through the entire second oxide semiconductor 962 serving as a channel, and the on-state current can be further increased.

<Crystal structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor film is described.

An oxide semiconductor film is classified into, for example, a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. Alternatively, an oxide semiconductor is classified into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

Note that examples of the non-single-crystal oxide semiconductor include a CAAC-OS (C Axis Crystallized Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. As a crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or the like can be given.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °. In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

<CAAC-OS>
The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film is unlikely to have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

<Microcrystalline oxide semiconductor film>
The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter larger than that of the crystal part (eg, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

<Amorphous oxide semiconductor film>
An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

Note that the crystal part size of the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of an InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

In addition, the oxide semiconductor film may have a different density for each structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing with the density of a single crystal having the same composition as the composition. For example, the density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the density of the single crystal. For example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the density of the single crystal. Note that it is difficult to form an oxide semiconductor film whose density is lower than 78% with respect to that of a single crystal.

The above will be described using a specific example. For example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the a-like OS film is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. It becomes. For example, in the oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS film and the density of the CAAC-OS film are 5.9 g / cm ³ or more 6 Less than ³ g / cm ³ .

Note that there may be no single crystal having the same composition. In that case, a density corresponding to a single crystal having a desired composition can be calculated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to calculate the density of the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably calculated by combining as few kinds of single crystals as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

In addition, in order to form the CAAC-OS film by a sputtering method, it is preferable to apply the following conditions.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the treatment chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. When the substrate heating temperature at the time of film formation is increased, when the flat or pellet-like sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

As an example of the target, an In—Ga—Zn-based oxide target is described below.

In-Ga-Zn which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder at a predetermined mol number ratio, and after heat treatment at a temperature of 1000 ° C. to 1500 ° C. A system oxide target is used. X, Y and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3, 1: 4: 4, 3: 1: 2 or 2: 1: 3. In addition, what is necessary is just to change suitably the kind of powder, and the mol number ratio to mix with the target to produce.

<Gate electrode>
The gate electrode 973 includes chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), Metal element selected from tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), an alloy containing the above metal element as a component, or the above metal It can be formed using an alloy or the like combining elements. The gate electrode 973 may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are stacked on the titanium film, and a titanium film is further formed thereon, Cu Single layer structure of -Mn alloy film, two layer structure in which Cu film is laminated on Cu-Mn alloy film, Cu film is laminated on Cu-Mn alloy film, and Cu-Mn alloy film is further laminated thereon There are three-layer structures. In particular, a Cu—Mn alloy film is preferable because it has low electric resistance and can form manganese oxide at an interface with an insulating film containing oxygen to prevent Cu from diffusing.

The gate electrode 973 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as an indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

<Gate insulation film>
The gate insulating film 953 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film containing one or more of them can be used. The gate insulating film 953 may be a stacked layer of the above materials. Note that the gate insulating film 953 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

An example of a stacked structure of the gate insulating film 953 is described. The gate insulating film 953 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, since the thickness of the gate insulating film 953 can be increased as compared with the case where silicon oxide or silicon oxynitride is used, leakage current due to a tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

<Source electrode and drain electrode>
The source electrode 971 and the drain electrode 972 can be formed using a material similar to that of the gate electrode 973. In particular, a Cu—Mn alloy film is preferable because it has low electrical resistance and can form manganese oxide at the interface with the oxide semiconductor 960 to prevent diffusion of Cu.

<Protective insulating film>
The insulating film 954 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating film 954, diffusion of oxygen from the oxide semiconductor 960 to the outside and entry of hydrogen, water, and the like into the oxide semiconductor 960 from the outside can be prevented. As the insulating film 954, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

The aluminum oxide film is preferable to be applied to the insulating film 954 because it has a high blocking effect of preventing permeation of both hydrogen, moisture and other impurities, and oxygen. Therefore, the aluminum oxide film prevents the entry of impurities such as hydrogen and moisture, which cause variation in the electrical characteristics of the transistor, into the oxide semiconductor 960 during and after the manufacturing process of the transistor, and constitutes the oxide semiconductor 960. It is suitable for use as a protective film having an effect of preventing release of oxygen as a component material from an oxide semiconductor and preventing unnecessary release of oxygen from the insulating film 952. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor.

<Interlayer insulation film>
In addition, an insulating film 955 is preferably formed over the insulating film 954. The insulating film contains one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used. The oxide insulating film may be a stack of the above materials.

<Second gate electrode>
Note that FIG. 19 illustrates an example in which one gate electrode is provided in a transistor; however, one embodiment of the present invention is not limited thereto. A plurality of gate electrodes may be provided in the transistor. As an example, FIGS. 21A to 21D illustrate an example in which the transistor 900 illustrated in FIGS. 19A and 19B is provided with a conductive film 974 as the second gate electrode. 21A is a top view, and a cross section in the direction of dashed-dotted line Y1-Y2 in FIG. 21A corresponds to FIG. 21B, and is in the direction of dashed-dotted line X1-X2 in FIG. A cross section corresponds to FIG. 21C, and a cross section in the direction of dashed-dotted line X3-X4 in FIG. 21A corresponds to FIG. Note that in FIGS. 21A to 21D, some elements are illustrated in an enlarged, reduced, or omitted manner for clarity.

The conductive film 974 can be formed using the materials described for the gate electrode 973 or a stacked structure. The conductive film 974 functions as a gate electrode layer. Note that the conductive film 974 may be supplied with a constant potential, or may be supplied with the same potential or the same signal as the gate electrode 973.

Note that as in the transistor 900 in FIG. 21, when a certain transistor T includes a pair of gates with a semiconductor film interposed therebetween, a signal A is fixed to one gate and the other gate is fixed. The potential Vb may be applied. Further, the signal A may be given to one gate, and the signal B may be given to the other gate. One gate may be supplied with a fixed potential Va and the other gate may be supplied with a fixed potential Vb.

The signal A is a signal for controlling a conduction state or a non-conduction state, for example. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is a potential for controlling the threshold voltage VthA corresponding to one gate of the transistor T, for example. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is not necessary to provide a potential generation circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of the circuit including the transistor T can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved. For example, the fixed potential Vb may be higher than the low power supply potential.

The signal B is a signal for controlling a conduction state or a non-conduction state, for example. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. At this time, the potential V1 and the potential V2 in the signal A may be different from the potential V3 and the potential V4 in the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor T may be almost the same.

When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor T is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B In the case where the transistor is non-conductive only when the potential is V4, the function of a NAND circuit, a NOR circuit, or the like may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including the transistor T is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized.

The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

When a fixed potential is applied to both gates of the transistor T, the transistor T may function as an element equivalent to a resistance element. For example, in the case where the transistor T is an n-channel transistor, the effective resistance of the transistor may be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 8)
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

22A to 22F illustrate electronic devices. These electronic devices include a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, and a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 5008, and the like.

FIG. 22A illustrates a mobile computer which can include a switch 5009, an infrared port 5010, and the like in addition to the above components. FIG. 22B illustrates a portable image reproducing device (eg, a DVD reproducing device) including a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can. FIG. 22C illustrates a goggle type display which can include a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above components. FIG. 22D illustrates a portable game machine that can include the memory medium reading portion 5011 and the like in addition to the above objects. FIG. 22E illustrates a digital camera with a television receiving function, which can include an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like in addition to the above objects. FIG. 22F illustrates a portable game machine that can include the second display portion 5002, the recording medium reading portion 5011, and the like in addition to the above objects.

The electronic devices illustrated in FIGS. 22A to 22F can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying programs or data recorded on the recording medium It can have a function of displaying on the section. Further, in an electronic device having a plurality of display units, one display unit mainly displays image information and another one display unit mainly displays character information, or the plurality of display units consider parallax. It is possible to have a function of displaying a three-dimensional image, etc. by displaying the obtained image. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image, a function for capturing a moving image, a function for correcting a captured image automatically or manually, and a captured image on a recording medium (externally or incorporated in a camera) A function of saving, a function of displaying a photographed image on a display portion, and the like can be provided. Note that the functions of the electronic devices illustrated in FIGS. 22A to 22F are not limited to these, and the electronic devices can have various functions.

FIG. 23A is a top view of the eyeglass-type device 5500, and FIG. 23B is a perspective view thereof.

The eyeglass-type device 5500 includes a plurality of batteries 5501 in a portion (hereinafter also referred to as a temple portion) disposed along the user's temporal region when worn.

The eyeglass device 5500 may include a terminal portion 5504. The battery 5501 can be charged from the terminal portion 5504. A plurality of batteries 5501 are preferably connected to each other. Accordingly, a plurality of batteries 5501 can be charged at the same time using the power supplied from the terminal portion 5504.

Further, the eyeglass-type device 5500 may include a display portion 5502. Further, a control unit 5503 may be included. The controller 5503 can control charging / discharging of the battery 5501 and can generate image data to be displayed on the display portion 5502. In addition, by mounting a chip having a wireless communication function on the controller 5503, data can be transmitted / received to / from the outside.

Alternatively, as illustrated in FIG. 23C, a glasses-type device 5510 that does not include the display portion 5502 may be used. An external display portion 5512 may be attached to the glasses-type device 5510. By attaching an external display portion 5512 to the eyeglass-type device 5510, the distance between the user's eyes and the display portion 5512 can be easily adjusted.

Further, wireless communication and wireless power feeding may be performed between the glasses-type device 5510 and the external display portion 5512.

Note that the structure and method described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

S switch S1 switch S2 switch S3 switch 10 semiconductor device 11 semiconductor device 20 power storage circuit 20_1 power storage circuit 20_2 power storage circuit 20_3 power storage circuit 21 battery 31 switch 31a transistor 32 switch 33 switch 34 switch 35 switch 36 switch 41 switch 41a transistor 42 switch 43 switch 44 switch 45 switch 46 switch 51 switch 51a transistor 52 transistor 53 transistor 60 semiconductor device 61 semiconductor device 63 switch 71 switch 72 switch 73 switch 100 memory cell 101 comparator 102 encoder 103 latch circuit 104 buffer 200 AD conversion circuit 210 sample hold circuit 211 transistor 212 Capacitor element 213 Operan 214 wiring 215 wiring 220 comparison circuit 230 successive approximation register 240 DA conversion circuit 300 phase synchronization circuit 310 phase comparator 320 control circuit 330 DA conversion circuit 340 voltage control oscillation circuit 350 frequency divider 400 storage device 410 memory cell 411 transistor 412 transistor 413 Capacitance element 420 Memory cell array 430 Row selection driver 440 Column selection driver 441 Decoder 442 Latch circuit 443 DA conversion circuit 444 Switch circuit 445 Transistor 446 Transistor 450 AD conversion circuit 700 Substrate 701 Plug 702 Wiring 703 Plug 704 Plug 705 Wiring 707 Wiring 720 Transistor 721 Impurity region 722 Impurity region 723 Channel formation region 724 Gate insulating film 725 Side wall insulating layer 726 Gate electrode 72 Element isolation layer 730 Transistor 731 Insulating film 732 Insulating film 740 Battery 741 Insulating film 742 Insulating film 750 Transistor 751 Impurity region 752 Impurity region 753 Channel forming region 754 Gate insulating film 755 Side wall insulating layer 756 Gate electrode 757 Insulating film 800 Battery 801 Insulating film 802 Positive electrode current collector layer 803 Positive electrode active material layer 804 Solid electrolyte layer 805 Negative electrode active material layer 806 Negative electrode current collector layer 807 Insulating film 808 Wiring 810 Battery 811 Insulating film 820 Battery 830 Battery 900 Transistor 940 Substrate 952 Insulating film 953 Gate insulation Film 954 Insulating film 955 Insulating film 960 Oxide semiconductor 961 Oxide semiconductor 962 Oxide semiconductor 963 Oxide semiconductor 971 Source electrode 972 Drain electrode 973 Gate electrode 974 Electrode 1000 Semiconductor device 1100 Semiconductor device 1200 Semiconductor device 1300 Semiconductor device 5000 Housing 5001 Display unit 5002 Display unit 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support Unit 5013 earphone 5014 antenna 5015 shutter button 5016 image receiving unit 5500 glasses-type device 5501 battery 5502 display unit 5503 control unit 5504 terminal unit 5510 glasses-type device 5512 display unit

Claims (8)

A first power storage circuit, a second power storage circuit, a first switch, and a second switch;
The conduction state of the first switch is controlled by a first signal;
The conduction state of the second switch is controlled by a second signal;
A function of outputting a first potential from the first power storage circuit via the first switch;
A function of outputting a second potential from the second power storage circuit via the second switch;
A semiconductor device having a function of outputting a third potential from the first power storage circuit and the second power storage circuit connected in series through the second switch. In claim 1,
The first power storage circuit or the second power storage circuit has a plurality of batteries,
The plurality of batteries are semiconductor devices connected in series. In claim 1,
The first power storage circuit or the second power storage circuit includes a plurality of batteries and a third switch,
The third switch is connected between the plurality of batteries;
The plurality of batteries are connected in series via a third switch,
The third switch is a semiconductor device which is a transistor including an oxide semiconductor in a channel formation region. In claim 3,
The plurality of batteries are semiconductor devices provided above the transistors. In any one of Claims 2 thru | or 4,
The plurality of batteries are charged by connecting the plurality of batteries in parallel, then applying a fourth potential to the first electrode of the plurality of batteries and a fifth potential to the second electrode of the plurality of batteries. , A semiconductor device that performs by supplying each of them.   A conversion circuit comprising the semiconductor device according to claim 1. A semiconductor device according to claim 1;
An electronic device having a display portion, operation keys, or a sensor. A conversion circuit according to claim 6;
An electronic device having a display portion, operation keys, or a sensor.

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