JP2015170749A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a reduced area.SOLUTION: A semiconductor device comprises a first transistor 490, a second transistor 491, a third transistor 492, a first capacitative element 493 and a second capacitative element 494. The third transistor has a first conductor on an insulator, a first insulator on the first conductor, a semiconductor on the first insulator, a second insulator on the semiconductor, a second conductor on the second insulator and a third conductor and a fourth conductor which are connected to the semiconductor. Either one of a source electrode or a drain electrode of the first transistor 490 is electrically connected with an electrode of one of the second conductor and the first capacitative element 493 of the third transistor 492. And either one of the source electrode or the drain electrode of the second transistor 491 is electrically connected with an electrode of one of the first conductor and the second capacitative element 494 of the third transistor 492.

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, the present invention relates to, for example, a semiconductor, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, or a processor. Alternatively, the present invention relates to a method for manufacturing a semiconductor, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, or a processor. Alternatively, the present invention relates to a method for driving a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, or a processor.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A memory device, a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, an electronic device, and the like may include a semiconductor device.

A combination of a transistor whose channel formation region is made of semiconductor silicon (Si) (hereinafter referred to as an Si transistor) and a transistor whose channel formation region includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). Thus, a semiconductor device that can retain data even after the power is shut off has been attracting attention (see Patent Document 1).

In recent years, with an increase in the amount of data handled, a semiconductor device having a large storage capacity has been demanded. Under such circumstances, the semiconductor device described in Patent Document 1 described above discloses a configuration for storing multi-value data and reading the data.

JP 2012-256400 A

One embodiment of the present invention has at least one of the following problems. Providing a semiconductor device (memory cell) with a reduced area, providing a semiconductor device with improved storage density, providing a semiconductor device with improved storage capacity, providing a miniaturized semiconductor device, Alternatively, a novel semiconductor device is provided.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

(1) One embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor element, and a second capacitor element, and the third transistor includes a first conductor. A first insulator on the first conductor; a semiconductor on the first insulator; a second insulator on the semiconductor; a second conductor on the second insulator; and a second conductor connected to the semiconductor. A first conductor that overlaps the first conductor and does not overlap the second conductor; and a second semiconductor that overlaps the second conductor and does not overlap the first conductor. One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor, and the source electrode of the second transistor Alternatively, one of the drain electrodes is connected to the first conductor and the second capacitor of the third transistor. It is a semiconductor device that is one electrode electrically connected to the element.

(2) Alternatively, according to one embodiment of the present invention, the area of the region between the first region and the second region included in the semiconductor is less than or equal to the area of the first region and less than or equal to the area of the second region. A semiconductor device according to the aspect of (1).

(3) Another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, and the third transistor is an insulator. A first conductor on the first conductor, a first insulator on the first conductor, a semiconductor on the first insulator, a second insulator on the semiconductor, a second conductor on the second insulator, A third conductor and a fourth conductor connected to the semiconductor, and the semiconductor has a third region overlapping the first conductor and a fourth region overlapping the second conductor; The third region and the fourth region do not overlap, and one of the source electrode or the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and one electrode of the first capacitor, One of the source electrode or the drain electrode of the two transistors is connected to the first conductor and the third transistor. Which is one electrode and the semiconductor device is electrically connected to the second capacitive element.

(4) Alternatively, according to one embodiment of the present invention, the area of the region between the third region and the fourth region included in the semiconductor is less than or equal to the area of the first region and less than or equal to the area of the second region. The semiconductor device according to the aspect of (1).

(5) Another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, and the third transistor is an insulator. A first conductor on the first conductor, a first insulator on the first conductor, a semiconductor on the first insulator, a second insulator on the semiconductor, a second conductor on the second insulator, A third conductor and a fourth conductor connected to the semiconductor, wherein the semiconductor includes a third region overlapping the first conductor, a fourth region overlapping the second conductor, a third region, A fifth region overlapping with the four regions, and the area of the fifth region is 25% or less of the area of the third region and 25% or less of the area of the fourth region. One of the source electrode and the drain electrode is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor. Are connected, one of a source electrode and a drain electrode of the second transistor, which is one of the electrodes and electrically the attached semiconductor device of the first conductor and the second capacitive element of the third transistor.

(6) Another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, and the third transistor is an insulator. A first insulator on the first conductor; a first insulator on the first conductor; a semiconductor on the first insulator at a position overlapping the first conductor; a second insulator on the semiconductor; A second conductor in a position overlapping with the semiconductor on the insulator; a third conductor and a fourth conductor connected to the semiconductor; and when viewed from above, an end of the first conductor; The end portions of the second conductor do not overlap, the distance between the end portions of the first conductor and the second conductor is equal to or less than the width of the first conductor, and the width of the second conductor. In the following, one of the source electrode or the drain electrode of the first transistor is connected to the second conductor and the first capacitor of the third transistor. One electrode of the element is electrically connected, and one of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and one electrode of the second capacitor element. It is a semiconductor device.

(7) Another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, and the third transistor includes an insulator. A first insulator on the first conductor; a first insulator on the first conductor; a semiconductor on the first insulator at a position overlapping the first conductor; a second insulator on the semiconductor; A second conductor that is located on the insulator and overlapping the semiconductor; and a third conductor and a fourth conductor that are connected to the semiconductor. The first conductor and the second conductor are: The area of the overlapping region is 25% or less of the area of the first conductor and 25% or less of the area of the second conductor. The source electrode or the drain electrode of the first transistor Is one of the second conductor of the third transistor and the first capacitive element. The semiconductor device is electrically connected to the electrode, and one of the source electrode and the drain electrode of the second transistor is electrically connected to one electrode of the first conductor and the second capacitor of the third transistor. .

(8) Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, and the third transistor includes an insulator. A first insulator on the first conductor; a first insulator on the first conductor; a semiconductor on the first insulator at a position overlapping the first conductor; a second insulator on the semiconductor; A second conductor in a position overlapping with the semiconductor on the insulator; a third conductor and a fourth conductor connected to the semiconductor; and when viewed from above, an end of the first conductor; The ends of the second conductor are aligned, and one of the source electrode or the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and one electrode of the first capacitor, One of the source electrode or drain electrode of the two transistors is connected to the third transistor. Which is one electrode and the semiconductor device is electrically connected to the first conductor and the second capacitive element register.

(9) Alternatively, according to one embodiment of the present invention, the channel formation region of the first transistor is formed using an oxide semiconductor, the channel formation region of the second transistor is formed using an oxide semiconductor, and the semiconductor included in the second transistor Is a semiconductor device according to any one of (1) to (8), which is an oxide semiconductor.

(10) Alternatively, in one embodiment of the present invention, the third transistor is stacked over the second transistor, and the first transistor is stacked over the third transistor. A semiconductor device according to an aspect.

(11) Alternatively, according to one embodiment of the present invention, the first transistor is stacked over the second transistor, and the channel formation region of the first transistor and the channel formation region of the second transistor overlap with each other. 9) A semiconductor device according to any one of the aspects.

(12) Alternatively, according to one embodiment of the present invention, the first transistor, the second transistor, the third transistor, the first capacitor element, and the second capacitor element are in any of 16 values to 1024 values. A semiconductor device according to any one of (1) to (11).

(13) Another embodiment of the present invention is an RFID tag including the semiconductor device according to any one of the embodiments (1) to (12) and an antenna.

(14) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (12) and a printed wiring board.

A semiconductor device (memory cell) with a reduced area can be provided. Alternatively, a semiconductor device with improved memory density can be provided. Alternatively, a semiconductor device with improved storage capacity can be provided. Alternatively, a miniaturized semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 10 is a circuit diagram illustrating a semiconductor device (memory cell) according to one embodiment of the present invention. FIG. 6 is a top view of a semiconductor device (memory cell) according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device (memory cell) according to one embodiment of the present invention. 6A and 6B illustrate voltages related to operation of a memory cell. 6A and 6B illustrate voltages related to operation of a memory cell. The circuit diagram which shows a memory cell array. FIG. 9 is a timing chart illustrating a memory cell write operation. FIG. 10 is a timing chart illustrating a memory cell read operation. 1 is a block diagram illustrating a storage device. FIG. 10 is a cross-sectional view illustrating a transistor. FIG. 10 is a cross-sectional view illustrating a transistor. Sectional TEM image and local Fourier transform image of an oxide semiconductor. The figure which shows the nano beam electron diffraction pattern of an oxide semiconductor, and the figure which shows an example of a transmission electron diffraction measuring apparatus. The figure which shows an example of the structural analysis by a transmission electron diffraction measurement, and a plane TEM image. Sectional drawing which shows lamination | stacking of a semiconductor, and the figure which shows a band structure. FIG. 10 is a block diagram illustrating a CPU according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating an RFID according to one embodiment of the present invention. FIG. 6 illustrates an electronic component according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

In the embodiment shown below, unless otherwise specified, as an insulator, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, An insulator containing one or more of zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Alternatively, a resin may be used as the insulator. For example, a resin containing polyimide, polyamide, acrylic, silicone, or the like may be used. By using a resin, it may not be necessary to planarize the upper surface of the insulator. In addition, since the resin can form a thick film in a short time, productivity can be increased. As the insulator, an insulator containing aluminum oxide, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide is preferably a single layer or a stacked layer. Use it.

In the embodiment shown below, unless otherwise specified, as the conductor, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, A conductor including one or more of gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, or tungsten may be used as a single layer or a stacked layer. For example, it may be an alloy film or a compound film, and includes a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, titanium and nitrogen. A conductor or the like may be used.

In this specification, when it is described that A has a region having a concentration B, for example, when the entire depth direction in a region with A is a concentration B, the average value in the depth direction in a region with A Is the density B, the median value in the depth direction in the area with A is the density B, the maximum value in the depth direction in the area with A is the density B, the depth in the area with A The case where the minimum value in the direction is the density B, the convergence value in the depth direction in a certain area of A is the density B, and the area where a probable value of A itself is obtained in the measurement is the density B is included. .

In addition, in this specification, when A is described as having a region having a size B, a length B, a thickness B, a width B, or a distance B, for example, the entire region in which A is a size B, a length If the average value in a region of A is size B, length B, thickness B, width B, or distance B when the thickness is B, thickness B, width B, or distance B, in the region of A When the median is size B, length B, thickness B, width B, or distance B, the maximum value in a region of A is size B, length B, thickness B, width B, or distance B. In some cases, when the minimum value in a region of A is size B, length B, thickness B, width B, or distance B, the convergence value in a region of A is size B, length B, thickness In the case of B, width B, or distance B, the region where a probable value of A itself is obtained in measurement is size B, length B, thickness B, incl. Such as when the width B or distance B.

Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Note that the functions of the “source” and “drain” of the transistor may be interchanged when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

Note that the arrangement of each circuit block in the drawing specifies the positional relationship for the sake of explanation, and even if it is shown in the drawing to realize different functions in different circuit blocks, the same circuit is used in an actual circuit or region. In some cases, different functions can be realized in the same area. In addition, the function of each circuit block in the drawing is to specify the function for explanation. Even if the function is shown as one circuit block, in an actual circuit or region, processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided.

(Embodiment 1)
In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

FIG. 1 illustrates an example of a circuit configuration of a semiconductor device according to one embodiment of the present invention.

In the following, the semiconductor device illustrated in FIG. 1 has a function as a memory cell. Hereinafter, the semiconductor device may be described as a semiconductor device (memory cell) or simply as a memory cell.

The memory cell 500 includes a transistor 490, a transistor 491, a transistor 492, a capacitor 493, and a capacitor 494.

The transistor 492 includes a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The first gate electrode and the second gate electrode are arranged above and below across the channel formation region. In addition, the first gate electrode and the second gate electrode may be partially overlapped but are shifted from each other. In this specification, such a transistor 492 is represented by a symbol illustrated in FIG. In the transistor 492, a channel formation region overlaps the first gate electrode but does not overlap the second gate electrode, a second region overlaps the second gate electrode but does not overlap the first gate electrode, and It is preferable to have.

Alternatively, in the transistor 492, the channel formation region preferably includes a third region overlapping with the first gate electrode and a fourth region overlapping with the second gate electrode, and the third region and the fourth region do not overlap.

When the third region and the fourth region do not overlap, it is preferable that the distance between the third region and the fourth region is small. When the width and interval of the third region and the width of the fourth region are defined with respect to the direction in which the third region and the fourth region are arranged, the interval is equal to or less than the width of the third region and / or It is preferable that the width is not more than 4 regions. More preferably, the interval is ½ or less of the width of the third region and / or ½ or less of the width of the fourth region.

Alternatively, the first gate electrode and the second gate electrode may be positioned at an interval when viewed from above. When the width and interval of the first gate electrode and the width of the second gate electrode are defined in the direction in which the first gate electrode and the second gate electrode are arranged, the interval is equal to or less than the width of the first gate electrode. And / or less than the width of the second gate electrode. More preferably, the interval is 1/2 or less of the width of the first gate electrode and / or 1/2 or less of the width of the second gate electrode.

Alternatively, when viewed from above, the end portion of the first gate electrode and the end portion of the second gate electrode do not overlap, and the interval between the end portion of the first gate electrode and the end portion of the second gate electrode is It is preferably less than the width of the first gate electrode and / or less than the width of the second gate electrode. More preferably, the interval is 1/2 or less of the width of the first gate electrode and / or 1/2 or less of the width of the second gate electrode.

Alternatively, the third region and the fourth region may partially overlap. A partially overlapped region (also referred to as a fifth region) is preferably small. The region preferably has an area of ½ or less of the first region, and has an area of ½ or less of the second region, and more preferably ¼ or less of the first region. It has an area and has an area of 1/4 or less of the second region.

Alternatively, the first gate electrode and the second gate electrode have regions overlapping each other, and the area of the overlapping region is preferably 50% or less of the area of the first gate electrode, and the second gate electrode Is less than 50% of the area of the first gate electrode, more preferably less than 25% of the area of the first gate electrode and less than 25% of the area of the second gate electrode.

Alternatively, when viewed from above, the end portion of the first gate electrode and the end portion of the second gate electrode may be aligned.

The transistor 492 having the above structure is turned on or off according to the potential of the first gate electrode and the potential of the second gate electrode. When the potential of the first gate electrode becomes higher than Vth1, a channel is formed in the channel formation region controlled by the first gate electrode, or carriers are induced. Alternatively, when the potential of the first gate electrode is higher than Vth1, a channel is formed in the third region included in the channel formation region, or carriers are induced. Alternatively, when the potential of the first gate electrode is higher than Vth1, a channel is formed in the first region included in the channel formation region, or carriers are induced. On the other hand, when the potential of the second gate electrode becomes higher than Vth2, a channel is formed in the channel formation region controlled by the second gate electrode or carriers are induced. Alternatively, when the potential of the second gate electrode becomes higher than Vth2, a channel is formed in the fourth region included in the channel formation region, or carriers are induced. Alternatively, when the potential of the second gate electrode is higher than Vth2, a channel is formed in the second region included in the channel formation region or carriers are induced. As described above, the transistor 492 has two threshold voltages of Vth1 and Vth2. Vth1 is a threshold voltage related to the first gate electrode, and Vth2 is a threshold voltage related to the second gate electrode. A channel formation region (or first region or third region) controlled by the first gate electrode and a channel formation region (or second region or fourth region) controlled by the second gate electrode are sources. Since the transistor 492 is positioned in series between the electrode and the drain electrode, the transistor 492 has a potential difference between the first gate electrode and the source or drain electrode larger than Vth1, and the second gate electrode and the source or drain electrode. Only when the potential difference is larger than Vth2, the conductive state is established.

It can be said that the transistor 492 has a function equivalent to a circuit in which two transistors, a transistor having a threshold voltage of Vth1 and a transistor having a threshold voltage of Vth2, are connected in series.

Memory cell 500 is connected to write word lines WW1, WW2, read word lines RW1, RW2, bit line BL, and source line SL.

One of a source electrode and a drain electrode of the transistor 491, one of the electrodes of the capacitor 494, and the first gate electrode of the transistor 492 are electrically connected to each other. This connected portion is also called a floating node FN1. One of a source electrode and a drain electrode of the transistor 490, one of the electrodes of the capacitor 493, and the second gate electrode of the transistor 492 are connected. This connected portion is also called a floating node FN2.

The gate electrode of the transistor 491 is connected to the write word line WW1. The other of the source electrode and the drain electrode of the transistor 491 is connected to the bit line BL. The other electrode of the capacitor 494 is connected to the read word line RW1. The gate electrode of the transistor 490 is connected to the write word line WW2. The other of the source electrode and the drain electrode of the transistor 490 is connected to the bit line BL. The other electrode of the capacitor 493 is connected to the read word line RW2. One of a source electrode and a drain electrode of the transistor 492 is connected to the source line SL. The other of the source electrode and the drain electrode of the transistor 492 is connected to the bit line BL.

Memory cell 500 is a circuit that stores information by holding potentials applied to floating node FN1 and floating node FN2. Alternatively, the memory cell 500 is a circuit that stores information by holding charges accumulated in the floating node FN1 and the floating node FN2. By holding various potentials (or charges or states) in the floating node FN1 and the floating node FN2, information of four values (2 bits) or more can be stored.

Specifically, information of 4 values (2 bits), information of 16 values (4 bits), information of 64 values (6 bits), information of 256 values (8 bits) or 1024 values (10 bits) are stored. (Or hold). For example, by holding two states in the floating node FN1 and two states in the floating node FN2, quaternary (= 2 × 2) information can be stored. For example, by holding 4 states in the floating node FN1 and 4 states in the floating node FN2, information of 16 values (= 4 × 4) can be stored. For example, by holding 8 states in the floating node FN1 and 8 states in the floating node FN2, information of 64 values (= 8 × 8) can be stored. For example, by holding 16 states in the floating node FN1 and 16 states in the floating node FN2, information of 256 values (= 16 × 16) can be stored. For example, by holding 32 states in the floating node FN1 and 32 states in the floating node FN2, information of 1024 values (= 32 × 32) can be stored. As described above, the memory cell 500 can store information on a value given by the product of the number of states of two floating nodes, so that the storage density can be improved.

Note that the number of states that can be stored is not limited to these values, and states of four values to 1024 values can be stored (or held). By holding k1 states in the floating node FN1 and k2 states in the floating node FN2, information of k1 × k2 values can be stored. Furthermore, a part of the state can also be used for parity check and error correction. In this case, the information has a value smaller than the k1 × k2 value.

The transistor 491 is a transistor that controls supply of a potential to the floating node FN1. Alternatively, the transistor 491 is a transistor that charges and discharges charge to and from the floating node FN1. The transistor 491 is a transistor having a function of writing. The transistor 490 is a transistor that controls supply of a potential to the floating node FN2. Alternatively, the transistor 490 is a transistor that charges and discharges charge to and from the floating node FN2. The transistor 490 is a transistor having a function of performing writing. The capacitor 494 has a function of changing the potential of the floating node FN1 by capacitive coupling. The capacitor 493 has a function of changing the potential of the floating node FN2 by capacitive coupling. The transistor 492 becomes conductive or nonconductive according to the potentials of the floating node FN1 and the floating node FN2. Alternatively, the source electrode or the drain electrode of the transistor 492 may have a predetermined potential in accordance with the potentials of the floating node FN1 and the floating node FN2. For example, the potential of the source electrode or the drain electrode may be different from the potential of the floating node FN1 by the threshold voltage Vth1, or may be different from the potential of the floating node FN2 by the threshold voltage Vth2. By detecting such a state, information held in the memory cell 500 can be read. The transistor 492 is a transistor having a function of reading data.

The write word line WW1 is supplied with a signal for controlling the conduction state of the transistor 491. The write word line WW2 is supplied with a signal line for controlling the conduction state of the transistor 490. The write word line RW1 is supplied with a signal line for controlling the potential of the floating node FN1 through capacitive coupling by the capacitor 494. The write word line RW2 is supplied with a signal line for controlling the potential of the floating node FN2 through capacitive coupling by the capacitive element 493. The source line SL and the bit line BL are supplied with signals for controlling potentials of one and the other of the source electrode and the drain electrode of the transistor 492, respectively. Alternatively, an output signal from the memory cell 500 is supplied to the bit line BL. In that case, the data read from the memory cell 500 is supplied to the bit line BL. Alternatively, the potential applied to the floating node FN1 when the transistor 491 is turned on is applied to the bit line BL. Alternatively, the potential applied to the floating node FN2 when the transistor 490 is turned on is applied to the bit line BL. In that case, data to be written to the memory cell 500 is supplied to the bit line BL.

The semiconductor device may have a memory cell array in which the memory cells 500 are arranged in an array (or matrix).

The transistor 490 may be an n-channel type or a p-channel type. The transistor 491 may be an n-channel type or a p-channel type. The transistor 492 may be an n-channel type or a p-channel type.

As the transistor 490 and the transistor 491, a transistor having a small drain current (also referred to as a leakage current) in an off state can be used. For example, the drain current in the off state is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 × 10 ⁻²⁴ A or less, or 85 at room temperature (about 25 ° C.). It is 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at a temperature. As an example, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region (hereinafter also referred to as a transistor including an oxide semiconductor) can be used.

By using a transistor with a small leakage current as the transistor 490, the charge accumulated in the floating node FN2 can be held for a long time. By using a transistor with a small leakage current as the transistor 491, the charge accumulated in the floating node FN1 can be held for a long time. In other words, the memory cell 500 functions as a memory circuit that can hold data for a long time without supply of power. Alternatively, it has a function as a nonvolatile memory circuit.

As the transistors 490 to 492, transistors with high withstand voltage can be used. That is, a transistor with a high gate breakdown voltage and a high drain breakdown voltage can be used. For example, a thick gate insulator of 5 nm or more, preferably 7 nm or more, more preferably 10 nm or more can be used. A semiconductor with an energy gap of 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, more preferably 3 eV to 3.5 eV can be used for the channel formation region. As an example, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region can be used.

By using transistors with high withstand voltage as the transistors 490 to 492, higher potentials can be held in the floating node FN1 and the floating node FN2. The memory cell 500 can store more different states and more information by holding a wide range of potentials from a low potential to a high potential in the floating node. Therefore, a higher storage density can be realized. For example, by storing 16 states in the floating node FN1 and the floating node FN2, the memory cell 500 can store 256-value information.

In the transistor 492, the first gate electrode and the second gate electrode are arranged above and below and shifted from each other with the channel formation region interposed therebetween. By disposing the first gate electrode and the second gate electrode above and below the channel formation region, the first gate electrode and the second gate electrode can be disposed in a region smaller than that of the same layer, and the memory cell can be reduced. Further, the first gate electrode and the second gate electrode are arranged so as to be shifted from each other, whereby the conduction state of the transistor 492 can be controlled independently. As a result, the memory cell 500 can store information on a value given by the product of the number of states of two floating nodes, and can improve the storage density.

Further, the transistors 490 to 492 are stacked, the transistor 490 is disposed on the same side as the second gate electrode when viewed from the channel formation region of the transistor 492, and the transistor 491 is viewed from the channel formation region of the transistor 492. Therefore, it may be arranged on the same side as the first gate electrode. By doing so, the memory cell 500 can be reduced. Further, the memory cell 500 can be reduced by arranging the transistor 490 and the transistor 491 so as to overlap each other. Further, the memory cell 500 can be reduced by arranging the transistor 490 and the transistor 492 so as to overlap each other. Further, the memory cell 500 can be reduced by arranging the transistor 491 and the transistor 492 so as to overlap each other.

The transistor A and the transistor B overlap each other because at least a gate electrode, a drain electrode (or a drain region), or a part of a source electrode (or a source region) included in the transistor A is a gate electrode included in the transistor B. , Overlaps with a part of the drain electrode (or drain region) or the source electrode (or source region). Alternatively, the transistor A includes a gate electrode, a drain electrode (or drain region), and a region including a source electrode (or source region), and the transistor B includes a gate electrode, a drain electrode (or drain region), and a source electrode (or The region including the source region is at least partially overlapped. Alternatively, the region including the component of the transistor A and the region including the component of the transistor B are at least partially overlapped.

Hereinafter, a memory cell in which the transistors 490 to 492 are stacked is described.

A configuration of the memory cell 500 having the circuit configuration shown in FIG. 1 will be described with reference to FIGS.

2 and 3, in order to facilitate understanding, a part of an insulator or the like is omitted, and conductors and the like formed in the same layer are given the same hatching pattern.

FIG. 2 is a top view illustrating an example of a structure of the memory cell 500. FIG. 2A illustrates a top view of a region including the bit line BL in the memory cell 500, and FIG. FIG. 2C illustrates a top view of a region including the transistor 491 and the capacitor 494 in the memory cell 500, and FIG. 2C illustrates a top view of a region including the transistor 492 in the memory cell 500. 2D is a top view of a region including the transistor 490 and the capacitor 493 in the memory cell 500. FIG. An area 501 indicates an area occupied by the memory cell 500.

FIG. 3 is a cross-sectional view showing an example of the configuration of the memory cell 500. 3 is a cross-sectional view taken along one-dot chain line A1-A2 in FIGS. 2A to 3D, and in the center of FIG. A cross section taken along the alternate long and short dash line B1-B2 is shown, and on the right side of the figure, a cross section taken along the alternate long and short dash line C1-C2 in FIGS. 2A to 2D is shown.

A memory cell 500 illustrated in FIGS. 2 and 3 includes a transistor 490, a transistor 491, a transistor 492, a capacitor 493, and a capacitor 494, and configures the memory cell having the circuit configuration illustrated in FIG. Here, the transistors 490 to 492 are described as examples using transistors including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

First, a device structure will be described with reference to a cross-sectional view of the memory cell 500 shown in FIG.

3 includes the substrate 400, the transistor 490 and the capacitor 493 over the substrate 400, the insulator 444 over the transistor 490 and the capacitor 493, the transistor 492 over the insulator 444, and the transistor 492. And the transistor 491 and the capacitor 494 over the insulator 446. Note that the insulators 444 and 446 are preferably insulators having a function of blocking oxygen and hydrogen.

The substrate 400 may be a semiconductor substrate using a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Good. An amorphous semiconductor or a crystalline semiconductor may be used for the semiconductor substrate, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. Moreover, a glass substrate may be sufficient. Further, an element substrate in which a semiconductor element is formed on a semiconductor substrate or a glass substrate may be used.

The transistor 490 includes the semiconductor 406a, the semiconductor 406b over the semiconductor 406a, the side surface of the semiconductor 406a, the conductor 416a and the conductor 416b in contact with the top surface and the side surface of the semiconductor 406b, the side surface of the semiconductor 406a, the top surface of the semiconductor 406b, The semiconductor device includes a side surface, a top surface and a side surface of the conductor 416a, a semiconductor 406c in contact with the top surface and the side surface of the conductor 416b, an insulator 411 over the semiconductor 406c, and a conductor 426 over the insulator 411.

The conductor 416a and the conductor 416b function as a source electrode and a drain electrode of the transistor 490. The insulator 411 functions as a gate insulator of the transistor 490. The conductor 426 functions as a gate electrode of the transistor 490.

As shown in FIG. 3, the side surfaces of the conductors 416a and 416b are in contact with the side surfaces of the semiconductor 406b. The conductor 426 has a structure in which the channel width direction of the semiconductor 406b is electrically surrounded, and has a structure in which the semiconductor 406b is surrounded not only on the top surface but also on the side surface. Such a transistor structure is called a surround channel (s-channel) structure. The conductor 404 preferably has a structure extending to a position below the semiconductor 406b.

When the transistor has an s-channel structure, the channel formation region can be easily controlled by the gate electric field with respect to the side surface of the semiconductor 406b. In the structure in which the conductor 426 extends below the semiconductor 406b, the controllability is further improved. As a result, the subthreshold swing value (also referred to as an S value) of the transistor 490 can be reduced, and the off-state current of the transistor 490 can be reduced.

The capacitor 493 includes a conductor 416a, a semiconductor 409c over the conductor 416a, an insulator 414 over the semiconductor 409c, and a conductor 429 over the insulator 414.

The conductor 416a functions as one of the electrodes of the capacitor 493. The insulator 414 functions as a dielectric of the capacitor 493. The conductor 429 functions as the other electrode of the capacitor 493.

The transistor 492 includes a conductor 423 over the insulator 444, an insulator 434 over the conductor 423, semiconductors 408a, 408b, and 408c over the insulator 434, an insulator 413 over the semiconductor, and an insulator A conductor 428 over 413, and a conductor 418a and a conductor 418b connected to the semiconductor are included.

Alternatively, the transistor 492 includes the conductor 423, the insulator 434 over the conductor 423, the semiconductor 408a over the insulator 434, the semiconductor 408b over the semiconductor 408a, the side surface of the semiconductor 408a, and the top and side surfaces of the semiconductor 408b. Conductor 418a and conductor 418b in contact with each other, a side surface of semiconductor 408a, a top surface and a side surface of semiconductor 408b, a top surface and a side surface of conductor 418a, a semiconductor 408c in contact with a top surface and a side surface of conductor 418b, and semiconductor 408c An insulator 413 and a conductor 428 over the insulator 413 are included.

Side surfaces of the conductor 418a and the conductor 418b are in contact with side surfaces of the semiconductor 408b. In addition, the conductor 428 has a structure in which the channel width direction of the semiconductor 408b is electrically surrounded, and has a structure in which the semiconductor 408b is surrounded not only on the top surface but also on the side surface. That is, it has an s-channel structure.

The conductor 418a and the conductor 418b function as a source electrode and a drain electrode of the transistor 492. The insulator 413 functions as a gate insulator of the transistor 492. The conductor 428 functions as a gate electrode (referred to as a first gate electrode) of the transistor 492. The insulator 434 functions as a gate insulator of the transistor 492. The conductor 423 functions as a gate electrode (referred to as a second gate electrode) of the transistor 492.

In the transistor 492, the semiconductor 408b includes a first region that overlaps with the conductor 423 and does not overlap with the conductor 428, and a second region that overlaps with the conductor 428 and does not overlap with the conductor 423.

In the transistor 492 illustrated in FIGS. 2 and 3, the conductor 423 and the conductor 428 are partially overlapped or substantially aligned when viewed from above. In the present invention, the positional relationship between the conductor 423 and the conductor 428 is not limited to this. When the conductor 423 and the conductor 428 overlap with each other when viewed from above, capacitive coupling between the conductor 423 and the conductor 428 may occur, which may affect the operation of the memory cell 500. Therefore, it is preferable that the overlap is small. Further, when the conductor 423 and the conductor 428 are spaced apart from each other when viewed from above, the semiconductor 408b located between the conductor 423 and the conductor 428 has the transistor 492 in a conductive state. Even in such a case, the resistance may be high, and the operation of the memory cell 500 may be affected. Therefore, the interval is preferably small. Therefore, the end portion of the conductor 423 and the end portion of the conductor 428 are preferably aligned.

In the transistor 492, the semiconductor 408b includes a third region overlapping with the conductor 423 and a fourth region overlapping with the conductor 428, and the third region and the fourth region may not overlap.

When the third region and the fourth region do not overlap, it is preferable that the distance between the third region and the fourth region is small. When the width and interval of the third region and the width of the fourth region are defined in the direction in which the third region and the fourth region are arranged, the interval is equal to or smaller than the width of the third region and / or The width is preferably equal to or smaller than the width of the region. More preferably, the interval is ½ or less of the width of the third region and / or ½ or less of the width of the fourth region.

Alternatively, the conductor 423 and the conductor 428 may be spaced apart from each other when viewed from above. When the width and interval of the conductor 423 and the width of the conductor 428 are defined with respect to the direction in which the conductor 423 and the conductor 428 are arranged, the interval is equal to or less than the width of the conductor 423 and / or The width is preferably equal to or less than the width of the conductor 428. More preferably, the interval is ½ or less of the width of the conductor 423 and / or ½ or less of the width of the conductor 428.

Alternatively, when viewed from above, the end portion of the conductor 423 and the end portion of the conductor 428 do not overlap with each other, and the distance between the end portion of the conductor 423 and the end portion of the conductor 428 is different from that of the conductor 423. It is preferably less than the width and / or less than the width of the conductor 428. More preferably, the interval is ½ or less of the width of the conductor 423 and / or ½ or less of the width of the conductor 428.

Alternatively, the third region and the fourth region may partially overlap. The partially overlapped region is preferably small. The region preferably has an area of ½ or less of the first region, and has an area of ½ or less of the second region, and more preferably ¼ or less of the first region. It has an area and has an area of 1/4 or less of the second region.

Alternatively, the conductor 423 and the conductor 428 have regions that overlap with each other, and the area of the overlapping region is preferably 50% or less of the area of the conductor 423 and 50% of the area of the conductor 428. Or less, more preferably 25% or less of the area of the conductor 423 and 25% or less of the area of the conductor 428.

Alternatively, the end portion of the conductor 423 and the end portion of the conductor 428 may be aligned when viewed from above.

With such a structure, the transistor 492 can have a smaller area than a transistor in which the gate electrode is formed of the same layer. As a result, the memory cell may be able to be reduced. Further, with such a structure, the conduction state of the transistor 492 can be independently controlled by the two gate electrodes. As a result, the memory cell 500 can store information on a value given by the product of the number of states of two floating nodes, and can improve the storage density.

The transistor 491 includes a semiconductor 407a, a semiconductor 407b over the semiconductor 407a, a side surface of the semiconductor 407a, a conductor 417a and a conductor 417b in contact with the top surface and the side surface of the semiconductor 407b, a side surface of the semiconductor 407a, a top surface of the semiconductor 407b, The semiconductor device has a side surface, a top surface and a side surface of the conductor 417a, and a semiconductor 407c in contact with the top surface and the side surface of the conductor 417b, an insulator 412 over the semiconductor 407c, and a conductor 427 over the insulator 412.

The conductors 417a and 417b function as a source electrode and a drain electrode of the transistor 491. The insulator 412 functions as a gate insulator of the transistor 491. The conductor 427 functions as a gate electrode of the transistor 491.

Side surfaces of the conductor 417a and the conductor 417b are in contact with side surfaces of the semiconductor 407b. In addition, the conductor 427 has a structure in which the channel width direction of the semiconductor 407b is electrically surrounded, and the semiconductor 407b has a structure in which not only the upper surface but also the side surface is surrounded. That is, it has an s-channel structure.

The capacitor 494 includes a conductor 417a, a semiconductor 410c over the conductor 417a, an insulator 415 over the semiconductor 410c, and a conductor 430 over the insulator 415.

The conductor 417a functions as one of the electrodes of the capacitor 493. The insulator 415 functions as a dielectric of the capacitor 494. The conductor 430 functions as the other electrode of the capacitor 494.

In this manner, by using a transistor including the semiconductors 406a, 406b, and 406c as the transistor 490, excellent characteristics as described below can be obtained. Specifically, excellent subthreshold characteristics and extremely small off-current can be obtained. In addition, a memory cell with a reduced area can be obtained by using a fine transistor. Note that the following description applies not only to the transistor 490 but also to the transistor 491 and / or the transistor 492. Further, the present invention is applied not only to the semiconductor 407a but also to the semiconductor 408a and / or the semiconductor 409a. Further, the present invention is applied not only to the semiconductor 407b but also to the semiconductor 408b and / or the semiconductor 409b. Further, the present invention is applied not only to the semiconductor 407c but also to the semiconductor 408c and / or the semiconductor 409c.

In the case where the transistor 490 is an accumulation type in which electrons are a majority carrier, an electric field extending from a region in contact with the source electrode and the drain electrode of the semiconductor 406b to a channel formation region is shielded at a short distance; Easy to control.

In addition, by forming a transistor on an insulating surface, unlike the case where a semiconductor substrate is used as a channel formation region as it is, no parasitic capacitance is formed between the gate electrode and the body or the semiconductor substrate. Becomes easier.

When the transistor has an s-channel structure, the channel formation region can be easily controlled by the gate electric field with respect to the side surface of the semiconductor 406b. In the structure in which the conductor 426 extends below the semiconductor 406b, the controllability is further improved. As a result, the subthreshold swing value (also referred to as an S value) of the transistor 490 can be reduced, and the off-state current of the transistor 490 can be reduced.

By using a s-channel structure as the transistor structure, good electrical characteristics can be obtained even in a fine transistor. By miniaturization of a transistor, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor 490 has a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor 490 preferably has a channel width of 40 nm or less, more preferably 30 nm or less. More preferably, it has a region of 20 nm or less.

When the transistor has an s-channel structure, a channel may be formed in the entire semiconductor 406b (bulk). Therefore, the thicker the semiconductor 406b, the larger the channel formation region. For example, the semiconductor 406b may have a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used. With such a structure, in the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) during conduction can be increased.

Since the transistor described above has high resistance to the short channel effect, the gate insulator can be made thicker than a conventional transistor using silicon or the like. For example, even in a fine transistor with a channel length and a channel width of 50 nm or less, a thick gate insulator of 5 nm or more, preferably 7 nm or more, more preferably 10 nm or more may be used. Increasing the thickness of the gate insulator may reduce the leakage current through the gate insulator. As a result, the retention characteristics in the memory cell are improved. In addition, by increasing the thickness of the gate insulator, the breakdown voltage of the gate insulator can be increased, and the transistor can be driven with a higher gate voltage. Therefore, a higher voltage can be held in the floating node, more states can be held, and the storage density can be increased.

In addition, at least a part (or all) of the conductor 416a (and / or the conductor 416b) is at least a part (or a part) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor layer such as the semiconductor 406b. All). The semiconductor 406b in contact with the semiconductor 406b may form a donor level when hydrogen enters an oxygen-deficient site and has an n-channel conductive region. Incidentally, there may be referred to a state that has entered the hydrogen site of the oxygen deficiency and V _{O H.} As a result, a good on-current can be obtained by the current flowing through the n-channel conductive region.

As the oxide semiconductor, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) described later is preferably used. The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts. In particular, it is preferable to increase the CAAC ratio described later. The CAAC ratio is a ratio of a region where a CAAC-OS diffraction pattern is observed in a certain range. By increasing the CAAC ratio, for example, defects can be reduced. Further, for example, carrier scattering can be reduced. In addition, a CAAC-OS with few impurities can be realized; for example, extremely low off-state current characteristics can be realized. For example, in the case of a high-quality CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and further preferably 95% or more and 100% or less.

In addition, it is effective to reduce the impurity concentration in the semiconductor 406b so that the oxide semiconductor is intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × 10 10. It indicates less than ¹³ / cm ³ . In an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density.

A transistor including a substantially intrinsic oxide semiconductor has low carrier density, and thus has less electrical characteristics with a negative threshold voltage. In addition, a transistor including the oxide semiconductor has few carrier traps in the oxide semiconductor, and thus has a small change in electrical characteristics and has high reliability. In addition, a transistor including the oxide semiconductor can have extremely low off-state current.

For example, the drain current when the transistor including an oxide semiconductor is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 × at room temperature (about 25 ° C.). It can be 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at 85 ° C. Note that an off state of a transistor means a state where a gate voltage is lower than a threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold voltage, the transistor is turned off.

The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 406a or the semiconductor 406c may be used. Alternatively, a four-layer structure including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406, and the semiconductor 406c above or below the semiconductor 406a or above or below the semiconductor 406c may be employed. Alternatively, an n-layer structure including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406, and the semiconductor 406c in any two or more positions over the semiconductor 406a, under the semiconductor 406a, over the semiconductor 406c, and under the semiconductor 406c. (N is an integer of 5 or more).

Further, a stacked structure between devices will be described with reference to a cross-sectional view of the memory cell 500 illustrated in FIG.

A memory cell 500 illustrated in FIG. 3 includes a substrate 400, an insulator 442 over the substrate 400, an insulator 432 over the insulator 442, a transistor 490 and a capacitor 493 over the insulator 432, and a transistor 490 and a capacitor. An insulator 452 over 493, an insulator 462 over the insulator 452, an insulator 444 over the insulator 462, an insulator 434 over the insulator 444, a transistor 492 over the insulator 434, and a transistor 492 over The insulator 454, the insulator 464 on the insulator 454, the insulator 446 on the insulator 464, the insulator 436 on the insulator 446, the transistor 491 and the capacitor 494 on the insulator 436, and the transistor 491 and the capacitor 494, an insulator 456, an insulator 466 on the insulator 456, and a conductor 480 on the insulator 466 It has a. The insulator is appropriately provided with an opening, and a conductor (also referred to as a via) is provided in the opening. The plurality of conductors are appropriately connected through the conductors. One or more layers of insulators and conductors may be further provided over the conductor 480.

The conductor 480 has a region functioning as the bit line BL. The conductor 430 has a function as an electrode of the capacitor 494 and a function as a read word line RW1. The conductor 427 has a function as a gate electrode of the transistor 491 and a function as a write word line WW1. The conductor 429 has a function as an electrode of the capacitor 493 and a function as a read word line RW2. The conductor 426 has a function as a gate electrode of the transistor 490 and a function as a write word line WW2. Note that the conductor 418a is connected to a source line SL (not shown).

The same conductor (conductor 417a) is used for one of a source electrode or a drain electrode of the transistor 491 and one electrode of the capacitor 494. The transistor 492 is electrically connected to the first gate electrode (conductor 428). The same conductor (conductor 416a) is used for one of a source electrode or a drain electrode of the transistor 490 and one electrode of the capacitor 493. The transistor 492 is electrically connected to the second gate electrode (conductor 423).

The bit line (conductor 480), the other of the source and drain electrodes of the transistor 491 (conductor 417b), the other of the source and drain electrodes of the transistor 492 (conductor 418b), and the source or drain of the transistor 490 The other electrode (conductor 416b) is electrically connected.

The transistor 492 is stacked over the transistor 490, and the transistor 491 is stacked over the transistor 492.

The channel formation region of the transistor 491 and the channel formation region of the transistor 490 overlap.

That is, the transistors 490 to 492 are stacked, the transistor 490 is disposed on the same side as the second gate electrode (conductor 423) when viewed from the channel formation region of the transistor 492, and the transistor 491 is connected to the transistor 492. By disposing on the same side as the first gate electrode (conductor 428) as viewed from the channel formation region, the memory cell 500 can be reduced. Further, the memory cell 500 can be reduced by arranging the transistor 490 and the transistor 491 so as to overlap each other. Further, the memory cell 500 can be reduced by arranging the channel formation region of the transistor 490 and the channel formation region of the transistor 491 so as to overlap each other. Further, the memory cell 500 can be reduced by arranging the transistor 490 and the transistor 492 so as to overlap each other. Further, the memory cell 500 can be reduced by arranging the transistor 491 and the transistor 492 so as to overlap each other.

The insulator 432 is preferably an insulator containing excess oxygen.

For example, an insulator containing excess oxygen is an insulator having a function of releasing oxygen by heat treatment. For example, silicon oxide containing excess oxygen is silicon oxide that can release oxygen by heat treatment or the like. Therefore, the insulator 432 is an insulator capable of moving oxygen through the film. That is, the insulator 432 may be an insulator having oxygen permeability. For example, the insulator 432 may be an insulator having higher oxygen permeability than a semiconductor over the insulator.

An insulator containing excess oxygen may have a function of reducing oxygen vacancies in a semiconductor over the insulator. Oxygen deficiency in a semiconductor forms DOS and becomes a hole trap or the like. Further, when hydrogen enters an oxygen deficient site, electrons as carriers may be generated. Therefore, stable electrical characteristics can be imparted to the transistor by reducing oxygen vacancies in the semiconductor.

The insulator 442 is provided between the substrate 400 and the transistor 490. As the insulator 442, for example, an oxide containing aluminum, for example, aluminum oxide is used. The insulator 442 is an insulator that blocks oxygen and hydrogen. Aluminum oxide having a density of less than 3.2 g / cm ³ is particularly preferable because it has a high function of blocking hydrogen. Alternatively, aluminum oxide with low crystallinity is preferable because it has a particularly high function of blocking hydrogen.

For example, in the case where the substrate 400 is an element substrate including a Si transistor, dangling bonds of silicon can be reduced by supplying hydrogen from the outside, so that the electrical characteristics of the transistor may be improved. The hydrogen may be supplied, for example, by disposing an insulator containing hydrogen in the vicinity of the Si transistor and performing heat treatment so that the hydrogen is diffused and supplied to the Si transistor.

The insulator containing hydrogen is, for example, 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or more in a surface temperature range of 100 ° C. to 700 ° C. ^{3 (} or more) or 1 × 10 ²⁰ atoms / cm ³ or more of hydrogen (in terms of the number of hydrogen atoms) may be released.

By the way, the hydrogen diffused from the insulator containing hydrogen has a function of blocking the hydrogen by the insulator 442, so that the amount of hydrogen reaching the transistor 490 is small. Hydrogen can serve as a carrier trap or a carrier generation source in the oxide semiconductor and can degrade the electrical characteristics of the transistor 490. Therefore, blocking hydrogen with the insulator 442 is important for improving the performance and reliability of the semiconductor device.

On the other hand, for example, when oxygen is supplied to the transistor 490 from the outside, oxygen vacancies in the oxide semiconductor can be reduced, so that electrical characteristics of the transistor may be improved. For example, the supply of oxygen may be performed by heat treatment in an atmosphere containing oxygen. Alternatively, for example, an insulator containing excess oxygen (oxygen) may be provided in the vicinity of the transistor 490 and subjected to heat treatment so that the oxygen is diffused and supplied to the transistor 490. Here, an insulator containing excess oxygen is used for the insulator 432.

The diffused oxygen may reach the Si transistor through each layer. However, since the insulator 442 has a function of blocking oxygen, only a small amount of oxygen reaches the Si transistor. When oxygen is mixed into silicon, the crystallinity of silicon may be lowered, or carrier movement may be hindered. Therefore, blocking oxygen with the insulator 442 is important for improving the performance and reliability of the semiconductor device.

An insulator 452 is preferably provided over the transistor 490. The insulator 452 has a function of blocking oxygen and hydrogen. For the insulator 452, the description of the insulator 442 is referred to, for example. Alternatively, the insulator 452 has a higher function of blocking oxygen and hydrogen than the semiconductor 406a and / or the semiconductor 406c, for example.

When the semiconductor device includes the insulator 452, outward diffusion of oxygen from the transistor 490 can be suppressed. Accordingly, oxygen can be effectively supplied to the transistor 490 with respect to the amount of excess oxygen (oxygen) contained in the insulator 432 or the like. The insulator 452 blocks impurities including hydrogen mixed from the outside of the semiconductor device or a layer provided above the insulator 452, so that deterioration of the electrical characteristics of the transistor 490 due to the entry of impurities is suppressed. it can.

Note that for convenience, the insulator 442 and / or the insulator 452 are described separately from the transistor 490; however, they may be part of the transistor 490.

The insulators 434 and 436 are preferably insulators containing excess oxygen. For example, the description of the insulator 432 can be referred to.

The insulators 444 and 446 are preferably insulators that block oxygen and hydrogen. For example, the description of the insulator 442 can be referred to.

The insulators 454 and 456 are preferably insulators that block oxygen and hydrogen. For example, the description of the insulator 452 can be referred to.

Note that in this embodiment, the transistor 490, 491, or 492 can be formed using an oxide semiconductor in a channel formation region or the like as an example; however, one embodiment of the present invention is not limited thereto. For example, the transistor 490 includes Si (silicon), Ge (germanium), SiGe (silicon germanium), and GaAs (in the channel formation region, the vicinity thereof, the source region, the drain region, and the like depending on circumstances or circumstances. (Gallium arsenide) or the like.

For example, in this specification and the like, a transistor such as the transistor 490, 491, or 492 can be formed using various substrates. The kind of board | substrate is not limited to a specific thing. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, and a tungsten substrate. , A substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, and the base film include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Another example is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride. Alternatively, examples include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Alternatively, a flexible substrate may be used as the substrate, and the transistor may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. The separation layer can be used to separate a semiconductor device from another substrate and transfer it to another substrate after a semiconductor device is partially or entirely completed thereon. At that time, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that, for example, a structure of a laminated structure of an inorganic film of a tungsten film and a silicon oxide film or a structure in which an organic resin film such as polyimide is formed over a substrate can be used for the above-described release layer.

That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. Examples of a substrate to which a transistor is transferred include a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) in addition to the above-described substrate capable of forming a transistor. (Silk, cotton, hemp), synthetic fibers (including nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

Next, the operation of the memory cell 500 illustrated in FIG. 1 will be described with reference to FIGS.

Hereinafter, the case where the transistor 490, the transistor 491, and the transistor 492 are n-channel transistors is described. The transistor 490 may be a p-channel transistor. The transistor 491 may be a p-channel transistor. The transistor 492 may be a p-channel transistor.

4 and 5 are diagrams illustrating various voltages used in the operation of the memory cell 500. FIG. Here, it is assumed that k1 types of states (k1 is an integer of 2 or more) are stored in FN1, and k2 types of states (k2 is an integer of 2 or more) are stored in FN2. FIG. 4 is a diagram focusing on the floating node FN1, and FIGS. 4A, 4B, and 4C show the potentials of the floating node FN1, the write word line WW1, and the read word line RW1, respectively. Similarly, FIG. 5 is a diagram focusing on the floating node FN2, and FIGS. 5A, 5B, and 5C show the potentials of the floating node FN2, the write word line WW2, and the read word line RW2, respectively. .

Here, the function of the transistor 492 is confirmed again. In the transistor 492, the first gate electrode and the second gate electrode are arranged above and below and shifted from each other with the channel formation region interposed therebetween. The potential of the first gate electrode is the potential of the floating node FN1, and the potential of the second gate electrode is the potential of the floating node FN2. Thus, the transistor 492 is turned on or off according to the potential of the floating node FN1 and the potential of the floating node FN2. The transistor 492 has a threshold voltage Vth1 related to the first gate electrode and a threshold voltage Vth2 related to the second gate electrode. When the potential of the first gate electrode or the floating node FN1 becomes higher than Vth1, a channel is formed (or carriers are induced) in the channel formation region controlled by the first gate electrode. When the potential of the second gate electrode or the floating node FN2 becomes higher than Vth2, a channel is formed (or carriers are induced) in the channel formation region controlled by the second gate electrode. The transistor 492 becomes conductive only when the potential of the first gate electrode is higher than Vth1 and the potential of the second gate electrode is higher than Vth2.

The transistor 492 is equivalent to a circuit in which two transistors, a transistor having a threshold voltage of Vth1 (referred to as a transistor 492_1) and a transistor having a threshold voltage of Vth2 (referred to as a transistor 492_2) are connected in series. It can be said that it has a function. The transistor 492_1 is turned on when the potential of the first gate electrode is higher than Vth1, and is turned off when the potential of the first gate electrode is lower than Vth1. The transistor 492_2 is turned on when the potential of the second gate electrode is higher than Vth2, and is turned off when the potential of the second gate electrode is lower than Vth2. The transistor 492 is turned on only when the transistors 492_1 and 492_2 are turned on.

In FIG. 4, a state Write1 indicates a state in which the transistor 491 is in a conductive state and the potential of the bit line BL is applied to the floating node FN1. The potential V1 (i) (i is an integer greater than or equal to 1 and less than or equal to k1) is k1 types of potentials applied to FN1. Here, it is assumed that V1 (i) <V1 (i + 1) (where i is an integer not less than 1 and not more than (k1-1). In FIG. 4A, not less than V1 (1) and not more than V1 (k1). The potential region is indicated by a hatching pattern, VG1_H is given to WW1, and the transistor 491 is turned on regardless of the type of k1.VG1_H is larger than V1 (k1) by Vth (491) or more. That is, VG1_H> V1 (k1) + Vth (491), where Vth (491) is a threshold voltage of the transistor 491. Thus, the maximum potential V1 (k1) is changed to FN1. The transistor 491 can be kept in a conductive state also when applied to the transistor 491. The potential VC1_0 is a potential applied to the RW1 during writing.

In FIG. 4, the state Standby1 is a state in which the potential of the floating node FN1 is held. VC1_0 is given to RW1. VG1_0 is given to WW1, and the transistor 491 is turned off regardless of k1 types of states. VG1_0 is a potential at which the transistor 491 is turned off even when V1 (1) is written to FN1, or a potential at which the drain current of the transistor 491 becomes sufficiently low. Note that the potential of FN1 immediately after writing may slightly vary from the potential of FN1 during writing depending on the gate-drain capacitance (or gate-source capacitance) of the transistor 491.

In FIG. 4, the state Off1 is a state where the transistor 492_1 is non-conductive regardless of the k1 types of states. It may be used in non-selected memory cells at the time of writing or reading. VC1_L is supplied to RW1, and the transistor 492_1 is turned off regardless of the k1 types of states. VC1_L is a potential at which the transistor 492_1 is turned off even when the potential of FN1 is V1L (k1). That is, V1L (k1) <Vth1. Here, in the state where V1 (k1) is written, the potential of FN1 when VC1_L is given to RW1 is V1L (k1). V1L (k1) is expressed as V1L (k1) = V1 (k1) + Cs1 / CFN1 × (VC1_L−VC1_0). Here, CFN1 is the total capacitance value of FN1, and Cs1 is the capacitance value of the capacitor 494. Therefore, VC1_L is a potential satisfying VC1_L <VC1_0 + CFN1 / Cs1 × (Vth1−V1 (k1)). Note that the potential of FN1 in the state Standby1 may be used instead of V1 (k1).

In FIG. 4, a state Read1 (1) is a state in which the transistor 492_1 is turned on when V1 (k1) is written and the transistor 492_1 is turned off when V1 (k1-1) is written. In other words, the transistor 492_1 is non-conductive in a state where (k1-1) types of potentials are written, other than a state where V1 (k1) is written. Such a state is obtained by applying the potential VC1 (1) to RW1. Similarly to the calculation described above, VC1 (1) is a potential that satisfies VC1_0 + CFN1 / Cs1 × (Vth1−V1 (k1)) <VC1 (1) <VC1_0 + CFN1 / Cs1 × (Vth1−V1 (k1-1)). It is obtained.

In FIG. 4, a state Read1 (k1-1) is a state in which the transistor 492_1 is turned on when V1 (2) is written and the transistor 492_1 is turned off when V1 (1) is written. In other words, the transistor 492_1 is in a conductive state in a state where (k1-1) types of potentials are written, other than a state where V1 (1) is written. Such a state is obtained by applying the potential VC1 (k1-1) to RW1. Similarly to the calculation described above, VC1 (1) is a potential that satisfies VC1_0 + CFN1 / Cs1 × (Vth1−V1 (2)) <VC1 (k1-1) <VC1_0 + CFN1 / Cs1 × (Vth1−V1 (1)). It is obtained.

In FIG. 4, the state On1 is a state in which the transistor 492_1 is turned on regardless of the k1 types of states. It may be used in a selected memory cell at the time of writing or reading. VC1_H is supplied to RW1, and the transistor 492_1 is turned on regardless of k1 types of states. VC1_H is a potential at which the transistor 492_1 is turned on even when the potential of FN1 is V1H (1). That is, V1H (1)> Vth1. Here, in a state where V1 (1) is written, the potential of FN1 when VC1_H is given to RW1 is V1H (1). V1H (1) is expressed as V1H (1) = V1 (1) + Cs1 / CFN1 × (VC1_H−VC1_0). Therefore, VC1_H is a potential that satisfies VC1_H> VC1_0 + CFN1 / Cs1 × (Vth1−V1 (1)). Note that the potential of FN1 in the state Standby1 may be used instead of V1 (1).

In the above description, the potentials of the floating node FN2, the write word line WW2, and the read word line RW2 are not specified, but these potentials are not particularly limited. This is because the potential of the floating node FN2, the write word line WW2, and the read word line RW2 has little influence on the floating node FN1.

As described in FIG. 4, the states of Write2, Standby2, Off2, Read2 (1), Read2 (k2-1), and On2 are defined using FIG. Further, potential V2 (i) (i is an integer of 1 to k2), VG2_H, VC2_0, VG2_0, VC2_L, VC2 (1), VC2 (k2-1), and VC2_H are defined. Note that V2 (i) <V2 (i + 1) (i is an integer of 1 to (k2-1)). The threshold voltage of the transistor 492 is Vth (492), the total capacitance value of FN2 is CFN2, and the capacitance value of the capacitor 493 is Cs2.

FIG. 6 is a diagram illustrating a part of the memory cell array in order to explain the operation of the memory cell. In FIG. 6, the (n−1) th bit line BL [n−1] or the nth bit line BL [n] of the memory cell array is connected to the (m−1) th word line WL [ m-1] or four memory cells connected to the mth word line WL [m] are shown. Note that the source line SL may be common to all memory cells.

FIG. 7 is a timing chart for explaining an example of the write operation to the memory cell array shown in FIG. In this example, four types of potentials V1, V2, V3, and V4 (V1 <V2 <V3 <V4) are written in FN1 and FN2, respectively. The memory cell realizes 16-value multivalue.

The timing chart shown in FIG. 7 is a timing chart in the periods p11 to p18 in which data is written to the memory cell connected to the (m−1) th word line WL [m−1], and the mth word line. And timing charts in periods p21 to p28 in which data is written to the memory cells connected to WL [m]. A constant potential VS0 is applied to the source line SL.

In a period p11 shown in FIG. 7, VG1_H is supplied to the write word line WW1 [m−1] and VC1_0 is supplied to the read word line RW1 [m−1], thereby writing to the FN1 of the selected memory cell. (State Write1). By applying VG2_L to the write word line WW2 [m−1] and VC2_L to the read word line RW2 [m−1], the transistor 492_2 of the selected memory cell is turned off (state Off2). At this time, the transistor 492 of the selected memory cell is turned off. By applying VG1_L to the write word line WW1 [m] and VC1_L to the read word line RW1 [m], the transistor 492_1 of the non-selected memory cell is turned off (state Off1). By applying VG2_L to the write word line WW2 [m] and VC2_L to the read word line RW2 [m], the transistor 492_2 of the non-selected memory cell is turned off (state Off2). At this time, the transistor 492 of the non-selected memory cell is turned off. A potential VB0 is applied to the bit lines BL [n-1] and BL [n]. The potential VB0 may be a bit line potential during standby.

In the period p12 illustrated in FIG. 7, the potential V4 is applied to the bit line BL [n-1] and the potential V1 is applied to BL [n]. Note that other wirings hold the potential of the previous period. As a result, V4 is applied to FN1 of the selected memory cell connected to the bit line BL [n-1], and FN1 of the selected memory cell connected to the bit line BL [n] V1 is given.

In the period p13 shown in FIG. 7, VG1_L is supplied to the write word line WW1 [m−1]. Note that other wirings hold the potential of the previous period. As a result, the transistor 491 of the selected memory cell connected to the write word line WW1 [m−1] is turned off, and the charge accumulated in the floating node FN1 is held. That is, the writing state ends. When the writing is completed, the potential of the read word line RW1 [m−1] and the bit lines BL [n−1] and BL [n] is held, so that the writing can be surely performed. If these potentials fluctuate simultaneously with the potential fluctuation of the write word line WW1 [m−1], the written state may be affected.

In the period p14 shown in FIG. 7, VC1_L is supplied to the read word line RW1 [m−1]. A potential VB0 is applied to the bit lines BL [n-1] and BL [n]. Note that other wirings hold the potential of the previous period. As a result, in all the memory cells, the transistor 492_1 is in the state Off1, and 492_2 is in the state Off2, which are in a non-selected state.

In a period p15 illustrated in FIG. 7, VG1_L is supplied to the write word line WW1 [m−1] and VC1_L is supplied to the read word line RW1 [m−1], so that the transistor 492_1 of the selected memory cell is turned off. (State Off1). By applying VG2_H to the write word line WW2 [m−1] and VC2_0 to the read word line RW2 [m−1], the FN2 of the selected memory cell is written (state Write2). At this time, the transistor 492 of the selected memory cell is turned off. By applying VG1_L to the write word line WW1 [m] and VC1_L to the read word line RW1 [m], the transistor 492_1 of the non-selected memory cell is turned off (state Off1). By applying VG2_L to the write word line WW2 [m] and VC2_L to the read word line RW2 [m], the transistor 492_2 of the non-selected memory cell is turned off (state Off2). At this time, the transistor 492 of the non-selected memory cell is turned off. A potential VB0 is applied to the bit lines BL [n-1] and BL [n].

In a period p16 illustrated in FIG. 7, the potential V3 is applied to the bit line BL [n-1] and the potential V2 is applied to BL [n]. Note that other wirings hold the potential of the previous period. As a result, FN2 of the selected memory cell connected to the bit line BL [n-1] is given V3, and FN1 of the selected memory cell connected to the bit line BL [n] V2 is given.

In a period p17 shown in FIG. 7, VG2_L is supplied to the write word line WW2 [m−1]. Note that other wirings hold the potential of the previous period. As a result, the transistor 490 of the selected memory cell connected to the write word line WW2 [m−1] is turned off, and the charge accumulated in the floating node FN2 is held. That is, the writing state ends. When writing is completed, the potential of the read word line RW2 [m−1] and the bit lines BL [n−1] and BL [n] can be held, so that writing can be performed reliably. If these potentials fluctuate simultaneously with the potential fluctuation of the write word line WW2 [m−1], the written state may be affected.

In the period p18 illustrated in FIG. 7, VC2_L is supplied to the read word line RW2 [m−1]. A potential VB0 is applied to the bit lines BL [n-1] and BL [n]. Note that other wirings hold the potential of the previous period. As a result, in all the memory cells, the transistor 492_1 is in the state Off1, and 492_2 is in the state Off2, which are in a non-selected state.

In a period p21 shown in FIG. 7, VG1_H is supplied to the write word line WW1 [m] and VC1_0 is supplied to the read word line RW1 [m], thereby writing data to the FN1 of the selected memory cell (state) Write 1). By applying VG2_L to the write word line WW2 [m] and VC2_L to the read word line RW2 [m], the transistor 492_2 of the selected memory cell is turned off (state Off2). At this time, the transistor 492 of the selected memory cell is turned off. By applying VG1_L to the write word line WW1 [m−1] and VC1_L to the read word line RW1 [m−1], the transistor 492 of the non-selected memory cell is turned off (state Off1). By applying VG2_L to the write word line WW2 [m−1] and VC2_L to the read word line RW2 [m−1], the transistor 492 of the non-selected memory cell is turned off (state Off2). At this time, the transistor 492 of the non-selected memory cell is turned off. A potential VB0 is applied to the bit lines BL [n-1] and BL [n].

In the period p22 illustrated in FIG. 7, the potential V2 is applied to the bit line BL [n-1] and the potential V3 is applied to BL [n]. Note that other wirings hold the potential of the previous period. As a result, V2 is applied to FN1 of the selected memory cell connected to the bit line BL [n−1], and FN1 of the selected memory cell connected to the bit line BL [n] V3 is given.

In the period p23 shown in FIG. 7, VG1_L is supplied to the write word line WW1 [m]. Note that other wirings hold the potential of the previous period. As a result, the transistor 491 of the selected memory cell connected to the write word line WW1 [m] is turned off, and the charge accumulated in the floating node FN1 is held. That is, the writing state ends. When writing is completed, the potential of the read word line RW1 [m] and the bit lines BL [n−1] and BL [n] can be held, so that writing can be performed reliably. If these potentials fluctuate simultaneously with the potential fluctuation of the write word line WW1 [m], the written state may be affected.

In a period p24 illustrated in FIG. 7, VC1_L is supplied to the read word line RW1 [m]. A potential VB0 is applied to the bit lines BL [n-1] and BL [n]. Note that other wirings hold the potential of the previous period. As a result, in all the memory cells, the transistor 492_1 is in the state Off1, and 492_2 is in the state Off2, which are in a non-selected state.

In a period p25 illustrated in FIG. 7, VG1_L is supplied to the write word line WW1 [m] and VC1_L is supplied to the read word line RW1 [m], so that the transistor 492_1 of the selected memory cell is turned off (state) Off1). By applying VG2_H to the write word line WW2 [m] and VC2_0 to the read word line RW2 [m], the FN2 of the selected memory cell is written (state Write2). At this time, the transistor 492 of the selected memory cell is turned off. By applying VG1_L to the write word line WW1 [m−1] and VC1_L to the read word line RW1 [m−1], the transistor 492_1 of the non-selected memory cell is turned off (state Off1). By applying VG2_L to the write word line WW2 [m−1] and VC2_L to the read word line RW2 [m−1], the transistor 492_2 of the non-selected memory cell is turned off (state Off2). At this time, the transistor 492 of the non-selected memory cell is turned off. A potential VB0 is applied to the bit lines BL [n-1] and BL [n].

In the period p26 illustrated in FIG. 7, the potential V1 is applied to the bit line BL [n-1] and the potential V4 is applied to BL [n]. Note that other wirings hold the potential of the previous period. As a result, V1 is given to FN2 of the selected memory cell connected to the bit line BL [n-1], and FN1 of the selected memory cell connected to the bit line BL [n] V4 is given.

In a period p27 shown in FIG. 7, VG2_L is supplied to the write word line WW2 [m]. Note that other wirings hold the potential of the previous period. As a result, the transistor 490 of the selected memory cell connected to the write word line WW2 [m] is turned off, and the charge accumulated in the floating node FN2 is held. That is, the writing state ends. When writing is completed, the potential of the read word line RW2 [m] and the bit lines BL [n−1] and BL [n] can be held, so that writing can be performed reliably. If these potentials fluctuate simultaneously with the potential fluctuation of the write word line WW2 [m], the written state may be affected.

In the period p28 shown in FIG. 7, VC2_L is supplied to the read word line RW2 [m]. A potential VB0 is applied to the bit lines BL [n-1] and BL [n]. Note that other wirings hold the potential of the previous period. As a result, in all the memory cells, the transistor 492_1 is in the state Off1, and 492_2 is in the state Off2, which are in a non-selected state.

Through the data writing described in the periods p11 to p18 and p21 to p28, a predetermined state is written into the memory cell array illustrated in FIG. Note that in the write operation period, the transistor 492 of the selected memory cell is non-conductive, and the transistor 492 of the non-selected memory cell is non-conductive. Therefore, even when the potential applied to the source line SL is different from the potential applied to the bit line BL, current does not flow through the transistor 492 in the conductive state.

FIG. 8 is a timing chart for explaining an example of a read operation to the memory cell array shown in FIG. A case where four types of potentials are read from FN1 and FN2 is shown. The memory cell realizes 16-value multivalue.

The timing chart shown in FIG. 8 shows periods p31 to p39 for reading data held in FN1 of the memory cell connected to the (m−1) th word line WL [m−1] and held in FN2. And a timing chart in the data reading periods p41 to p49. A constant potential VS0 is applied to the source line SL. In addition, since reading from the memory cell connected to the mth word line WL [m] is not performed, VG1_L is given to WW1 [m] and VG2_L is given to WW2 [m] throughout the reading period. Further, VC1_L is given to RW1 [m], and VC2_L is given to RW2 [m]. In reading, the transistors 490 and 491 are always turned off, so that VG1_L is supplied to WW1 [m−1] and VG2_L is supplied to WW2 [m−1] throughout the reading period. Therefore, in the following, potentials applied to RW1 [m−1], RW2 [m−1], BL [n−1], and BL [n] will be mainly described.

In a period p31 illustrated in FIG. 8, VC1_L is supplied to the read word line RW1 [m−1], so that the transistor 492_1 of the selected memory cell is turned off (state Off1). By applying VC2_H to the read word line RW2 [m−1], the transistor 492_2 of the selected memory cell is turned on (state On2). At this time, the transistor 492 of the selected memory cell is non-conductive. A potential V _precharge is _applied to the bit lines BL [n−1] and BL [n]. The period p31 is a precharge period. The potential V _precharge is a precharge potential. At the end of the period p31, the bit lines BL [n−1] and BL [n] are in a floating state.

In the period p32 shown in FIG. 8, by applying VC1 (1) to the read word line RW1 [m−1], the transistor 492_1 becomes conductive in a state where V4 is written to FN1 of the selected memory cell. In this state, the transistor 492_1 is turned off (state Read1 (1)). Note that since VC2_H is supplied to the read word line RW2 [m−1], the transistor 492_2 of the selected memory cell remains in a conductive state. Accordingly, the conduction state of the transistor 492 of the selected memory cell is determined by the state held by FN1. Since the potential V4 is written to FN1 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned on. As a result, the bit line BL [n−1] in a floating state is electrically connected to the source line SL through the transistor 492 in a conductive state. Then, the charge accumulated in the bit line BL [n−1] is charged or discharged, and the potential of the bit line BL [n−1] changes from V _precharge to VS0. On the other hand, since the potential V1 is written to FN1 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned off. As a result, the potential of the bit line BL [n] in a floating state is held.

In a period p33 shown in FIG. 8, VC1_L is supplied to the read word line RW1 [m−1], so that the transistor 492_1 of the selected memory cell is turned off (state Off1). Accordingly, the transistor 492 of the selected memory cell is turned off. As a result, the potential of the immediately preceding period is held in the bit line BL [n−1] and the bit line BL [n]. In the period p32 or the period p33, reading can be performed by detecting the potentials of the bit line BL [n−1] and the bit line BL [n] with a reading circuit.

In periods p34 to p36 shown in FIG. 8, operations similar to those in the periods p31 to p33 are performed. However, VC1 (2) is applied to the read word line RW1 [m−1] instead of VC1 (1). When VC1 (2) is supplied to the read word line RW1 [m−1], the transistor 492_1 is turned on when V3 or V4 is written to the FN1 of the selected memory cell, and the transistor 492_1 is turned on in other states. Non-conducting. Since the potential V4 is written to FN1 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned on. Since the potential V1 is written in FN1 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned off. As a result, in the period p35, the potential of the bit line BL [n−1] changes from V _precharge to VS0. The potential of the bit line BL [n] is maintained.

In periods p37 to p39 shown in FIG. 8, operations similar to those in the periods p31 to p33 are performed. However, VC1 (3) is applied to the read word line RW1 [m−1] instead of VC1 (1). When VC1 (3) is applied to the read word line RW1 [m−1], the transistor 492_1 becomes conductive when V2, V3, or V4 is written to the FN1 of the selected memory cell, and the transistor 492_1 is otherwise turned on. 492_1 becomes non-conductive. Since the potential V4 is written to FN1 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned on. Since the potential V1 is written in FN1 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned off. As a result, in the period p38, the potential of the bit line BL [n−1] changes from V _precharge to VS0. The potential of the bit line BL [n] is maintained.

In a period p41 illustrated in FIG. 8, VC1_H is supplied to the read word line RW1 [m−1], so that the transistor 492_1 of the selected memory cell is turned on (state On1). By applying VC2_L to the read word line RW2 [m−1], the transistor 492_2 of the selected memory cell is turned off (state Off2). At this time, the transistor 492 of the selected memory cell is non-conductive. A potential V _precharge is _applied to the bit lines BL [n−1] and BL [n]. The period p31 is a precharge period. The potential V _precharge is a precharge potential. At the end of the period p41, the bit lines BL [n−1] and BL [n] are in a floating state.

In the period p42 shown in FIG. 8, by applying VC2 (1) to the read word line RW2 [m−1], the transistor 492_2 becomes conductive in a state where V4 is written to FN2 of the selected memory cell, and otherwise In this state, the transistor 492_2 is turned off (state Read2 (1)). Note that VC1_H is supplied to the read word line RW1 [m−1]; thus, the transistor 492_1 of the selected memory cell remains in a conductive state. Accordingly, the conduction state of the transistor 492 of the selected memory cell is determined by the state held by FN2. Since the potential V3 is written to FN2 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned off. As a result, the potential of the bit line BL [n−1] in the floating state is held. On the other hand, since the potential V2 is written to FN2 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned off. As a result, the potential of the bit line BL [n] in a floating state is held.

In a period p43 illustrated in FIG. 8, VC2_L is supplied to the read word line RW2 [m−1], so that the transistor 492_2 of the selected memory cell is turned off (state Off2). Accordingly, the transistor 492 of the selected memory cell is turned off. As a result, the potential of the immediately preceding period is held in the bit line BL [n−1] and the bit line BL [n]. In the period p42 or the period p43, reading can be performed by detecting the potentials of the bit line BL [n−1] and the bit line BL [n] with a reading circuit.

In the periods p44 to p46 illustrated in FIG. 8, operations similar to those in the periods p41 to p43 are performed. However, VC2 (2) is applied to the read word line RW2 [m−1] instead of VC2 (1). When VC2 (2) is applied to the read word line RW2 [m−1], the transistor 492_2 is turned on when V3 or V4 is written to the FN2 of the selected memory cell, and the transistor 492_2 is turned on in other states. Non-conducting. Since the potential V3 is written to FN2 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned on. Since the potential V2 is written to FN2 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned off. As a result, in the period p45, the potential of the bit line BL [n−1] changes from V _precharge to VS0. The potential of the bit line BL [n] is maintained.

In the periods p47 to p49 shown in FIG. 8, operations similar to those in the periods p41 to p43 are performed. However, VC2 (3) is applied to the read word line RW2 [m−1] instead of VC2 (1). When VC2 (3) is applied to the read word line RW2 [m−1], the transistor 492_2 becomes conductive when V2, V3, or V4 is written to the FN2 of the selected memory cell, and in other states, the transistor 492_2 492_2 becomes non-conductive. Since the potential V3 is written to FN2 of the selected memory cell connected to the bit line BL [n-1], the transistor 492 is turned on. Since the potential V2 is written to FN2 of the selected memory cell connected to the bit line BL [n], the transistor 492 is turned on. As a result, in the period p48, the potential of the bit line BL [n−1] changes from V _precharge to VS0. The potential of the bit line BL [n] changes from V _precharge to VS0.

As described above, the data stored in the memory cell array illustrated in FIG. 6 is read by reading the data described in the periods p31 to p39 and p41 to p49. In the read circuit, when the bit line potential is higher than Vref and “1”, and when the bit line potential is lower than “0”, the read circuit connected to the bit line BL [n−1] as a result of the timing chart shown in FIG. Reads “0”, “0”, “0”, “1”, “0”, “0”. The first three values indicate that V4 is written in FN1 of the selected memory cell, and the latter three values indicate that V3 is written in FN2 of the selected memory cell. The read circuit connected to the bit line BL [n] reads “1”, “1”, “1”, “1”, “1”, “0”. The first three values indicate that V1 is written in FN1 of the selected memory cell, and the latter three values indicate that V2 is written in FN2 of the selected memory cell.

As described above, in the memory cell array shown in FIG. 6, four kinds of potentials V1, V2, V3, and V4 (V1 <V2 <V3 <V4) can be written to and read from FN1 and FN2, respectively. . Since the states of writing to FN1 and FN2 are independent, the memory cell realizes 16-value multivalue. Note that although four types of potentials are written in FN1 and FN2, respectively, the present invention is not limited to this, and various multivalues can be realized.

With the semiconductor device (memory cell) described above, a memory cell with a reduced area can be realized. As a result, a semiconductor device with improved storage density and a semiconductor device with improved storage capacity can be provided.

(Embodiment 2)
An example of a structure of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

FIG. 9 illustrates an example of a structure of a semiconductor device. A semiconductor device 600 illustrated in FIG. 9 is an example of a semiconductor device that can function as a memory device. The semiconductor device 600 includes a memory cell array 610, a row decoder 621, a word line driver circuit 622, a bit line driver circuit 630, an output circuit 640, a control logic circuit 660, and a power supply circuit 670.

The memory cell array 610 includes the memory cells described above. The bit line driver circuit 630 includes a column decoder 631, a precharge circuit 632, a read circuit 633, and a write circuit 634. The precharge circuit 632 has a function of precharging the bit line. The reading circuit 633 has a function of detecting the potential of the bit line and reading data from the memory cell. The read signal is output to the outside of the semiconductor device 600 through the output circuit 640 as a digital data signal RDATA.

The semiconductor device 600 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD), or the like as a power supply voltage from outside.

Further, control signals (CE, WE, RE), an address signal ADDR, a data signal WDATA, and the like are input to the semiconductor device 600 from the outside. ADDR is input to the row decoder 621 and the column decoder 631, and WDATA is input to the write circuit 634.

The control logic circuit 660 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder 621, the column decoder 631, the power supply circuit 670, and the like. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 660 is not limited to this, and other control signals may be input as necessary.

The read circuit 633 may include a sense amplifier and compare the potential Vref with the bit line potential. Further, a logic circuit that performs data conversion may be provided, and the read data may be converted into an output format. The writing circuit 634 may include a logic circuit that performs data conversion, and may convert the input data WDATA into a format for writing.

The power supply circuit 670 receives VDD, VSS, or another high power supply voltage, generates a potential necessary for a read operation and a write operation, and outputs the potential.
For example, when writing to and reading from the 16-value memory cells described above, V1, V2, V3, V4, VG1_H, VG1_L, VG2_H, VG2_L, VC1_H, VC1_L, VC2_H, VC2_L, VC1 (1), VC1 (2) ), VC1 (3), VC2 (1), VC2 (2), VC2 (3), and the like.

Note that the above-described circuits or signals can be appropriately discarded as necessary.

The semiconductor device 600 provides the above-described memory cell to provide a semiconductor device having a memory cell with a reduced area, a semiconductor device with improved storage density, a semiconductor device with improved storage capacity, or a small semiconductor device. Can do.

Note that circuits other than the memory cell array 610 may include an n-channel Si transistor and a p-channel Si transistor. The region where the transistor including an oxide semiconductor is not used can be stacked under the memory cell array 610. As a result, a smaller memory device can be manufactured.

A circuit other than the memory cell array 610 may include a transistor including an oxide semiconductor and a p-channel Si transistor. Since the above-described transistor using an oxide semiconductor has a low off-state current and a high on-state current, a low leakage current and a high-speed operation can be compatible even when a CMOS circuit is configured in combination with a p-channel Si transistor. In particular, since all n-channel transistors are formed using oxide semiconductors, it is not necessary to fabricate n-channel Si transistors, the process is simplified, and the yield can be improved and the process cost can be reduced. Become.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
The transistors 490, 491, and 492 can have various structures. In this embodiment, in order to facilitate understanding, only the transistor 490 and a region in the vicinity thereof are extracted and illustrated in FIGS.

FIG. 10A is an example of a top view of the transistor 490. FIG. FIG. 10B illustrates an example of a cross-sectional view taken along one-dot chain line E1-E2 and one-dot chain line E3-E4 in FIG. Note that in FIG. 10A, part of the insulator and the like is omitted for easy understanding.

Although FIGS. 3A and 3B and the like illustrate the example in which the conductors 416a and 416b functioning as the source electrode and the drain electrode are in contact with the top and side surfaces of the semiconductor 406b, the top surface of the insulator 432, and the like, The structure is not limited to this. For example, as illustrated in FIG. 10, the conductor 416a and the conductor 416b may be in contact with only the top surface of the semiconductor 406b.

In the transistor illustrated in FIGS. 10A and 10B, the conductor 416a and the conductor 416b are not in contact with the side surface of the semiconductor 406b. Therefore, an electric field applied from the conductor 404 functioning as a gate electrode toward the side surface of the semiconductor 406b is difficult to be shielded by the conductor 416a and the conductor 416b. Further, the conductor 416 a and the conductor 416 b are not in contact with the upper surface of the insulator 432. Therefore, excess oxygen (oxygen) released from the insulator 432 is not consumed because the 416a and the conductor 416b are oxidized. Therefore, excess oxygen (oxygen) released from the insulator 432 can be efficiently used to reduce oxygen vacancies in the semiconductor 406b. In other words, the transistor having the structure illustrated in FIGS. 10A and 10B is a transistor with excellent electric characteristics such as a high on-state current, a high field effect mobility, a low subthreshold swing value, and a high reliability.

FIG. 11A is an example of a top view of the transistor 490. FIG. FIG. 11B illustrates an example of a cross-sectional view taken along the dashed-dotted line G1-G2 and the dashed-dotted line G3-G4 in FIG. Note that in FIG. 11A, part of an insulator or the like is omitted for easy understanding.

A transistor 490 illustrated in FIGS. 11A and 11B includes a conductor 421 over the insulator 442, an insulator 432 having a protrusion over the insulator 442 and the conductor 421, and the insulator 432. A semiconductor 406a on the protrusion, a semiconductor 406b on the semiconductor 406a, a semiconductor 406c on the semiconductor 406b, and a conductor 416a and a conductor 416b which are in contact with the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c and are spaced apart from each other. , On the semiconductor 406c, on the conductor 416a and on the conductor 416b, on the conductor 426 on the insulator 411, on the conductor 416a, on the conductor 416b, on the insulator 411, and on the conductor 426 An insulator 452 and an insulator 462 over the insulator 452 are provided.

Note that the insulator 411 is in contact with at least the side surface of the semiconductor 406b in the G3-G4 cross section. In addition, the conductor 426 faces the upper surface and the side surface of the semiconductor 406b through at least the insulator 411 in the G3-G4 cross section. The conductor 421 faces the lower surface of the semiconductor 406b with the insulator 432 interposed therebetween. Further, the insulator 432 may not have a convex portion. Further, the semiconductor 406c may not be provided. Further, the insulator 452 is not necessarily provided. Further, the insulator 462 is not necessarily provided.

A transistor 490 illustrated in FIG. 11 is different from the transistor 490 illustrated in FIG. Specifically, the structures of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c of the transistor 490 illustrated in FIG. 3 are different from the structures of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c of the transistor 490 illustrated in FIG. Further, the presence or absence of the conductor 421 is different. Therefore, the description of the transistor illustrated in FIG. 4 can be referred to for the transistor illustrated in FIG. 11 as appropriate.

(Embodiment 4)
The structures of oxide semiconductors that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, the semiconductor 407a, the semiconductor 407b, the semiconductor 407c, the semiconductor 408a, the semiconductor 408b, the semiconductor 408c, and the like are described below. Note that in this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor is classified roughly into a non-single-crystal oxide semiconductor and a single-crystal oxide semiconductor. The non-single-crystal oxide semiconductor refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, or the like.

First, the CAAC-OS will be described.

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts.

When the CAAC-OS is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

When CAAC-OS is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface where a CAAC-OS is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS.

On the other hand, when CAAC-OS is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, the arrangement of metal atoms is not necessarily arranged regularly between different crystal parts.

FIG. 12A is a cross-sectional TEM image of the CAAC-OS. FIG. 12B is a cross-sectional TEM image obtained by further enlarging FIG. 12A, and the atomic arrangement is highlighted for easy understanding.

FIG. 12C is a local Fourier transform image of a circled region (diameter approximately 4 nm) between A-O-A ′ in FIG. From FIG. 12C, the c-axis orientation can be confirmed in each region. Further, since the direction of the c-axis is different between A-O and O-A ′, it is suggested that the grains are different. Further, it can be seen that the angle of the c-axis continuously changes little by little, such as 14.3 °, 16.6 °, and 26.4 ° between A and O. Similarly, it can be seen that the angle of the c-axis continuously changes little by little between −18.3 °, −17.6 °, and −15.9 ° between O and A ′.

Note that when electron diffraction is performed on the CAAC-OS, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm to 30 nm is performed on the top surface of the CAAC-OS, spots are observed (see FIG. 13A).

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS has orientation.

Note that most crystal parts included in the CAAC-OS are large enough to fit in a cube whose one side is less than 100 nm. Therefore, a case where a crystal part included in the CAAC-OS fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. Note that a large crystal region may be formed when a plurality of crystal parts included in the CAAC-OS are connected to each other. For example, in a planar TEM image, a crystal region that is 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on the CAAC-OS using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS having an InGaZnO ₄ crystal by an out-of-plane method, the diffraction angle A peak may appear in the vicinity of (2θ) of 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented substantially perpendicular to the formation surface or the top surface. It can be confirmed.

On the other hand, when the CAAC-OS is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of an InGaZnO ₄ single crystal oxide semiconductor, analysis (φ scan) is performed when 2θ is fixed in the vicinity of 56 ° and the sample is rotated with the normal vector of the sample surface as the axis (φ axis). Six peaks attributed to the crystal plane equivalent to the () plane are observed. On the other hand, in the case of a CAAC-OS, a clear peak does not appear even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS, the orientations of the a-axis and the b-axis are irregular between different crystal parts, but have c-axis orientation, and the c-axis is a normal vector of a formation surface or an upper surface. It can be seen that it faces in a direction parallel to. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when a crystallization treatment such as a heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS. Therefore, for example, when the shape of the CAAC-OS is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS.

In the CAAC-OS, the distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS, the area near the upper surface has a higher ratio of c-axis aligned crystal parts than the area near the formation surface. May be. In addition, in the CAAC-OS to which an impurity is added, a region to which the impurity is added may be changed, and a region having a different ratio of partially c-axis aligned crystal parts may be formed.

Note that in the analysis of the CAAC-OS including an InGaZnO ₄ crystal by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. The CAAC-OS preferably has a peak at 2θ of around 31 ° and a peak at 2θ of around 36 °.

The CAAC-OS is an oxide semiconductor with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have large atomic radii (or molecular radii). If they are contained inside an oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed and the crystallinity is lowered. It becomes a factor to make. Note that the impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.

A CAAC-OS is an oxide semiconductor with a low density of defect states. For example, oxygen vacancies in an oxide semiconductor can serve as a carrier trap or a carrier generation source by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier traps. Therefore, a transistor including the oxide semiconductor is a highly reliable transistor with little variation in electrical characteristics. Note that the charge trapped in the carrier trap of the oxide semiconductor takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor using a CAAC-OS has little change in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor will be described.

In a microcrystalline oxide semiconductor, a crystal part may not be clearly observed in an observation image using a TEM. In most cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). In addition, for example, the nc-OS may not clearly confirm the crystal grain boundary in an observation image obtained by a TEM.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In the nc-OS, regularity is not observed in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole layer. Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on an analysis method. For example, when structural analysis is performed on the nc-OS using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. When nc-OS is subjected to electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a larger probe diameter (eg, 50 nm or more) than the crystal part, a diffraction pattern such as a halo pattern is observed. The On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to or smaller than that of the crystal part, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS, a plurality of spots may be observed in the ring-shaped region (see FIG. 13B).

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

Therefore, the nc-OS may have a higher carrier density than the CAAC-OS. An oxide semiconductor with a high carrier density may have a high electron mobility. Therefore, a transistor using the nc-OS may have high field effect mobility. Further, the nc-OS has a higher density of defect states than the CAAC-OS, and thus may have a large number of carrier traps. Therefore, a transistor using the nc-OS has a large variation in electric characteristics and has low reliability as compared with a transistor using the CAAC-OS. Note that the nc-OS can be formed even if it contains a relatively large amount of impurities; therefore, the nc-OS can be formed more easily than the CAAC-OS and can be preferably used depending on the application. Therefore, a semiconductor device including a transistor using an nc-OS can be manufactured with high productivity.

Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, and a CAAC-OS, for example.

As described above, the CAAC-OS has an advantage that carrier mobility is less likely to be lowered because carrier scattering due to crystal grain boundaries is smaller than that of polycrystal and microcrystal. In addition, a CAAC-OS is an oxide semiconductor with a low density of defect states and has few carrier traps; thus, a transistor using the CAAC-OS is an excellent transistor with high electrical characteristics and small reliability.

In the case where an oxide semiconductor has a plurality of structures, structural analysis may be possible by using nanobeam electron diffraction.

13C shows an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, and an optical system 16 1 shows a transmission electron diffraction measurement apparatus having an observation room 20 below, a camera 18 installed in the observation room 20, and a film chamber 22 below the observation room 20. The camera 18 is installed toward the inside of the observation room 20. Note that the film chamber 22 may not be provided.

FIG. 13D shows an internal structure of the transmission electron diffraction measurement apparatus shown in FIG. Inside the transmission electron diffraction measurement apparatus, electrons emitted from the electron gun installed in the electron gun chamber 10 are irradiated to the substance 28 arranged in the sample chamber 14 through the optical system 12. The electrons that have passed through the substance 28 are incident on the fluorescent plate 32 installed inside the observation room 20 via the optical system 16. On the fluorescent plate 32, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of incident electrons.

The camera 18 is installed facing the fluorescent screen 32, and can capture a pattern that appears on the fluorescent screen 32. The angle formed between the center of the lens of the camera 18 and the straight line passing through the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 is, for example, 15 ° to 80 °, 30 ° to 75 °, or 45 ° to 70 °. The following. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. The camera 18 may be installed in the film chamber 22 in some cases. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with less distortion can be taken from the back surface of the fluorescent plate 32.

The sample chamber 14 is provided with a holder for fixing the substance 28 as a sample. The holder has a structure that transmits electrons passing through the substance 28. The holder may have a function of moving the substance 28 to the X axis, the Y axis, the Z axis, and the like, for example. The movement function of the holder may have an accuracy of moving in the range of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, and the like. These ranges may be set to optimum ranges depending on the structure of the substance 28.

Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

For example, as shown in FIG. 13D, it is possible to confirm how the structure of the substance changes by changing (scanning) the irradiation position of the electron 24 that is a nanobeam in the substance. At this time, if the substance 28 is a CAAC-OS, a diffraction pattern as shown in FIG. 13A is observed. Alternatively, when the substance 28 is an nc-OS, a ring-shaped diffraction pattern with a bright spot as shown in FIG. 13B is observed.

A diffraction pattern typically shown in the CAAC-OS shown in FIG. 13A, that is, a diffraction pattern showing c-axis orientation is referred to as a CAAC structure diffraction pattern. As shown in FIG. 13A, in the CAAC-OS diffraction pattern, for example, a spot located at the vertex of a hexagon is confirmed. In the CAAC-OS, by scanning the irradiation position, the direction of the hexagon is not uniform, and it can be seen that the hexagon is rotating little by little. The angle of rotation has a certain width.

Alternatively, in the CAAC-OS diffraction pattern, a state where the irradiation position is scanned and the c-axis is rotated little by little is seen. This can be said that the surface formed by the a-axis and the b-axis is rotating, for example.

By the way, even if the substance 28 is CAAC-OS, a diffraction pattern similar to that of the nc-OS or the like may be partially observed. Therefore, the quality of the CAAC-OS can be represented by a ratio of a region where a CAAC-OS diffraction pattern is observed in a certain range (also referred to as a CAAC ratio or a CAAC conversion ratio) in some cases. For example, in the case of a high-quality CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and further preferably 95% or more and 100% or less. Note that a ratio of a region where a diffraction pattern different from that of the CAAC-OS in a certain range is observed is referred to as a non-CAAC ratio or a non-CAAC conversion rate.

Hereinafter, a method for evaluating the CAAC ratio of the CAAC-OS will be described. A measurement point is selected at random, a transmission electron diffraction pattern is obtained, and the ratio of the number of measurement points at which a CAAC structure diffraction pattern is observed is calculated with respect to the number of all measurement points. Here, the number of measurement points is preferably 50 points or more, and more preferably 100 points or more.

As a method of randomly selecting measurement points, for example, the irradiation position may be scanned in a straight line, and a diffraction pattern may be acquired at regular intervals. Scanning the irradiation position is preferable because the boundary between the area having the CAAC structure and the other area can be confirmed.

As an example, a sample having a CAAC-OS immediately after film formation (denoted as as-sputtered) and a sample having a CAAC-OS after 450 ° C. heat treatment in an atmosphere containing oxygen were manufactured. A transmission electron diffraction pattern was obtained while scanning. Here, the diffraction pattern was observed while scanning at a rate of 5 nm / second for 60 seconds, and the observed diffraction pattern was converted into a still image every 0.5 seconds, thereby deriving the CAAC ratio. As the electron beam, a nano beam having a probe diameter of 1 nm was used. The same measurement was performed on 6 samples. And the average value in 6 samples was used for calculation of CAAC ratio.

The CAAC ratio in each sample is shown in FIG. The CAAC ratio of the CAAC-OS immediately after the film formation was 75.7% (the non-CAAC ratio was 24.3%). The CAAC ratio of the CAAC-OS after the 450 ° C. heat treatment was 85.3% (the non-CAAC ratio was 14.7%). It can be seen that the CAAC ratio after the 450 ° C. heat treatment is higher than that immediately after the film formation. That is, it can be seen that the non-CAAC ratio is decreased (the CAAC ratio is increased) by heat treatment at a high temperature (for example, 400 ° C. or higher). Further, it can be seen that a CAAC-OS having a high CAAC ratio can be obtained by heat treatment at less than 500 ° C.

Here, most of the diffraction patterns different from those of the CAAC-OS were the same as those of the nc-OS. Further, an amorphous oxide semiconductor could not be confirmed in the measurement region. Accordingly, it is suggested that the region having a structure similar to that of the nc-OS is rearranged and affected by the structure of the adjacent region by the heat treatment.

14B and 14C are planar TEM images of the CAAC-OS immediately after film formation and after heat treatment at 450 ° C. By comparing FIG. 14B and FIG. 14C, it is found that the CAAC-OS after the heat treatment at 450 ° C. has a more uniform film quality. That is, it can be seen that heat treatment at a high temperature improves the quality of the CAAC-OS film.

When such a measurement method is used, the structure analysis of an oxide semiconductor having a plurality of structures may be possible.

Here, when nanobeam electron diffraction is performed, a region where the CAAC-OS partially has a structure other than the CAAC structure, for example, a region where a diffraction pattern of an nc structure is observed, or a diffraction pattern of a spinel crystal structure is observed. Consider the case of having a region to be processed. In such a case, at the boundary between the region where the diffraction pattern of the CAAC structure is observed and the region where the diffraction pattern of a structure other than the CAAC structure is observed, for example, carrier scattering increases and the carrier mobility decreases. There are things to do. Further, since the boundary portion is likely to be an impurity migration path and is likely to trap the impurity, there is a concern that the impurity concentration of the CAAC-OS increases.

In particular, when the region having a structure other than the CAAC structure is a region having a spinel crystal structure, a clear boundary may be observed between the region having the CAAC structure and the boundary portion. Then, the electron mobility may decrease due to carrier scattering. In the case where a conductive film is formed over the CAAC-OS, an element included in the conductive film, for example, a metal element or the like may diffuse to the boundary between the spinel and another region. Further, in a film having a spinel crystal structure, the impurity concentration in the film, for example, the hydrogen concentration may increase, and for example, there is a possibility that impurities such as hydrogen are trapped in the grain boundary portion. Therefore, it is more preferable that the CAAC-OS does not contain or contain a spinel crystal structure.

Consider a case where the oxide semiconductor includes an indium oxide semiconductor, element M, and zinc. Here, the element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of a plurality of the aforementioned elements. A preferable range of the ratio of the number of atoms of indium, the element M, and zinc of the oxide semiconductor, and x: y: z will be described.

It is known that an oxide containing indium, element M and zinc has a homologous phase (homologus series) represented by InMO ₃ (ZnO) _m (m is a natural number). Here, a case where the element M is Ga is considered as an example.

For example, a compound represented by ZnM ₂ O ₄ such as ZnGa ₂ O ₄ is known as a compound having a spinel crystal structure. When the composition in the vicinity of ZnGa ₂ O ₄ , that is, when x, y and z have values close to (x, y, z) = (0, 1, 2), a spinel crystal structure is formed. Or it is easy to mix.

In order to increase carrier mobility, it is preferable to increase the In content. In an oxide semiconductor containing indium, element M, and zinc, the s orbitals of heavy metals mainly contribute to carrier conduction. By increasing the indium content, more s orbitals overlap, so the indium content is low. A large amount of oxide has higher mobility than an oxide with a small content of indium. Therefore, carrier mobility can be increased by using an oxide containing a large amount of indium for the oxide semiconductor.

For example, the carrier mobility can be increased by increasing the atomic ratio of indium, which is preferable. For example, when the ratio of the number of atoms of indium, element M, and zinc included in the oxide semiconductor is represented by x: y: z, x is preferably 1.75 times or more of y.

In order to further increase the CAAC ratio of the oxide semiconductor, it is preferable to increase the atomic ratio of zinc. For example, in some cases, the CAAC ratio can be further increased by setting the atomic ratio of the In—Ga—Zn oxide to a range in which a solid solution region can be obtained. When the ratio of the number of zinc atoms to the sum of the number of atoms of indium and gallium is increased, the range in which a solid solution region can be taken tends to be widened. Therefore, in some cases, the CAAC ratio of the oxide semiconductor can be further increased by increasing the atomic ratio of zinc to the sum of the numbers of atoms of indium and gallium. For example, when the ratio of the number of atoms of indium, element M, and zinc included in the oxide semiconductor is represented by x: y: z, z is preferably 0.5 times or more of x + y. On the other hand, in order to increase the atomic ratio of indium and increase carrier mobility, z is preferably not more than twice x + y.

As a result, the rate at which a spinel crystal structure is observed in nanobeam electron diffraction can be eliminated or made extremely low. Thus, an excellent CAAC-OS can be obtained. In addition, since carrier scattering and the like at the boundary between the CAAC structure and the spinel crystal structure can be reduced, a transistor with high field-effect mobility can be realized when an oxide semiconductor is used for the transistor. In addition, a highly reliable transistor can be realized.

As a result, an oxide semiconductor with a high CAAC ratio can be realized. That is, a high-quality CAAC-OS can be realized. In addition, a CAAC-OS having no or very little region in which a spinel crystal structure is observed can be realized. For example, in the case of a high-quality CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and further preferably 95% or more and 100% or less.

In the case where an oxide semiconductor is formed by a sputtering method, a film with an atomic ratio that deviates from the atomic ratio of the target may be formed. In particular, zinc may have a film atomic ratio smaller than the target atomic ratio. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

Therefore, the atomic ratio of the target is preferably higher than that of an oxide semiconductor obtained by a sputtering method.

Note that the oxide semiconductor may be formed by stacking a plurality of films. Further, the CAAC ratio of each of the plurality of films may be different. In addition, among the plurality of stacked films, at least one film preferably has, for example, a CAAC ratio that is 90% higher, more preferably 95% or more, and still more preferably 97% or more and 100% or less.

The above is the structure of the oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, the semiconductor 407a, the semiconductor 407b, the semiconductor 407c, the semiconductor 408a, the semiconductor 408b, the semiconductor 408c, and the like.

Next, other elements of the semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, the semiconductor 407a, the semiconductor 407b, the semiconductor 407c, the semiconductor 408a, the semiconductor 408b, the semiconductor 408c, and the like are described.
In the following, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are described as representative examples; however, a semiconductor that is applied to the semiconductor 406a can be similarly applied to the semiconductors 407a and 408a. The semiconductor applied to the semiconductor 406b can be similarly applied to the semiconductors 407b and 408b. The semiconductor applied to the semiconductor 406c can be similarly applied to the semiconductors 407c and 408c. Further, the characteristics of the transistor 490 can be similarly obtained in the transistors 491 and 492.

An oxide semiconductor that can be used for the semiconductor 406b is an oxide semiconductor containing indium, for example. For example, when the semiconductor 406b contains indium, the carrier mobility (electron mobility) increases. The semiconductor 406b preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 406b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

For the semiconductor 406b, an oxide with a wide energy gap is used, for example. The energy gap of the semiconductor 406b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

In oxide semiconductors, the energy gap is large, electrons are hard to be excited, and the effective mass of holes is large. Avalanche collapse may not occur easily. Therefore, for example, hot carrier deterioration due to avalanche collapse may be suppressed. Therefore, the drain withstand voltage can be increased and the transistor can be driven with a higher drain voltage. Thus, a higher voltage, that is, more states can be held in the floating node, and the storage density can be increased in some cases.

The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c preferably contain at least indium. Note that when the semiconductor 406a is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is more than 50 atomic%, more preferably In is less than 25 atomic%, M is 75 atomic% or more. Further, when the semiconductor 406b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, M is less than 66 atomic%. In addition, when the semiconductor 406c is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is more than 50 atomic%, more preferably In is less than 25 atomic%, M is 75 atomic% or more. Note that the semiconductor 406c may be formed using the same kind of oxide as the semiconductor 406a.

As the semiconductor 406b, an oxide having an electron affinity higher than those of the semiconductor 406a and the semiconductor 406c is used. For example, as the semiconductor 406b, an oxide having an electron affinity higher than that of the semiconductor 406a and the semiconductor 406c by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV. Is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 406c preferably contains indium gallium oxide. The gallium atom ratio [In / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

At this time, when an electric field is applied to the gate electrode, a channel is formed in the semiconductor 406b having high electron affinity among the semiconductors 406a, 406b, and 406c. Thus, the field-effect mobility of the transistor can be increased. Here, since the constituent elements of the semiconductor 406b and the semiconductor 406c are the same, interface scattering hardly occurs.

Here, a mixed region of the semiconductor 406a and the semiconductor 406b may be provided between the semiconductor 406a and the semiconductor 406b. Further, in some cases, there is a mixed region of the semiconductor 406b and the semiconductor 406c between the semiconductor 406b and the semiconductor 406c. In the mixed region, the interface state density is low. Therefore, the stacked body of the semiconductors 406a, 406b, and 406c has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface. Note that FIG. 15A is a cross-sectional view in which a semiconductor 406a, a semiconductor 406b, and a semiconductor 406c are stacked in this order. FIG. 15B illustrates energy (Ec) at the lower end of the conduction band corresponding to the dashed-dotted line P1-P2 in FIG. 15A, and illustrates the case where the electron affinity of the semiconductor 406c is greater than that of the semiconductor 406a. FIG. 15C illustrates the case where the electron affinity of the semiconductor 406c is smaller than that of the semiconductor 406a.

At this time, electrons move mainly in the semiconductor 406b, not in the semiconductor 406a and the semiconductor 406c. As described above, when the interface state density at the interface between the semiconductor 406a and the semiconductor 406b and the interface state density at the interface between the semiconductor 406b and the semiconductor 406c are lowered, movement of electrons in the semiconductor 406b is inhibited. Therefore, the on-state current of the transistor 490 can be increased.

For example, the semiconductor 406a and the semiconductor 406c are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 406b or two or more elements. Since the semiconductor 406a and the semiconductor 406c are composed of one or more elements other than oxygen constituting the semiconductor 406b, or two or more elements, an interface state at the interface between the semiconductor 406a and the semiconductor 406b and the interface between the semiconductor 406b and the semiconductor 406c. The position is difficult to form.

It is preferable that the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c have no or few spinel crystal structures. The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are preferably CAAC-OS.

For example, when a CAAC-OS including a plurality of c-axis aligned crystal parts is used as the semiconductor 406a, the semiconductor 406b stacked thereover has a favorable c-axis alignment even in the vicinity of the interface with the semiconductor 406a. Can be formed.

Further, by increasing the CAAC ratio of the CAAC-OS, for example, defects can be reduced. Further, for example, a region having a spinel structure can be reduced. Further, for example, carrier scattering can be reduced. Further, for example, a film having a high blocking ability against impurities can be obtained. Therefore, by increasing the CAAC ratio of the semiconductors 406a and 406c, a favorable interface can be formed with the semiconductor 406b in which a channel is formed, and carrier scattering can be reduced. For example, the CAAC ratio of the semiconductor 406a and / or the semiconductor 406c may be 10% or more, preferably 20% or more, more preferably 50%, more preferably 70% or more. Further, entry of impurities into the semiconductor 406b can be suppressed, and the impurity concentration of the semiconductor 406b can be reduced.

The semiconductor 406b is preferably a semiconductor with reduced oxygen vacancies.

For example, in the case where the semiconductor 406b has oxygen vacancies (also referred to as V 2 _O ), donor levels may be formed when hydrogen enters oxygen vacancy sites. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _O H scatters electrons, it becomes a factor for reducing the on-state current of the transistor 490. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor 490 can be increased by reducing oxygen vacancies in the semiconductor 406b in some cases.

In order to reduce oxygen vacancies in the semiconductor 406b, for example, there is a method in which excess oxygen contained in the insulator 432 is moved to the semiconductor 406b through the semiconductor 406a. In this case, the semiconductor 406a is preferably a layer having oxygen permeability (a layer through which oxygen passes or permeates).

Oxygen is released from the insulator 432 by heat treatment or the like and is taken into the semiconductor 406a. Note that oxygen may exist by being separated between atoms in the semiconductor 406a or may be present by being combined with oxygen or the like. The semiconductor 406a has higher oxygen permeability as the density is lower, that is, as the number of gaps between atoms is larger. For example, in the case where the semiconductor 406a has a layered crystal structure and oxygen movement hardly occurs across the layer, the semiconductor 406a is preferably a layer having moderately low crystallinity.

In order to allow excess oxygen (oxygen) released from the insulator 432 to reach the semiconductor 406b, the semiconductor 406a preferably has crystallinity enough to transmit excess oxygen (oxygen). For example, in the case where the semiconductor 406a is a CAAC-OS, excess oxygen (oxygen) cannot be transmitted if the entire layer is changed to CAAC; thus, a structure having a gap in part is preferable. For example, the CAAC ratio of the semiconductor 406a may be less than 100%, preferably less than 98%, more preferably less than 95%, more preferably less than 90%.

In order to increase the on-state current of the transistor 490, the thickness of the semiconductor 406c is preferably as small as possible. For example, the semiconductor 406c may have a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 406c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 406b where a channel is formed. Therefore, the semiconductor 406c preferably has a certain thickness. For example, the semiconductor 406c may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. The semiconductor 406c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulator 402 and the like.

In order to increase reliability, the semiconductor 406a is preferably thick and the semiconductor 406c is thin. For example, the semiconductor 406a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the distance from the interface between the adjacent insulator and the semiconductor 406a to the semiconductor 406b where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

For example, between the semiconductor 406b and the semiconductor 406a, for example, in secondary ion mass spectrometry (SIMS), less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ And a region having a silicon concentration of less than 2 × 10 ¹⁸ atoms / cm ³ . Further, between SIMS 406b and 406C, in SIMS, it is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably less than 2 × 10 ¹⁸ atoms / cm ³ . It has a region having a silicon concentration.

In order to reduce the hydrogen concentration of the semiconductor 406b, it is preferable to reduce the hydrogen concentration of the semiconductor 406a and the semiconductor 406c. The semiconductors 406a and 406c have a SIMS of 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and even more preferably 5 ×. The region has a hydrogen concentration of 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration of the semiconductor 406b, it is preferable to reduce the nitrogen concentrations of the semiconductor 406a and the semiconductor 406c. The semiconductor 406a and the semiconductor 406c are less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and further preferably 5 × in SIMS. The region has a nitrogen concentration of 10 ¹⁷ atoms / cm ³ or less.

The above is the structure and other elements of the oxide semiconductor that can be applied to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, and the like. By using the above oxide semiconductor for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, and the like, the transistor 490 can have favorable electrical characteristics. For example, excellent subthreshold characteristics and extremely small off-current can be obtained. Moreover, a high on-current and a good switching speed can be obtained. Also, a high breakdown voltage can be obtained.

(Embodiment 5)
An example of a structure of a semiconductor device to which the semiconductor device according to one embodiment of the present invention is applied is described with reference to FIGS.

A semiconductor device 300 illustrated in FIG. 16 includes a CPU core 301, a power management unit 321, and a peripheral circuit 322. The power management unit 321 includes a power controller 302 and a power switch 303. The peripheral circuit 322 includes a cache 304 having a cache memory, a bus interface (BUS I / F) 305, and a debug interface (Debug I / F) 306. The CPU core 301 includes a data bus 323, a control device 307, a PC (program counter) 308, a pipeline register 309, a pipeline register 310, an ALU (Arithmetic logic unit) 311, and a register file 312. Data exchange between the CPU core 301 and the peripheral circuit 322 such as the cache 304 is performed via the data bus 323.

The semiconductor device according to one embodiment of the present invention can be applied to the cache 304. As a result, the cache can be reduced in size, increased in density, or increased in capacity, and the semiconductor device can be downsized, the semiconductor device having a larger storage capacity, the semiconductor device operating at higher speed, or the semiconductor device having lower power consumption. Can provide.

The control device 307 controls the operations of the PC 308, the pipeline register 309, the pipeline register 310, the ALU 311, the register file 312, the cache 304, the bus interface 305, the debug interface 306, and the power controller 302, thereby providing an input. A function of decoding and executing an instruction included in a program such as an executed application.

The ALU 311 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.

The cache 304 has a function of temporarily storing frequently used data. The PC 308 is a register having a function of storing an address of an instruction to be executed next. Although not shown in FIG. 16, the cache 304 is provided with a cache controller that controls the operation of the cache memory.

The pipeline register 309 is a register having a function of temporarily storing instruction data.

The register file 312 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 311, and the like.

The pipeline register 310 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 311 or data obtained as a result of the arithmetic processing of the ALU 311.

The bus interface 305 functions as a data path between the semiconductor device 300 and various devices outside the semiconductor device 300. The debug interface 306 has a function as a signal path for inputting a command for controlling debugging to the semiconductor device 300.

The power switch 303 has a function of controlling supply of power supply voltage to various circuits other than the power controller 302 included in the semiconductor device 300. The various circuits belong to several power domains, and the power switches 303 control whether or not the various circuits belonging to the same power domain are supplied with the power switch 303. The power controller 302 has a function of controlling the operation of the power switch 303.

The semiconductor device 300 having the above structure can perform power gating. The flow of power gating operation will be described with an example.

First, the CPU core 301 sets the timing for stopping the supply of the power supply voltage in the register of the power controller 302. Next, a command to start power gating is sent from the CPU core 301 to the power controller 302. Next, various registers and the cache 304 included in the semiconductor device 300 start data saving. Next, supply of power supply voltage to various circuits other than the power controller 302 included in the semiconductor device 300 is stopped by the power switch 303. Next, when an interrupt signal is input to the power controller 302, supply of power supply voltage to various circuits included in the semiconductor device 300 is started. Note that a counter may be provided in the power controller 302 and the timing at which the supply of the power supply voltage is started may be determined using the counter without depending on the input of the interrupt signal. Next, the various registers and the cache 304 start data restoration. Next, the execution of the instruction in the control device 307 is resumed.

Such power gating can be performed in the entire processor or in one or a plurality of logic circuits constituting the processor. Further, power supply can be stopped even in a short time. For this reason, power consumption can be reduced with fine granularity spatially or temporally.

By applying the semiconductor device according to one embodiment of the present invention to the cache 304, the cache 304 can hold data for a long time even when supply of power supply voltage is stopped. Therefore, when power gating is performed, the data in the cache 304 can be kept, and there is no need to save. As a result, power and time can be reduced. In other words, when a volatile SRAM is used without applying the semiconductor device according to one embodiment of the present invention to the cache 304, the cache data is discarded or saved outside the semiconductor device 300 during power gating. There is a need. In the case of discarding data, energy and time for retrieving data from the outside of the semiconductor device 300 at the time of recovery (that is, energy and time necessary for warming up the cache) are required; however, the semiconductor according to one embodiment of the present invention This can be reduced by applying the device. When data is saved, power and time required for saving and restoring data are required; however, this can be reduced by applying the semiconductor device of one embodiment of the present invention.

Note that a semiconductor device according to one embodiment of the present invention includes not only a CPU but also a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller ID), and an RF (Microcontroller ID). (Frequency Identification), custom LSI, and the like.

(Embodiment 6)
An example of a structure of a semiconductor device to which the semiconductor device according to one embodiment of the present invention is applied is described with reference to FIGS.

A semiconductor device 800 illustrated in FIG. 17 is an example of a structure of an RFID tag. The RFID tag in this embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of these characteristics, the RFID tag can be used in an individual authentication system that identifies an article by reading individual information such as the article.

A semiconductor device 800 illustrated in FIG. 17 includes an antenna 804, a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811.

The semiconductor device according to one embodiment of the present invention can be applied to the memory circuit 810. As a result, the memory circuit 810 can be reduced in size, increased in density, or increased in capacity, and a downsized semiconductor device or a semiconductor device having a larger storage capacity can be provided.

The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double voltage rectification, and the signal rectified by a capacitive element provided in the subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

The demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804.

A logic circuit 809 is a circuit for decoding and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.

Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged facing each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. The semiconductor device 800 described in this embodiment can be used for any method.

Note that the above-described circuits can be appropriately disposed as necessary.

Note that in any circuit other than the memory circuit 810, the transistor including the oxide semiconductor described in the above embodiment can be used as the n-channel transistor. Since the transistor has a low off-state current and a high on-state current, both a low leakage current and a high-speed operation can be achieved. Alternatively, the element including the rectifying action included in the demodulation circuit 807 may be a transistor including the oxide semiconductor described in the above embodiment. Since the transistor has a low off-state current, the reverse current of the element that exhibits a rectifying function can be reduced. As a result, excellent rectification efficiency can be realized. In addition, since transistors using these oxide semiconductors can be manufactured by the same process, the semiconductor device 800 can have high performance while suppressing process cost.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 7)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an example in which the semiconductor device is applied to an electronic device including the electronic component will be described with reference to FIGS.

FIG. 18A illustrates an example in which the semiconductor device described in the above embodiment is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A semiconductor device including a transistor as shown in FIG. 3 is completed by assembling a plurality of detachable components on a printed circuit board through an assembly process (post-process).

About a post process, it can be completed by passing through each process shown to Fig.18 (a). Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). By reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and reduce the size of the component.

A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with resin, the built-in circuit part and wire can be protected from mechanical external force, and deterioration of characteristics due to moisture and dust can be reduced. .

Next, the lead frame lead is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, an electronic component having a memory device that is reduced in size, increased in density, or increased in capacity can be realized. The electronic component is an electronic component that has been reduced in size or increased in storage capacity.

FIG. 18B is a schematic perspective view of the completed electronic component. FIG. 18B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 700 shown in FIG. 18B shows a lead 701 and a semiconductor device 703. An electronic component 700 shown in FIG. 18B is mounted on a printed circuit board 702, for example. A plurality of such electronic components 700 are combined and each is electrically connected on the printed circuit board 702 to complete a substrate (mounting substrate 704) on which the electronic components are mounted. The completed mounting board 704 is provided inside an electronic device or the like.

The above-described electronic component is used in an image reproduction apparatus (typically an apparatus having a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) including a display device, a personal computer, and a recording medium. Can be applied. Other electronic devices that can use the above-described electronic components include mobile phones, portable game machines, portable data terminals, electronic books, video cameras, digital still cameras and other cameras, goggle-type displays (head-mounted displays). ), Navigation systems, sound reproducing devices (car audio, digital audio player, etc.), copiers, facsimiles, printers, printer multifunction devices, automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 19A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 19A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 19B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 19C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 19D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 19E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.

FIG. 19F illustrates an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

By applying electronic components including a semiconductor device (memory cell) according to one embodiment of the present invention to each of these electronic devices and having a memory device with a reduced size, a higher density, or an increased capacity, a small electronic device A device or a high-performance electronic device can be provided.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

For example, in this specification and the like, when X and Y are explicitly described as being connected, when X and Y are electrically connected, X and Y are functionally connected. The case where they are connected and the case where X and Y are directly connected are included. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from A is transmitted to B, X and Y are functionally connected. To do.

Note that when X and Y are explicitly described as being electrically connected, when X and Y are electrically connected (that is, another element between X and Y). Or when X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

In addition, about the content which is not prescribed | regulated in the drawing and text in a specification, the one aspect | mode of the invention which prescribed | regulated removing the content can be comprised. Or, when a numerical value range indicated by an upper limit value and a lower limit value is described for a certain value, the range is unified by arbitrarily narrowing the range or by removing one point in the range. One aspect of the invention excluding a part can be defined. Thus, for example, it can be defined that the prior art does not fall within the technical scope of one embodiment of the present invention.

As a specific example, a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it can be specified as an invention that the circuit does not include the sixth transistor. Alternatively, it can be specified that the circuit does not include a capacitor. Furthermore, the invention can be configured by specifying that the circuit does not have the sixth transistor having a specific connection structure. Alternatively, the invention can be configured by specifying that the circuit does not include a capacitor having a specific connection structure. For example, the invention can be defined as having no sixth transistor whose gate is connected to the gate of the third transistor. Alternatively, for example, it can be specified that the first electrode does not include a capacitor connected to the gate of the third transistor.

As another specific example, a certain value is described as, for example, “It is preferable that a certain voltage is 3 V or more and 10 V or less”. In that case, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is −2 V or higher and 1 V or lower. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is 13 V or higher. Note that, for example, the invention can be specified such that the voltage is 5 V or more and 8 V or less. In addition, for example, it is also possible to prescribe | regulate invention that the voltage is about 9V. Note that, for example, the voltage is 3 V or more and 10 V or less, but the invention can be specified except for the case where the voltage is 9 V. Note that even if a value is described as “preferably in such a range”, “preferably satisfying these”, or the like, the value is not limited to the description. That is, even if it is described as “preferred” or “preferred”, the description is not necessarily limited thereto.

As another specific example, it is assumed that a certain value is described as, for example, “a certain voltage is preferably 10 V”. In that case, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is −2 V or higher and 1 V or lower. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is 13 V or higher.

As another specific example, it is assumed that the property of a certain substance is described as, for example, “a certain film is an insulating film”. In that case, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an organic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an inorganic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a conductive film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a semiconductor film.

As another specific example, it is assumed that a certain laminated structure is described as “a film is provided between the A film and the B film”, for example. In that case, for example, the invention can be defined as excluding the case where the film is a laminated film of four or more layers. Alternatively, for example, the invention can be defined as excluding the case where a conductive film is provided between the A film and the film.

Note that one embodiment of the invention described in this specification and the like can be implemented by various people. However, the implementation may be performed across multiple people. For example, in the case of a transmission / reception system, company A may manufacture and sell a transmitter, and company B may manufacture and sell a receiver. As another example, in the case of a light emitting device having a transistor and a light emitting element, the semiconductor device in which the transistor is formed is manufactured and sold by Company A. In some cases, company B purchases the semiconductor device, forms a light-emitting element on the semiconductor device, and completes the light-emitting device.

In such a case, an aspect of the invention that can claim patent infringement can be configured for either Company A or Company B. In other words, it is possible to constitute an aspect of the invention that only Company A implements, and as an aspect of another invention, it is possible to constitute an aspect of the invention that is implemented only by Company B. is there. In addition, it is possible to determine that one embodiment of the invention that can claim patent infringement against Company A or Company B is clear and described in this specification and the like. For example, in the case of a transmission / reception system, even if there is no description in the case of only a transmitter, or in the case of only a receiver in this specification, etc., one aspect of the invention can be configured with only the transmitter, One embodiment of another invention can be formed using only a receiver, and it can be determined that one embodiment of the invention is clear and described in this specification and the like. As another example, in the case of a light-emitting device including a transistor and a light-emitting element, the description in the case of only a semiconductor device in which a transistor is formed or the description in the case of only a light-emitting device having a light-emitting element is not included in this specification and the like. Even in this case, one embodiment of the invention can be formed using only a semiconductor device in which a transistor is formed, and one embodiment of the invention can be formed using only a light-emitting device including a light-emitting element. It is clear and can be determined to be described in this specification and the like.

Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when there are a plurality of cases where the terminal is connected, it is not necessary to limit the terminal connection to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There are cases.

Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

Note that in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the present invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods It is possible to extract one part of a drawing or a sentence on which one or more of the above are described and constitute one embodiment of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, M (M is an integer and M <N) layers are extracted from a cross-sectional view including N layers (N is an integer) to form one embodiment of the invention. It is possible to do. As another example, M elements (M is an integer and M <N) are extracted from a flowchart including N elements (N is an integer) to form one aspect of the invention. It is possible to do. As another example, a part of the elements is arbitrarily extracted from the sentence “A has B, C, D, E, or F”. "A has E and F", "A has C, E and F", or "A has B, C, D and E" It is possible to constitute one aspect of the invention.

Note that in this specification and the like, when at least one specific example is described in a drawing or text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. To be understood. Therefore, in the case where at least one specific example is described in a drawing or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. One embodiment of the invention is clear.

Note that in this specification and the like, at least the contents shown in the drawings (may be part of the drawings) are disclosed as one embodiment of the invention, and can constitute one embodiment of the invention It is. Therefore, if a certain content is described in the figure, even if it is not described using sentences, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention. Is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. And it can be said that one aspect of the invention is clear.

400 Substrate 406a, 406b, 406c Semiconductor 407a, 407b, 407c Semiconductor 408a, 408b, 408c Semiconductor 409c, 410c Semiconductor 411, 412, 413 Insulator 414, 415 Insulator 416a, 416b Conductor 417a, 417b Conductor 418a, 418b Conductive Body 423 Conductor 426, 427, 428 Conductor 429, 430 Conductor 432, 434, 436 Conductor 442, 444, 446 Conductor 462, 464, 466 Insulator 490, 491, 492 Transistor 493, 494 Capacitance element 500 Memory Cell 501 area

Claims (14)

A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor on the first insulator;
A second insulator on the semiconductor;
A second conductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
The semiconductor is
A first region that overlaps the first conductor and does not overlap the second conductor;
A second region that overlaps the second conductor and does not overlap the first conductor;
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. In claim 1,
The area of the region sandwiched between the first region and the second region of the semiconductor is less than or equal to the area of the first region and less than or equal to the area of the second region. . A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor on the first insulator;
A second insulator on the semiconductor;
A second conductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
The semiconductor is
A third region overlapping the first conductor;
A fourth region overlapping the second conductor,
The third region and the fourth region do not overlap,
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. In claim 3,
An area of a region sandwiched between the third region and the fourth region of the semiconductor is not more than the area of the first region and not more than the area of the second region. . A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor on the first insulator;
A second insulator on the semiconductor;
A second conductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
The semiconductor is
A third region overlapping the first conductor;
A fourth region overlapping the second conductor;
A fifth region where the third region and the fourth region overlap,
The area of the fifth region is 25% or less of the area of the third region and 25% or less of the area of the fourth region;
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor in a position overlapping the first conductor on the first insulator;
A second insulator on the semiconductor;
A second conductor in a position overlapping the semiconductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
When viewed from above, the end of the first conductor and the end of the second conductor do not overlap,
The distance between the end portion of the first conductor and the end portion of the second conductor is not more than the width of the first conductor and not more than the width of the second conductor.
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor in a position overlapping the first conductor on the first insulator;
A second insulator on the semiconductor;
A second conductor in a position overlapping the semiconductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
The first conductor and the second conductor have regions overlapping each other,
The area of the overlapping region is 25% or less of the area of the first conductor and 25% or less of the area of the second conductor;
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. A first transistor;
A second transistor;
A third transistor;
A first capacitive element;
A second capacitive element;
Have
The third transistor is
A first conductor;
A first insulator on the first conductor;
A semiconductor in a position overlapping the first conductor on the first insulator;
A second insulator on the semiconductor;
A second conductor in a position overlapping with the oxide semiconductor on the second insulator;
A third conductor and a fourth conductor connected to the semiconductor;
Have
When viewed from above, the end of the first conductor and the end of the second conductor are aligned,
One of the source electrode and the drain electrode of the first transistor is electrically connected to the second conductor of the third transistor and the one electrode of the first capacitor,
One of the source electrode and the drain electrode of the second transistor is electrically connected to the first conductor of the third transistor and the one electrode of the second capacitor element. In any one of Claims 1 to 8,
The channel formation region of the first transistor is formed of an oxide semiconductor,
The channel formation region of the second transistor is formed of an oxide semiconductor,
The semiconductor device of the second transistor is an oxide semiconductor. In any one of Claims 1 thru | or 9,
The third transistor is stacked on the second transistor,
The semiconductor device, wherein the first transistor is stacked on the third transistor. In any one of Claims 1 thru | or 9,
The first transistor is stacked on the second transistor,
The channel formation region of the first transistor and the channel formation region of the second transistor overlap each other. In any one of Claims 1 thru | or 11,
The first transistor, the second transistor, the third transistor, the first capacitor element, and the second capacitor element maintain any one of 16 values to 1024 values. Semiconductor device. A semiconductor device according to any one of claims 1 to 12,
An antenna,
RFID tag having A semiconductor device according to any one of claims 1 to 12,
A printed wiring board;
Electronic equipment having