JPWO2013150636A1 - Atomic order flattening surface treatment method and heat treatment apparatus for silicon wafer - Google Patents

Abstract

A slip line does not exist in a silicon wafer having a plurality of terraces that are stepped in atomic steps on the surface.

Description

  The present invention relates to a method for planarizing a surface of a silicon wafer for producing a semiconductor device such as an IC or LSI.

  Unevenness on the surface of a silicon wafer for creating a semiconductor device such as an IC or LSI hinders improvement in current drive capability of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as shown in Non-Patent Document 1, for example. It is a factor, and it is required to make the surface as flat as possible.

  On the other hand, it has been reported that when a silicon wafer is heat-treated in an Ar atmosphere at 1200 ° C., an ultimate flat surface in which atomic level steps and terrace structures appear can be formed (Non-patent Document 2).

However, high-temperature processing at 1200 ° C. is not realistic when mass production is considered.

On the other hand, Patent Document 1 describes that a 200 mmφ wafer surface can be flattened in an atomic order without slipline by performing a heat treatment at 850 ° C. in an atmosphere of high purity Ar gas. .

International Publication Number WO2011 / 096417A1

T. Ohmi, K. Kotani, A. Teramoto, and M. Miyashita, IEEE Elec. Dev. Lett., 12, 652 (1991). L. Zhong, A. Hojo, Y. Matsushita, Y. Aiba, K. Hayashi, R. Takeda, H. Shirai, and H. Saito, Phy. Rev. B. 54, 2304 (1996).

  However, according to the method of Patent Document 1, it is described that crystal defects called slip lines are not formed even when a large-diameter silicon wafer such as 200 mmφ is heat-treated at a low temperature of 850 ° C. in an atmosphere of high-purity Ar gas. However, it is disclosed in Patent Document 1 whether it is suitable for mass production, whether it can be applied to a silicon wafer having a larger diameter, or even if it can be applied, the yield is high enough to be suitable for mass production. Not proposed.

  That is, Patent Document 1 does not disclose whether or not the formation of crystal defects can be prevented even when a large number of large-diameter silicon wafers are continuously and continuously processed and mass-produced.

  The present invention seeks to achieve mass production in pursuit of problems in mass production of slip-lineless, large-diameter silicon wafers with flattened atomic order.

  Specifically, one of the objects of the present invention is that even when the diameter is larger than 200 mmφ, the atomic order flattening process without slipline is performed with good yield, and even if the heat treatment apparatus is used repeatedly, it is equivalent to the initial wafer. It is an object of the present invention to provide an atomic order flattening surface treatment method for a silicon wafer, which can obtain a silicon wafer having the following atomic order surface flatness with high yield.

  Another object of the present invention is to use a higher-purity heat treatment atmosphere gas, and to achieve a high-yield high-yield atomic order planarization surface treatment at a lower temperature and with a smaller amount of gas used for larger diameter wafers. It is an object of the present invention to provide an atomic order planarization surface treatment method for a silicon wafer that can be performed by the above method.

  In order to solve the above-described problem, according to the first aspect of the present invention, a gas transport path for introducing a heat treatment atmosphere gas from the outside into the heat treatment space of the silicon wafer of the heat treatment apparatus has a joint with the heat treatment apparatus. The double space structure has an inner space communicating with the heat treatment space and an outer space not communicating with the heat treatment space and exhausting the transported gas to the outside. Atomic order of silicon wafer, characterized in that in the heat treatment process of a silicon wafer, the heat treatment atmosphere gas is caused to flow in the inner space and the heat treatment atmosphere gas or a gas equivalent to the heat treatment atmosphere gas is caused to flow in the outer space. A planarized surface treatment method is provided.

  According to the second aspect of the present invention, in the atomic order flattening surface treatment method for a silicon wafer by surface heat treatment, the heat treatment space in which the silicon wafer in the heat treatment apparatus is installed has a water content of 0.2 vol.ppb or less, There is provided an atomic order planarization surface treatment method for a silicon wafer, characterized in that heat treatment is performed at a heat treatment temperature of 900 ° C. or lower while introducing a heat treatment atmosphere gas having an oxygen content of 0.1 vol.

  According to a third aspect of the present invention, in the second aspect, a heat treatment temperature of 900 vol.% While introducing a heat treatment atmosphere gas having a water content of 0.01 vol. Ppb or less and an oxygen content of 0.02 vol. Ppb or less. There is provided an atomic order planarization surface treatment method for a silicon wafer, characterized by performing a heat treatment at a temperature not higher than ° C.

  According to the present invention, it is possible to provide a silicon wafer having surface flatness on the order of atoms and having no slip line even if the wafer has a large area of 200 mmφ or more.

  In addition, according to the present invention, by continuously using a higher-purity heat treatment atmosphere gas, the atomic order is flattened more quickly at a lower temperature and with a smaller amount of gas used for larger diameter wafers. Surface treatment can be performed with high yield.

It is a figure which shows the result (sample number 4) of a X-ray topography when heat-processing a silicon wafer on various conditions. It is typical explanatory drawing for demonstrating the relationship between the off angle of the silicon wafer which concerns on embodiment of this invention, and terrace width. It is typical explanatory drawing for demonstrating the typical example which is one of the suitable heat processing apparatuses used with the Example of this invention. FIG. 4 is a schematic explanatory diagram for enlarging and explaining a portion A shown in FIG. 3. FIG. 4 is a schematic explanatory diagram for enlarging and explaining a portion B shown in FIG. 3. (A) is typical explanatory drawing for expanding and explaining the portion C shown in Drawing 3, and shows the structure currently used by related technology here. FIG. 4B is a schematic explanatory diagram for explaining a part C shown in FIG. 3 in an enlarged manner, and shows a structure used in the present invention. It is a photograph figure which shows the AFM image of the sample surface of Example 1, 4-1 and Comparative Example 1,2. It is a typical top view showing an example at the time of forming MOSFET on a silicon wafer concerning this embodiment. It is typical sectional drawing of the source-drain direction of FIG. 3 is a graph showing a temperature profile during heat treatment of Example 1. It is a photograph figure which shows the AFM image of the sample surface of Example 5 and Comparative Examples 3-5 before and after oxidation (before and after treatment). It is a figure which shows the drain voltage-drain current characteristic of Example 6 and Comparative Example 6. It is a photograph figure which shows the AFM image of the sample surface of Example 4-1. It is a figure which shows the evaluation result (evaluation area: 1 mm x 1 mm) of a cumulative failure rate (Cumulative Failure "%"). It is a figure which shows the evaluation result (evaluation area: 4 mm x 4 mm) of a cumulative failure rate (Cumulative Failure "%"). It is a figure which shows the experimental result which evaluated the influence degree to the planarization process of heat processing temperature and Ar flow volume.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. First, the silicon wafer according to the present embodiment will be briefly described.

  The silicon wafer that has been subjected to the atomic order flattening surface treatment by the surface treatment method of the present invention has a plurality of terraces formed on the surface in steps of one atomic layer, and has no slip line. .

  Here, the “slip line” means a kind of “crystal defect” that occurs when silicon atoms regularly arranged are displaced due to high temperature when a silicon wafer is heat-treated. That is, the silicon wafer obtained by the surface treatment method of the present invention has a structure free from crystal defects.

  Moreover, the state in which a plurality of terraces stepped in atomic order steps are formed on the surface means a state as shown in FIG.

  As schematically shown in FIG. 2, the surface of the silicon wafer according to the present embodiment is inclined from the Just (100) plane by an off angle (θ).

  In FIG. 2, the crystal on the substrate surface is the (100) plane, and the off angle with respect to the (100) plane inclined by 36 ° in the <011> direction with respect to the <01-1> direction. The case where the surface orientation is tilted by 0.06 ° is shown.

As shown in FIG. 2, at the atomic level, when the substrate surface is inclined by the off angle (θ), the lattice points of the surface are different. The positions where the lattice points on the surface are switched are steps S _A and S _B. The height of this step is 0.13 nm, which is one atomic step on the silicon (100) surface.

The number of steps and terraces at this time is expressed by the equation (1) as shown in FIG.
L = 0.13 / tan θ (nm) (1)
L: Terrace width, θ: Off angle from (100) plane

  The terrace width varies by several atoms at the atomic level. However, the variation is small on the order of nm, and the influence on the characteristics can be ignored or within an extremely small range even if there is an influence. Therefore, it can be said that the terrace width is substantially the same width. Also, the direction of the step is not a straight line, and there are irregularities of several atoms at the atomic level, but the irregularities are also small in the order of nm, and the influence on the characteristics can be ignored or even within the extremely small range. Accordingly, since the steps are substantially straight and can be regarded as one direction, it can be said that the steps are formed in substantially the same direction. The present inventors have confirmed that the relationship between the terrace width L obtained from the AFM image and the off angle obtained by the X-ray diffraction measurement is in good agreement with the result of the equation (1).

  That is, the number of steps formed on the silicon surface is one atom, and the off-angle is also considered to be substantially the same as an average angle. In the following description, the step direction is simply described as being the same direction, the terrace width being the same width, and the off-angle being the same angle.

  As described above, in order to obtain a silicon wafer in which a plurality of terraces stepped in atomic steps are formed on the surface and no slip line is present, heat treatment is performed in the heat treatment space of the silicon wafer of the heat treatment apparatus. A gas transport path for introducing atmospheric gas from the outside has a double space structure separated at a joint with the heat treatment apparatus, and the double space structure has an inner space communicating with the heat treatment space and an outer space. The space is structured not to communicate with the heat treatment space but to exhaust the transported gas to the outside, and in the heat treatment process of the silicon wafer, the heat treatment atmosphere gas flows into the inner space and the heat treatment atmosphere gas flows into the outer space. Alternatively, the atomic order planarization surface treatment may be performed by flowing a gas equivalent to the heat treatment atmosphere gas.

  FIG. 3 shows a schematic explanatory view of an example of a heat treatment apparatus preferably used for embodying the present invention. A heat treatment apparatus 300 shown in FIG. 3 includes an upper installation table 301 and a lower installation table 302, both of which have a two-layer structure.

  An outer tube 303 is installed on the upper mounting table 301, and an SiC (silicon carbide) tube 304, an inner tube 305, and a wafer setting table 306 are arranged inside the outer tube 303 from the outside of the figure.

  The external tube 303 is made of a highly heat-resistant glassy material such as quartz and has a cylindrical structure having a double structure provided with a hollow. The external tube 303 has a gas inlet 307 and a gas exhaust port 308 as shown in the figure, and the gas flows through the hollow portion 309 having a double structure from the gas inlet 307 toward the gas exhaust port 308. It is like that. A heater 310 provided at a desired pitch is attached to the outside of the external tube 303.

  When the outer tube 303 is made of quartz so that the inner tube 303 can be easily observed from the outside when the heat treatment is performed for a long time or repeatedly, the metal caused by the heater 310 passes through the outer tube 303 and slightly enters the heat treatment apparatus. However, it invades. In order to prevent this point, an inert gas, for example, Ar gas is flowed into the hollow portion 309 of the outer tube 303 so that the metal does not enter the heat treatment space.

  Details of this point will be described with reference to FIG. When the heater wire 310a outside the outer tube 303 continues to generate heat in order to maintain the heat treatment temperature in the heat treatment apparatus, the metal is released from the heater wire 310a to become the floating metal 401, and the floating metal 401 is exposed to the outside. It passes through the outer wall 303a of the tube 303 and enters the inside of the apparatus.

  At that time, if a flow of an inert gas such as Ar gas is formed in the hollow portion 309 of the outer tube 303 in advance, the released metal is discharged from the apparatus together with the Ar gas through the gas discharge port 308 by the gas flow. , It does not pass through the inner wall 303b of the outer tube 303 and enter the inside of the apparatus.

  The space between the outer tube 303 and the inner tube 305 is maintained at a desired degree of vacuum as necessary during heat treatment so that the inner tube 305 can be kept clean.

  A gas flow path 311 for introducing a heat treatment atmosphere gas into the internal tube 305 from the outside is provided outside the internal tube 305. The gas flow path 311 communicates with a gas inlet means 312 provided in the upper part of the inner tube 305 and has a gas introduction path 313 for taking in a heat treatment atmosphere gas from the outside on the upstream side.

  The gas inlet means 312 is provided with pores for introducing the introduced gas into the internal tube 305 in accordance with the desired specifications and design. The internal tube 305 extends downward to the vicinity of the lower installation table 302 and communicates with a gas exhaust path 314 for exhausting the heat treatment atmosphere gas in the internal tube 305 at an intermediate position between the upper installation table 301 and the lower installation table 302. ing.

  The wafer setting table 306 is provided with a predetermined number of grooves for setting wafers on the inside, and has a structure capable of performing heat treatment from one to many simultaneously.

When a wafer is set on the wafer setting table 306, as shown in FIG. 3, a predetermined number of dummy wafers 319 are arranged at the upper and lower positions of the wafer to be heat-treated (process wafer 318), and the entire surface of the process wafer 318 is placed. Heat and maintain uniformly. As a result, the entire heat-treated surface of the process wafer 318 is maintained at a uniform and uniform temperature.

  A heat insulation structure 315 is disposed below the wafer setting table 306 in order to make uniform the heat distribution in the space where the wafer setting table 306 is placed. The heat insulation structure 315 is preferably a ladder structure made of, for example, quartz. In particular, if it is made of foamed quartz, the shape can be made arbitrarily and the apparent heat capacity can be increased, which is desirable.

  External pipes 316a and 316b are connected to the gas introduction path 313 and the gas exhaust path 314, respectively, as shown.

  In the present invention, the following contrivances are applied to the connection position of this external pipe (part B indicated by a dotted-line arrow) and a place sealed by an O-ring (part C indicated by a dotted-line arrow). .

  First, a description will be given with reference to FIG. FIG. 5 (a) illustrates the method according to the related art, and (b) illustrates the method of the present invention.

  If there is a joint in the pipe, no matter how tightly it is sealed, it will be used for a long time, and the number of repetitions will increase slightly. Revealed by the inventors. No matter how purified heat treatment atmosphere gas is used, atmospheric components gradually invade from the joint as time passes and back diffuse into the heat treatment space, contaminating the heat treatment atmosphere. Although the amount of atmospheric components that cause pollution is very small, water components and oxygen components can greatly affect the heat treatment even with a very small amount, have the flatness of the target atomic order, and are slip lineless. Large area silicon wafers cannot be produced with high productivity. That is, it becomes impossible to mass-produce a large area silicon wafer without a slip line.

  The quartz pipe 501 and the external pipe 316a constituting the gas introduction path 313 are connected so that the heat treatment atmosphere gas can be introduced from the outside into the heat treatment space of the heat treatment apparatus.

According to the research results of the present inventors, if the heat treatment apparatus is used for a long time or is used repeatedly, even if an attempt is made to cut off the air intrusion by making the connection at the connection position (joint portion 500) more reliable, there is a change over time. The air gradually enters from the joint 500.

  In order to prevent this, in the present invention, as shown in FIG. 5B, the periphery of the joint portion 500 is surrounded by a pair of purge flanges 502 a and 502 b, and the space between the joint portion 500 and the flange 502 is purged. The structure is devised so that the invasion of the atmosphere from the joint portion 500 can be completely prevented by flowing the working gas at a desired relative positive pressure. A purge gas is introduced from the pipe 503.

  As the purge gas, the same kind of gas as the heat treatment atmosphere gas or the same gas is used. In particular, it is desirable to use the same type of gas as the heat treatment atmosphere gas.

  In FIG. 5B, the gas introduction path 313 portion of the heat treatment atmosphere gas has been described, but the gas exhaust path 314 also has the same structure.

  Next, a structural device in the present invention of a portion (portion C indicated by a dotted-line arrow) that is sealed with an O-ring or the like will be described with reference to FIG. FIG. 6A shows a structure according to the related art, and FIG. 6B shows a structure according to the present invention.

  As explained in FIG. 5, even if it is tried to maintain the airtightness by precisely sealing with an O-ring or the like, the change over time over a long period of time, especially the change over time when heat is applied, reduces the airtightness. As a result, the atmosphere gradually enters through a slight gap between the device and the O-ring. For the purpose of preventing this, as shown in FIG. 6 (b), a purge channel 603 is provided inside the mounting flange 602 and the purge gas is allowed to flow at a desired relative positive pressure, thereby preventing the atmosphere from entering the apparatus. Prevent completely.

  According to the study by the present inventors, a commercially available high-purity argon (Ar) gas, which is relatively easily available, is used as a heat treatment atmosphere gas, and heat treatment is performed at a high temperature, for example, around 1200 ° C., with a conventional heat treatment apparatus. In this case, a sliplineless silicon wafer can be formed. However, in the case of a large-area wafer of about 200 mmφ, it is possible to obtain sliplineless atomic order flatness over the entire wafer surface in consideration of productivity. The conclusion is that it is practically difficult.

The purity of commercially available high-purity argon (Ar) gas, which is relatively easy to obtain, is of the Grade 1 (G1) class in terms of gas quality standards, and exceeds 99.9999 vol%, and contains oxygen (O ₂ ). The amount is less than 0.1 vol. Ppm, and the water (H ₂ O) content is less than −80 ° C. in terms of dew point.

  In the earlier application of the present inventors (Patent Document 1), the purity of argon (Ar) gas is further increased so that the moisture content is 0.2 vol.ppb or less and the oxygen content is 0.1 vol.ppb or less. ) By using gas, a silicon wafer having slip-lineless atomic order flatness over the entire surface of a large area wafer of about 200 mmφ is heat-treated in a much lower temperature range of 800 to 900 ° C. It is shown to be obtained by doing.

  The first and third aspects of the present invention described above are further developments of this technology, and a slip lineless atomic order flattening process can be produced at a high yield even for large-diameter silicon wafers of 200 mmφ or more. It is an atomic order surface flattening method that can be implemented with good performance and is optimal for mass production.

  Furthermore, in the third aspect of the present invention described above, the atomic order flattening surface can be performed more quickly at a lower temperature and with a smaller amount of gas used for a larger diameter wafer by using a heat treatment atmosphere gas with higher purity. Processing can be performed with high yield.

  The inner tube 305 used at this time is preferably as purified as possible.

In the present invention, a gas species that is inert (non-reactive) to the silicon wafer surface is used as the heat treatment atmosphere gas. As such a gas, it is preferable to use a rare gas such as Ar (argon) or He (helium), an inert gas such as N ₂ (nitrogen), or a mixed gas obtained by mixing two or more of these gases. desirable. In particular, it is desirable to use Ar (argon) in the present invention.

  It is desirable that the temperature during the heat treatment be 900 degrees or less. By setting the heat treatment temperature to 900 ° C. or less, even when the silicon wafer has a large diameter of 300 mmφ or more, a wafer having no slip line can be obtained.

  However, since a flat surface in the atomic order cannot be obtained by heat treatment at a very low temperature, the temperature during the heat treatment is preferably 700 ° C. or higher, more preferably 750 ° C. or higher, and further preferably 800 ° C. or higher. It is desirable to do. That is, the temperature during the heat treatment is preferably in the range of 700 ° C to 900 ° C.

  As described above, a silicon wafer in which a plurality of terraces stepped in steps of one atomic layer is formed on the surface and a slip line does not exist deteriorates the current drive capability of the MOSFET when the MOSFET is formed. Thus, a MOSFET can be formed with good yield.

  Here, a method for forming a MOSFET using the silicon wafer according to the present embodiment will be described with reference to FIGS.

  First, the surface of the semiconductor substrate 901 (silicon wafer, silicon substrate) that has been subjected to the above-described treatment (heat treatment at 900 ° C. or lower) is cleaned by a cleaning method that does not use an alkaline solution.

Next, as shown in FIG. 9, for example, after a SiO ₂ film 902 is formed by a radical oxidation method in which the substrate surface is directly oxidized by oxygen radicals generated by plasma, a SiO ₂ film 903 is formed by a CVD method or the like.

  Next, an activation region in which the MOS transistor is to be formed is opened using a photolithography method or the like. At this time, as shown in FIG. 8, it is desirable that the direction parallel to the step is the carrier traveling direction so that there is no step in the source-drain direction (so that the step does not intersect the carrier traveling direction). By adopting such a configuration, it is possible to realize a MOSFET having extremely small roughness in the carrier traveling direction and high carrier mobility.

  FIG. 8 illustrates the case where the source-drain is set in a direction inclined by 54 ° in the <011> direction with respect to the <01-1> direction.

Next, as shown in FIG. 9, the SiO ₂ film 902 and the SiO ₂ film 903 in the opening are removed using the photoresist as a mask material, and the photoresist is removed. Note that the openings are formed in a plurality (a large number) of portions where the transistors are to be provided. In FIGS. 8 and 9, one opening portion and one transistor are shown. Thereafter, the exposed semiconductor surface is cleaned by a cleaning method that does not use an alkaline solution, and then a SiO ₂ film 904 is formed as a gate insulating film by radical oxidation, and polycrystalline polysilicon is formed as a gate electrode 905. Note that if the isotropic oxidation method such as the radical oxidation method, the interface flatness does not deteriorate regardless of the film thickness. Further, the gate insulating film may be formed by radical nitridation, or may be formed by combining radical oxidation and radical nitridation.

  Thereafter, a MOSFET is formed by a known MOSFET formation method.

  Specifically, by forming a source diffusion layer 906 and a drain diffusion layer 907, forming an interlayer insulating film 908, opening a contact hole, a gate extraction electrode 909, a source extraction electrode 910, and a drain extraction electrode 911, A MOSFET as shown in FIG. 9 is formed.

  In addition, the formation method of MOSFET is not specifically limited. As a method for forming the gate insulating film, for example, a method of oxidizing a semiconductor substrate isotropically or a method of nitriding may be used. In addition, element isolation methods between a large number of formed transistors may be STI (Shallow trench Isolation), LOCOS (Local Oxidation of Silicon) method, etc., and the active region surface cleaning method, oxide film, nitride film formation method, The film thickness should just be comparable.

  As described above, according to the present embodiment, the silicon wafer is configured such that a plurality of terraces that are stepped by atomic steps are formed on the surface, and no slip line exists.

  Therefore, by using the silicon wafer, even when the wafer has a large diameter (200 mmφ or more), a MOSFET and a circuit composed of the MOSFET can be manufactured with high yield.

  Hereinafter, the present invention will be described in more detail based on examples.

<Slip line evaluation>
Samples were prepared by heating a (100) -oriented silicon wafer at various heat treatment temperatures, and the presence or absence of slip lines was evaluated. The specific procedure is as follows.

(1) Preparation of sample (Example 1)
First, a silicon wafer having a diameter of 200 mmφ and a surface of (100) orientation was prepared, and the silicon wafer surface was cleaned by the following procedure. First, the surface of the silicon wafer was washed with O ₃ water for 10 minutes, washed with dilute HF (0.5 wt%) for 1 minute, and finally rinsed with ultrapure water for 3 minutes.

Thereafter, the silicon wafer is placed in the heat treatment apparatus shown in FIG. 3, and the heat treatment temperature is 850 ° C. and the heat treatment time is 180 minutes while flowing Ar at a flow rate of 0.2 ppb or less and O ₂ of 0.1 ppb or less at 20 L / min. A heat treatment was performed below.

  However, during the heat treatment process, it was not carried out as described in FIGS. 4, 5, and 6, and the heat treatment apparatus conditions were the same as those performed in the heat treatment apparatus described in FIG.

  Specifically, the silicon wafer was first heated from the state of 30 ° C. to 850 ° C. by the temperature sequence shown in FIG. 10 and held at 850 ° C. for 180 minutes. Thereafter, the temperature of the silicon wafer was lowered to 30 ° C. by the temperature sequence shown in FIG. A sample was prepared by the above procedure.

(Example 2)
A sample was prepared under the same conditions as in Example 1 except that the Ar flow rate was 10 L / min and the heat treatment time (holding time) was 540 minutes.

(Example 3)
A sample was produced under the same conditions as in Example 1 except that the Ar flow rate was 10 L / min and the heat treatment time (holding time) was 270 minutes.

(Example 4-1)
A sample was prepared under the same conditions as in Example 1 except that the Ar flow rate was 10 L / min, the heat treatment temperature was 900 ° C., and the heat treatment time was (holding time) 60 minutes.

(Example 4-2)
A sample was prepared under the same conditions as in Example 1 except that the Ar flow rate was 14 L / min, the heat treatment temperature was 800 ° C., and the heat treatment time was (holding time) 90 minutes.

(Comparative Example 1)
A sample was prepared under the same conditions as in Example 1 except that the Ar flow rate was 10 L / min, the heat treatment temperature (holding temperature) was 1100 ° C., and the heat treatment time (holding time) was 60 minutes.

(Comparative Example 2)
A sample was prepared under the same conditions as in Example 1 except that the Ar flow rate was 10 L / min, the heat treatment temperature (holding temperature) was 1200 ° C., and the heat treatment time (holding time) was 60 minutes.

(2) Evaluation of sample The presence or absence of the slip line of the produced sample was evaluated using X-ray diffraction topography (X-ray diffraction topography). For evaluation, RU-300 manufactured by Rigaku Corporation was used, and the presence or absence of a slip line was evaluated from a transmission X-ray topograph.

  The surface of the sample was observed using AFM (SPI400 manufactured by Seiko Instruments Inc.). The off-angle and direction of the sample were measured using an X-ray diffractometer (X'pert Pro manufactured by PANalitycal).

The evaluation results are shown in Table 1, and the transmission X-ray topographs of Examples 1, 2, 4 (4-1, 4-2) and Comparative Example 1 are shown in FIG.
Further, AFM images of Examples 1 and 4-1, and Comparative Examples 1 and 2 are shown in FIG.

  Furthermore, the AFM image of Example 4-2 is shown in FIG. The AFM images at the top, bottom, left, and right ends are each at a location 5 mm from the edge of the wafer, and the center AFM image is at the center (100 mm from the wafer edge). The AFM images between the lower end, the left end, and the right end are each 50 mm from the edge of the wafer.

  As is clear from Table 1 and FIGS. 1 and 13, none of the samples (Examples 1 to 4 (4-1 and 4-2)) heat-treated at 900 ° C. or lower showed a slip line, and the crystal formed by heat treatment. It was found that there were no defects. Other surface defects and point defects were not observed.

  On the other hand, in Comparative Examples 1 and 2, slip lines were observed (see FIG. 1A), and it was found that crystal defects were generated by heat treatment.

  Further, as is apparent from FIGS. 7 and 13, it is observed that in each sample, a plurality of terraces that are stepped in atomic steps are formed on the surface, and a flat surface in atomic order is observed. It turns out that it is obtained.

<Evaluation of surface irregularities by radical oxidation>
Various treatments were applied to the surface of the obtained sample, and the shape of the flat surface was evaluated. The specific procedure is as follows.

(1) Preparation of sample (Example 5)
The sample of Example 1 was subjected to radical oxidation using a microwave-excited plasma apparatus manufactured by Tokyo Electron Ltd. at a temperature of 400 ° C., 133 Pa, and a Kr / O 2 flow rate ratio of 98/2 to form a 6 nm oxide layer. did. Thereafter, the oxide film was removed using a solution in which 36 wt% HCl and 50 wt% HF were mixed in 19/1. Whether or not the oxide film was removed was judged by confirming that it became hydrophobic.

(Comparative Example 3)
The surface was thermally oxidized by heating the sample for 10 minutes at a temperature of 900 ° C. in an O ₂ atmosphere using α-8 manufactured by Tokyo Electron Co., Ltd. for the sample of Example 1 to form a 6 nm oxide layer. . Thereafter, the oxide film was removed using a solution in which 36 wt% HCl and 50 wt% HF were mixed in 19/1. Whether or not the oxide film was removed was judged by confirming that it became hydrophobic.

(Comparative Example 4)
The surface of the sample of Example 1 was thermally oxidized using α-8 manufactured by Tokyo Electron Ltd. in an O ₂ atmosphere at 1000 ° C. for 10 minutes to thermally oxidize the surface to form a 17 nm oxide layer. Thereafter, the oxide film was removed using a solution in which 36 wt% HCl and 50 wt% HF were mixed in 19/1. Whether or not the oxide film was removed was judged by confirming that it became hydrophobic.

(Comparative Example 5)
The sample of Example 1 was washed with a solution of 36 wt% HCl and 50 wt% HF mixed at 19/1 for 1 minute, and then rinsed with ultrapure water for 5 minutes (that is, the surface was not oxidized). ).

(2) Evaluation of sample Next, the surface shape of Example 5 and Comparative Examples 3 to 5 before and after oxidation (Comparative Example 5 before and after cleaning) was observed by AFM. The results are shown in FIG. Note that the AFM image in FIG. 11 is a 1 μm square.

  As shown in FIG. 11, it can be seen that the step (terrace) on the surface of the sample subjected to radical oxidation (Example 5) clearly appears even after oxidation, and the flatness of the surface on the atomic order is maintained. It was.

  On the other hand, in the samples subjected to thermal oxidation (Comparative Examples 3 and 4), it was found that the step and the terrace were unclear, and the flatness of the surface on the atomic order was deteriorated.

<Evaluation of MOSFET current-voltage characteristics>
MOSFETs as shown in FIG. 8 and FIG. 9 were fabricated according to the following procedure, and drain current-drain voltage (I _D -V _D ) characteristics were evaluated.

(1) Preparation of sample (Example 6)
First, the surface of the sample of Example 1 was prepared by T. Ohmi, “Total room temperature wet cleaning Si substrate surface,” J. Electrochem. Soc., Vol. 143, No. 9, pp. 2957-2964, Sep. 1996. It was washed by a washing method not using an alkaline solution described in. Next, after a 7 nm SiO ₂ film 902 is formed at a temperature of 400 ° C. by a radical oxidation method in which the substrate surface is directly oxidized by oxygen radicals generated by plasma, a 300 nm SiO ₂ film 3 is formed by a CVD method. Formed.

  Next, an activation region in which a MOS transistor is formed is opened by photolithography.

Next, using the photoresist as a mask material, the SiO ₂ film 902 and the SiO ₂ film 903 at the opening are removed with a solution of HCl / HF = 19/1, and the photoresist is H ₂ SO ₄ / H ₂ O ₂ = 4: Removed with 1 solution. Thereafter, the exposed semiconductor surface was cleaned by the above-described cleaning method without using an alkaline solution, and then a SiO ₂ film 904 as a gate insulating film was formed at 5.6 nm by radical oxidation, and polycrystalline polysilicon was formed as a gate electrode 905. Thereafter, the source diffusion layer 906 and the drain diffusion layer 907 are formed, the interlayer insulating film 908 is formed, the contact holes are opened, the gate extraction electrode 909, the source extraction electrode 910, and the drain extraction electrode 911 are formed by a known method. As a result, a MOSFET as shown in FIG. 9 was completed.

(Comparative Example 6)
A MOSFET was fabricated under the same conditions as in Example 5 except that the planarization process was not performed and Ra = 0.06 nm.

(2) Evaluation of sample A drain voltage was applied to the prepared sample in units of 0.5 V in a range of -3 V to 3 V, and a drain current was measured. The results are shown in FIG.

  As apparent from FIG. 12, the MOSFET of Example 6 having a flat interface has a larger drain current than that of Comparative Example 6 at the same gate voltage and drain voltage, and a good MOSFET is formed. I understood that.

<Evaluation of Cumulative Failure Rate (Cumulative Failure “%”)>
FIG. 14 is a diagram showing the results of evaluating the cumulative failure rate with the evaluation area set to 1 mm × 1 mm. The horizontal axis is the charge to breakdown Qbd, and the vertical axis is the cumulative failure rate. The more the graph is to the right, the better the performance.

  In FIG. 14, (a) is when the heat treatment temperature is set to 1100 ° C. and the surface is flattened at the atomic level, (b) is when the heat treatment temperature is set to 800 ° C. and the surface is flattened at the atomic level, (C) is a case where no leveling treatment is performed at the atomic level, and (d) is a case where the surface roughness is increased by APM after the leveling treatment. The results of forming and measuring a MOS diode by forming an oxide film are shown respectively.

  From the results shown in FIG. 14, it can be seen that Qbd is flatter, that is, (a) and (b) are larger than those having larger roughness, that is, (c) and (d). .

  FIG. 15 is a diagram similarly showing the results of evaluating the cumulative failure rate with the evaluation area set to 4 mm × 4 mm.

  In FIG. 15, (a) is the case where the heat treatment temperature is set to 1100 ° C. and the surface is flattened at the atomic level, (b) is the heat treatment temperature is set to 800 ° C. and the surface is flattened to the atomic level, (C) shows a case in which a process for flattening to the atomic level is not performed, and a measurement result obtained by forming a MOS diode by forming a 5.8 nm oxide film on each sample by a radical oxidation method is shown.

  From the results shown in FIG. 15, it can be seen that the initial failure is eliminated by performing the flattening process when the evaluation is performed with a sample having a large area.

(Example 7)
Each sample was prepared by changing the heat treatment temperature and the flow rate of Ar, which is a heat treatment atmosphere gas, from a silicon wafer having a (100) orientation on the surface, and the degree of influence of the heat treatment temperature and the Ar flow rate on the planarization treatment was examined. The presence / absence of the slip line was evaluated in the same manner as in Example 1. The specific procedure is as follows.

(1) Production of each sample First, a silicon wafer having a diameter of 300 mmφ and a surface of (100) orientation was prepared, and the silicon wafer surface was cleaned by the following procedure.

First, the surface of the silicon wafer was washed with O ₃ (ozone) water for 10 minutes, washed with diluted HF (0.5 wt%) for 1 minute, and finally rinsed with ultrapure water for 3 minutes.

Thereafter, the silicon wafer was placed in the heat treatment apparatus shown in FIG. 3, and heat treatment was performed at a predetermined heat treatment temperature for 180 minutes while flowing Ar having a purity of moisture of 0.02 ppb or less and O ₂ of 0.01 ppb or less.

  During the heat treatment process, as described with reference to FIGS. 4, 5, and 6, the intrusion of air and free metal into the apparatus was completely prevented. Ar was used as a gas used for preventing air from entering the atmosphere, and the gas was continuously flowed at a pressure slightly higher than the pressure in the internal tube 305.

  Specifically, the temperature of the silicon wafer is first raised from 30 ° C. to the heat treatment maintaining temperature (850 ° C. in FIG. 10) in a temperature sequence equivalent to the temperature sequence pattern shown in FIG. Retained. Thereafter, the temperature of the silicon wafer was lowered to 30 ° C. in a temperature sequence equivalent to the temperature sequence pattern shown in FIG. A sample was prepared by the above procedure.

  The results are shown in FIG. No slip line was observed in any sample. This confirmed that the surface was extremely excellent in flatness.

Heat treatment temperature (° C) Ar flow rate (slm)
Sample 1 (△) 850 14
Sample 2 (◯) 860 14
Sample 3 (◇) 875 14
Sample 4 (□) 900 14
Sample 5 (black triangle) 850 28

  As can be seen from FIG. 16, the flattening speed is higher when the heat treatment temperature is higher at the same Ar flow rate. If the heat treatment temperature is the same, the larger the Ar flow rate, the faster the flattening treatment speed.

  In the above-described embodiment, only the case where the present invention is used for a MOSFET has been described. However, the present invention is not limited to this and can be applied to all structures using a silicon wafer having a flat surface. .

Claims (7)

  A gas transport path for introducing a heat treatment atmosphere gas from the outside into the heat treatment space of the silicon wafer of the heat treatment apparatus has a double space structure separated at the joint with the heat treatment apparatus, The space communicates with the heat treatment space, the outer space does not communicate with the heat treatment space, and the transported gas is exhausted to the outside. During the heat treatment process of the silicon wafer, the heat treatment atmosphere gas is introduced into the inner space. A method of planarizing a surface of an atomic order of a silicon wafer, characterized by flowing the heat treatment atmosphere gas or a gas equivalent to the heat treatment atmosphere gas into the outer space   In an atomic order planarization surface treatment method for silicon wafers by surface heat treatment, the purity of water content 0.2 vol.ppb or less and oxygen content 0.1 vol.ppb or less in the heat treatment space where the silicon wafer is installed in the heat treatment apparatus An atomic order planarization surface treatment method for a silicon wafer, characterized in that the heat treatment is performed at a heat treatment temperature of 900 ° C. or lower while introducing a heat treatment atmosphere gas.   In an atomic order planarization surface treatment method for silicon wafers by surface heat treatment, the purity of water content 0.02 vol.ppb or less and oxygen content 0.01 vol.ppb or less in the heat treatment space where the silicon wafer is installed in the heat treatment apparatus An atomic order planarization surface treatment method for a silicon wafer, characterized in that the heat treatment is performed at a heat treatment temperature of 900 ° C. or lower while introducing a heat treatment atmosphere gas.   2. The heat treatment temperature of 900 according to claim 1, further introducing a heat treatment atmosphere gas having a water content of 0.2 vol. Ppb or less and an oxygen content of 0.1 vol. Ppb or less into the heat treatment space in which the silicon wafer is installed. An atomic order planarization surface treatment method for a silicon wafer, characterized by performing a heat treatment at a temperature of ℃ or less. An internal tube that defines a heat treatment space on the inner side, has a double structure of an external tube, a heater provided outside the external tube, and is provided in the heat treatment space to introduce and discharge an inert gas. And a wafer setting table disposed inside the inner tube,
The outer tube comprises a gas flow passage defined within the double structure;
The portion of the inner tube that introduces and discharges the inert gas includes a flange for introducing and discharging the inert gas, and a pipe that guides the inert gas inside the flange for introducing and discharging the inert gas. A heat treatment apparatus characterized by comprising:   6. The heat treatment apparatus according to claim 5, wherein an inert gas is caused to flow through the gas flow path of the outer tube. The inner tube is further attached via an O-ring, and an inert gas is supplied to the O-ring from the outside of the heat treatment space. Heat treatment equipment.

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