JPWO2013031906A1 - Photoelectric conversion device and manufacturing method thereof - Google Patents

Abstract

A photoelectric conversion device in which a first electrode, a first photoelectric conversion layer, and a second electrode are stacked in this order, and the first photoelectric conversion layer is stacked in order from the first electrode side to the second electrode side. A p-type silicon-based semiconductor layer, an i-type silicon-based semiconductor layer made of a microcrystalline silicon-based semiconductor, and an n-type silicon-based semiconductor layer containing phosphorus and oxygen. The second portion where the oxygen concentration is maximized is located at the same position in the layer thickness direction as the first portion where the phosphorus concentration is maximum or at a position closer to the i-type silicon-based semiconductor layer.

Description

  The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device having an i-type silicon-based semiconductor layer made of microcrystalline silicon. The present invention also relates to a method for manufacturing a photoelectric conversion device.

  2. Description of the Related Art In recent years, attention has been focused on solar cells, which are representative of renewable energy, due to power energy sources and global warming issues. The most widespread among solar cells are those using bulk crystals such as single crystal silicon and polycrystalline silicon, but bulk crystal solar cells use a silicon substrate with a thickness of several hundred μm. Therefore, it is difficult to reduce the cost significantly. In contrast, thin-film silicon solar cells are easy to increase in area and have a merit that the material cost is low and the cost can be reduced because the film thickness is as thin as about 1/100 that of bulk crystal solar cells. . However, thin-film silicon solar cells have lower power generation efficiency than crystalline solar cells, and improvement of photoelectric conversion characteristics is an important issue.

  For the photoelectric conversion layer of the thin film silicon solar cell, an amorphous silicon solar cell using a hydrogenated amorphous silicon semiconductor as a light absorption layer and a hydrogenated microcrystalline silicon semiconductor as a light absorption layer are disclosed in, for example, Japanese Patent Application Laid-Open No. 2010-2010. And a microcrystalline silicon solar cell as shown in Japanese Patent No. 129785 (Patent Document 1). Also, in recent years, a stacked thin film silicon solar cell in which both of these are used to take advantage of the difference in band gap and spectral sensitivity characteristics has attracted particular attention in recent years. In order to increase the efficiency of stacked thin film silicon solar cells, of course, it is necessary to increase the efficiency of both amorphous silicon layers and microcrystalline silicon layers. Microcrystalline silicon solar cells are a new technology compared to amorphous silicon solar cells. In addition, since there is an advantage that light degradation does not occur, it is very important to improve the efficiency of the microcrystalline silicon solar cell.

  In Japanese Unexamined Patent Publication No. 2010-129785 (Patent Document 1), in a microcrystalline silicon solar cell, an n-type semiconductor layer is formed using a gas containing at least one element of carbon and nitrogen as a source gas. It is described that the fill factor is improved.

JP 2010-129785 A

  However, the characteristics of the microcrystalline silicon solar cell are generally as follows. The open circuit voltage (Voc) is as low as 0.1 to 0.2 V as compared with the polycrystalline silicon solar cell and the single crystal silicon solar cell. Jsc) and form factor (FF) are generally low, and even if the n-type semiconductor layer is improved as described above, it is difficult to sufficiently improve the photoelectric conversion characteristics.

  An object of the present invention is to provide a photoelectric conversion device having an i-type silicon-based semiconductor layer made of a microcrystalline silicon-based semiconductor, having excellent photoelectric conversion characteristics, and a method for manufacturing the photoelectric conversion device.

  The present invention is a photoelectric conversion device in which a first electrode, a first photoelectric conversion layer, and a second electrode are stacked in this order, and the first photoelectric conversion layer is directed from the first electrode side to the second electrode side. A p-type silicon-based semiconductor layer, an i-type silicon-based semiconductor layer made of a microcrystalline silicon-based semiconductor, and an n-type silicon-based semiconductor layer containing phosphorus and oxygen. The system semiconductor layer has a second site where the oxygen concentration is maximized at a position where the position in the layer thickness direction is the same as the first site where the phosphorus concentration is maximum or a position closer to the i-type silicon semiconductor layer. The term “microcrystal” also includes the case of having an amorphous part.

The second portion preferably has a phosphorus concentration of 1 × 10 ¹⁹ (atoms / cm ³ ) or more. The second portion preferably has an oxygen concentration of 1 × 10 ²⁰ (atoms / cm ³ ) or more.

  In one embodiment of the present invention, the n-type amorphous silicon-based semiconductor layer has an n-type amorphous silicon oxide layer including a second portion, and the n-type amorphous silicon oxide layer is preferably Has a thickness of 10 nm or less.

  The n-type amorphous silicon oxide layer preferably has a configuration in which the band gap continuously decreases in the layer thickness direction from the first electrode side toward the second electrode side.

  The i-type silicon-based semiconductor layer has a crystallization rate of preferably 2 or more and 15 or less. Here, the “crystallization rate” refers to the ratio (Ic / Ia) of the peak intensity (Ic) of the crystalline silicon phase to the peak intensity (Ia) of the amorphous silicon phase, which is obtained from the Raman spectroscopic measurement spectrum.

  In one embodiment of the present invention, a second photoelectric conversion layer is further provided between the first electrode and the second electrode.

  In one embodiment of the present invention, a translucent insulating substrate is provided, and the first electrode, the first photoelectric conversion layer, and the second electrode are stacked in this order on the translucent substrate. In another embodiment of the present invention, a non-translucent insulating substrate is provided, and the second electrode, the first photoelectric conversion layer, and the first electrode are stacked in this order on the non-transparent insulating substrate. Yes.

  Moreover, this invention is a manufacturing method of the said photoelectric conversion apparatus, Comprising: It has the process of supplying the gas containing an oxygen atom and forming the said n-type silicon type semiconductor layer.

  In one embodiment of the manufacturing method, the step of forming the n-type silicon-based semiconductor layer is a step of forming an n-type silicon-based semiconductor layer on the i-type silicon-based semiconductor layer, and a unit time of a gas containing oxygen atoms A step of continuously reducing the amount of supply per unit.

In the above manufacturing method, a gas containing at least one of CO ₂ gas, O ₂ gas, and N ₂ O gas can be used as the gas containing oxygen atoms.

  According to the present invention, a photoelectric conversion device including an i-type silicon-based semiconductor layer made of a microcrystalline silicon semiconductor and having excellent photoelectric conversion characteristics can be provided.

It is sectional drawing which shows schematically the structure of the photoelectric conversion apparatus of 1st Embodiment. It is sectional drawing which shows typically a part of structure of the plasma CVD apparatus used by 1st Embodiment. It is sectional drawing which shows schematically the structure of the photoelectric conversion apparatus of 2nd Embodiment. It is a figure which shows the relationship between the distance of the film thickness direction in the photoelectric conversion apparatus of Example 3, and atomic concentration. It is a figure which shows the relationship between the distance of the film thickness direction in a photoelectric conversion apparatus of the comparative example 1, and atomic concentration. In Examples 1-3 and Comparative Example 1, it is a figure which shows the relationship between an open circuit voltage and the film thickness of an n-type amorphous silicon oxide layer. In Examples 1-3 and Comparative Example 1, it is a figure which shows the relationship between a fill factor and the film thickness of an amorphous silicon oxide layer. In Examples 1-3 and Example 4, 5, it is a figure which shows the relationship between an open circuit voltage and the film thickness of an n-type amorphous silicon oxide layer. In Examples 1-3 and Example 4, 5, it is a figure which shows the relationship between a fill factor and the film thickness of an amorphous silicon oxide layer.

  The photoelectric conversion device of the present invention is a solar cell in which a first electrode, a first photoelectric conversion layer, and a second electrode are laminated in this order. The first photoelectric conversion layer includes a p-type silicon-based semiconductor layer, an i-type silicon-based semiconductor layer made of a microcrystalline silicon-based semiconductor, phosphorus, and phosphorus, which are sequentially stacked from the first electrode side to the second electrode side. And an n-type silicon-based semiconductor layer containing oxygen. The n-type silicon-based semiconductor layer has a second portion where the oxygen concentration is maximized at the same position in the layer thickness direction as the first portion where the phosphorus concentration is maximum or at a position closer to the i-type silicon-based semiconductor layer. Hereinafter, the photoelectric conversion device of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
(Configuration of photoelectric conversion device)
FIG. 1 is a cross-sectional view schematically showing the configuration of the photoelectric conversion apparatus according to the first embodiment. As illustrated in FIG. 1, the photoelectric conversion device 100 according to the first embodiment includes a substrate 11, a first electrode 12, a first photoelectric conversion layer 10, and a second electrode 16 that are stacked in this order. The photoelectric conversion device 100 is a super straight type in which light is incident from the substrate 11 side.

The substrate 11 is a translucent insulating substrate made of a translucent material. The substrate 11 is preferably made of, for example, a resin such as glass or polyimide, and has heat resistance and translucency in the semiconductor layer formation step by the plasma CVD method. The 1st electrode 12 is comprised with the material which has translucency. The first electrode 12 can be made of, for example, SnO ₂ , indium tin oxide (ITO), or the like. The thickness and shape of the substrate 11 and the first electrode 12 are not particularly limited.

  The first photoelectric conversion layer 10 includes a p-type silicon-based semiconductor layer 13 made of a microcrystalline silicon-based semiconductor, an i-type silicon-based semiconductor layer 14 made of a microcrystalline silicon-based semiconductor, and an n-type silicon-based semiconductor layer 15 stacked in order. And has a pin junction structure from the substrate 11 side. The n-type silicon-based semiconductor layer 15 is formed by sequentially stacking an n-type amorphous silicon oxide layer 15a, an n-type amorphous silicon layer 15b, and an n-type microcrystalline silicon layer 15c. The n-type silicon-based semiconductor layer 15 contains phosphorus and oxygen, and the oxygen concentration is maximized at a position where the position in the layer thickness direction is the same as that of the first portion where the phosphorus concentration is maximum or closer to the i-type silicon-based semiconductor layer 14 A second part. This second part is included in the n-type amorphous silicon oxide layer 15a.

The 2nd electrode 16 consists of the transparent conductive film 16a and the metal film 16b which were laminated | stacked in order from the side close | similar to the 1st photoelectric converting layer 10. FIG. The transparent conductive film 16a can be made of, for example, SnO ₂ , ITO, ZnO or the like. The metal film 16b can be made of, for example, silver, aluminum, titanium, palladium, or the like. The second electrode 16 may be configured by only the metal film 16b.

  In the photoelectric conversion device 100, by having the n-type amorphous silicon oxide layer 15a including the second portion where the oxygen concentration is maximized, a high open-circuit voltage and a fill factor can be obtained, and an excellent photoelectric conversion layer efficiency can be obtained. It is done. This is because the n-type amorphous silicon oxide layer 15a widens the band gap on the n layer side of the i / n interface, reduces the diffusion of holes to the n layer side, and improves the reverse saturation current. It is considered that the open circuit voltage and the fill factor are improved. In addition, it is considered that electrons are tunnel transported through a level close to the conduction band caused by oxygen contained in the n-type amorphous silicon oxide layer 15a, thereby contributing to improvement of the open circuit voltage and the fill factor. .

  The film thickness of the n-type amorphous silicon oxide layer 15a is preferably 10 nm or less, and more preferably 6 nm or less. When the film thickness of the n-type amorphous silicon oxide layer 15a exceeds 10 nm, productivity is lowered. In addition, it is preferable that the light incident side (first electrode 12 side) has the largest band gap and the back electrode side (second electrode 16 side) has the graded structure having the smallest band gap. With such a configuration, the open circuit voltage and the fill factor can be further improved, and more excellent photoelectric conversion efficiency can be obtained. In the case of a graded structure, the band gap on the light incident side is preferably 1.85 eV or more. When the band gap on the light incident side is 1.85 eV or more, the diffusion of holes to the n layer side can be sufficiently reduced.

In the n-type silicon-based semiconductor layer 15, the phosphorus concentration at the second portion where the oxygen concentration becomes maximum is preferably 1 × 10 ¹⁹ (atoms / cm ³ ) or more. When the phosphorus concentration is 1 × 10 ¹⁹ (atoms / cm ³ ) or more, sufficient conductivity can be obtained. In the n-type silicon-based semiconductor layer 15, the oxygen concentration at the second portion where the oxygen concentration is maximized is preferably 1 × 10 ²⁰ (atoms / cm ³ ) or more. When the oxygen concentration is 1 × 10 ²⁰ (atoms / cm ³ ) or more, diffusion of holes into the n layer can be sufficiently reduced.

  The i-type silicon-based semiconductor layer 14 preferably has a crystallization rate of 2 or more and 15 or less. This is because when the crystallization rate is less than 2, a sufficient short-circuit current value cannot be obtained and the photoelectric conversion efficiency may be lowered, and photodegradation may occur due to the large amount of amorphous components. Further, when the crystallization rate is larger than 15, a sufficient open-circuit voltage value cannot be obtained, and the photoelectric conversion efficiency may be lowered. The i-type silicon-based semiconductor layer 14 preferably has a thickness of 500 nm to 5000 nm.

  The p-type silicon-based semiconductor layer 13 preferably has a thickness of 5 nm to 50 nm. When the thickness of the p-type silicon-based semiconductor layer 13 is less than 5 nm, the first electrode 12 may be partially exposed, and a normal semiconductor pin junction is not formed, so that the characteristics as a photoelectric conversion device are significantly deteriorated. Because there is a case to do. On the other hand, if the thickness of the p-type silicon-based semiconductor layer 13 exceeds 50 nm, the light absorption amount of the p-type silicon-based semiconductor layer 13 becomes excessive, and the amount of light reaching the i-type silicon-based semiconductor layer 14 is reduced. It is because the short circuit current as a conversion layer apparatus may fall.

(Plasma CVD equipment)
FIG. 2 is a cross-sectional view schematically showing a part of the configuration of a plasma CVD apparatus used for manufacturing the photoelectric conversion apparatus of the present embodiment. The plasma CVD apparatus shown in FIG. 2 is a so-called capacitively coupled plasma CVD apparatus, in which the cathode electrode 3 in the reaction chamber 4 and the high-frequency power source 6 are connected via a matching circuit 5 to fix the cathode electrode 3 and the substrate 11. The plasma is generated in the region between the anode electrode 2 and the anode electrode 2. The substrate 11 is preheated to a desired temperature by the heater 1 before film formation. Note that the plasma CVD apparatus used in this embodiment is a multi-chamber plasma CVD apparatus, and a plurality of reaction chambers are provided, for example, in a straight line.

(Manufacturing method of photoelectric conversion device)
In the manufacturing method of the present embodiment, the following steps are performed using the plasma CVD apparatus shown in FIG. First, the p-type silicon-based semiconductor layer 13 is formed on the substrate 11 provided with the first electrode 12. The reaction chamber 4 is evacuated to 1 × 10 ⁻⁶ Torr, and the temperature of the substrate 11 is controlled to 250 ° C. or lower. Then, a mixed gas is introduced into the reaction chamber 4 by a flow rate controller (not shown), and the pressure in the reaction chamber 4 is kept constant by a conduction valve (not shown) provided in the exhaust system.

The pressure in the reaction chamber 4 is, for example, not less than 0.5 Torr and not more than 5 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and diborane gas is used. In the mixed gas, the flow rate of the hydrogen gas with respect to the silane gas is desirably 20 times or more and 200 times or less. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. A p-type silicon semiconductor layer 13 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3 is, for example, 0.05 W / cm ² or more and 0.5 W / cm ² or less.

Next, the i-type silicon-based semiconductor layer 14 is formed. The pressure in the reaction chamber 4 is, for example, 2 Torr or more and 20 Torr or less. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas and hydrogen gas is used. In the mixed gas, the flow rate of the hydrogen gas with respect to the silane gas is preferably 10 to 100 times. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The i-type silicon-based semiconductor layer 14 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3 is, for example, 0.05 W / cm ² or more and 0.5 W / cm ² or less.

Next, an n-type amorphous silicon oxide 15a is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, phosphine gas, and carbon dioxide gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. An n-type amorphous silicon oxide layer 15a is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.2 W / cm ² or less. When the n-type amorphous silicon oxide 15a has a graded structure, the supply amount of carbon dioxide gas per unit time is continuously reduced. The oxygen source in the n-type amorphous silicon oxide 15a is not limited to the carbon dioxide gas, and a gas containing oxygen atoms such as O ₂ gas and N ₂ O gas can be used. When carbon dioxide gas is used as an oxygen source, a film with good film quality can be formed.

Next, an n-type amorphous silicon layer 15b is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and phosphine gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The film thickness is 1 nm or more and 20 nm or less. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.2 W / cm ² or less. The n-type amorphous silicon oxide layer 15a and the n-type amorphous silicon layer 15b may be formed continuously.

Next, an n-type microcrystalline silicon layer 15c is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.5 Torr and not more than 5 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and phosphine gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The n-type microcrystalline silicon layer 15c is formed to have a thickness of 5 nm to 50 nm. The power density per unit area of the cathode electrode 3 is, for example, 0.05 W / cm ² or more and 0.5 W / cm ² or less. As described above, the photoelectric conversion layer 10 is formed.

  Next, the second electrode 16 is formed on the photoelectric conversion layer 10. The second electrode 16 includes a transparent conductive film 16a and a metal film 16b, which are sequentially formed by a method such as CVD, sputtering, or vapor deposition.

(Modification)
The photoelectric conversion device 100 according to the first embodiment has a superstrate type configuration, but can also be applied to a substrate type configuration. In the substrate type configuration, the substrate 11 formed on the first electrode 12 side is formed on the second electrode 16 side in the super straight type photoelectric conversion device 100 shown in FIG. An insulating substrate is used. The configurations of the first electrode 12 and the second electrode 16 can be selected as appropriate, but the first electrode 12 on the light incident side is configured in a grid shape that does not uniformly cover the p-type silicon-based semiconductor layer 13. . Also in the substrate type photoelectric conversion device, the effect of the present invention can be obtained in the same manner as the super straight type photoelectric conversion device.

[Second Embodiment]
FIG. 3 is a cross-sectional view schematically showing the configuration of the photoelectric conversion apparatus according to the second embodiment. The photoelectric conversion device 200 of the second embodiment shown in FIG. 3 differs from the photoelectric conversion device 100 shown in FIG. 1 only in that it has a second photoelectric conversion layer 20 in addition to the first photoelectric conversion layer 10. In the photoelectric conversion device 200, the same components as those of the photoelectric conversion device 100 are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 3, the photoelectric conversion device 200 includes a second photoelectric conversion layer 20 between the first electrode 12 and the first photoelectric conversion layer 10. The second photoelectric conversion layer 20 includes a p-type silicon-based semiconductor layer 23 and an i-type silicon-based layer in order from the first electrode 12 side so that the direction of the pin junction is the same as that of the first photoelectric conversion layer 10. A semiconductor layer 24 and an n-type silicon-based semiconductor layer 25 are stacked. The n-type silicon-based semiconductor layer 25 is formed by laminating an n-type amorphous silicon layer 25a and an n-type microcrystalline silicon layer 25b in this order from the i-type silicon-based semiconductor layer 24 side. The n-type silicon semiconductor layer 25 has the same layer as the n-type amorphous silicon oxide layer 15a of the first photoelectric conversion layer 10 on the i-type silicon semiconductor layer 24 side from the n-type amorphous silicon layer 25a. It may be. In this case, the effect of improving the photoelectric conversion efficiency according to the present invention can be obtained in the second photoelectric conversion layer 20 as well as the first photoelectric conversion layer 10.

  In the photoelectric conversion device 200, light enters from the substrate 11 side. Since the second photoelectric conversion layer 20 is located closer to the light incident side than the first photoelectric conversion layer 10, only the light transmitted through the second photoelectric conversion layer 20 is incident on the first photoelectric conversion layer 10. Since the second photoelectric conversion layer 20 and the first photoelectric conversion layer 10 can be configured to receive different regions by dividing the region of the incident light spectrum, a stacked structure having a plurality of such photoelectric conversion layers. In, light can be used effectively and a high open circuit voltage can be obtained. In order to enhance such an effect, the band gap of the second photoelectric conversion layer 20 on the light incident side is preferably configured to be larger than the band gap of the first photoelectric conversion layer. In this case, among the incident light, short wavelength light is mainly absorbed by the second photoelectric conversion layer 20, long wavelength light is mainly absorbed by the first photoelectric conversion layer 10, and light in each wavelength region is effectively used. Can do.

  An intermediate layer may be formed between the first photoelectric conversion layer 10 and the second photoelectric conversion layer 20. In this case, the intermediate layer is preferably a transparent conductive film. By providing the intermediate layer, a part of the light incident on the intermediate layer from the second photoelectric conversion layer 20 is reflected by the intermediate layer, and the remaining light is transmitted through the intermediate layer to the first photoelectric conversion layer 10. Since the light enters, the amount of light incident on each photoelectric conversion layer can be controlled. As a result, the photocurrent values of the photoelectric conversion layers 10 and 20 are equalized, and the photogenerated carriers generated in the photoelectric conversion layers 10 and 20 can contribute to the short-circuit current of the stacked photoelectric conversion device without waste. As a result, the short-circuit current of the photoelectric conversion device can be increased as a result, and the photoelectric conversion efficiency can be improved. Further, when the light absorption layer of the second photoelectric conversion layer 20 is made of an amorphous silicon-based semiconductor, light degradation occurs, but by reflecting a part of incident light by the intermediate layer, the second photoelectric conversion layer 20 is reflected. Therefore, the influence of light deterioration can be reduced, and stable photoelectric conversion efficiency can be obtained.

(Modification)
In the present embodiment, a photoelectric conversion device in which two photoelectric conversion layers are stacked is shown, but a photoelectric conversion device in which two or more photoelectric conversion layers are stacked may be used. Further, in the present embodiment, the super straight type photoelectric conversion device has been described. However, the present embodiment can also be applied to a substrate type photoelectric conversion device, as in the first embodiment.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated in detail, this invention is not limited to these.

[Examples 1 to 3, Comparative Example 1]
(Configuration of photoelectric conversion device)
As Examples 1 to 3, photoelectric conversion devices having the same configuration as the photoelectric conversion device 100 of the first embodiment shown in FIG. The film thickness of the i-type silicon-based semiconductor layer 14 of Examples 1 to 3 was 1.8 μm. Examples 1 to 3 were fabricated so that only the film thicknesses of the n-type amorphous silicon oxide layer 15a and the n-type amorphous silicon layer 15b were different. Further, as Comparative Example 1, a photoelectric conversion device different from Examples 1 to 3 was manufactured only in that the n-type amorphous silicon oxide layer 15a was not formed and the film thickness of the n-type amorphous silicon layer 15b was different.

(Manufacture of photoelectric conversion devices)
According to the manufacturing method of the first embodiment, a glass substrate 11 having an SnO ₂ film as a first electrode 12 (Asahi-VU substrate manufactured by Asahi Glass Co., Ltd.) is used, and a multi-chamber plasma CVD apparatus is used. 1 photoelectric conversion layer 10 was formed.

First, the p-type silicon-based semiconductor layer 13 was formed as follows. The inside of the first reaction chamber 4 was evacuated to 1 × 10 ⁻⁶ Torr, and the temperature of the substrate 11 was set to 200 ° C. The mixed gas was introduced into the reaction chamber 4 by a flow rate controller, and the pressure in the reaction chamber 4 was kept constant by a conduction valve provided in the exhaust system. The pressure in the reaction chamber 4 was 1.4 Torr. Silane gas, hydrogen gas, and diborane gas were used as the mixed gas, and the flow rate of the hydrogen gas relative to the silane gas was 105 times. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The power density per unit area of the cathode electrode 3 was 0.2 W / cm ² . The film thickness of the p-type silicon-based semiconductor layer 13 was 30 nm.

Next, the i-type silicon-based semiconductor layer 14 was formed as follows. The pressure in the second reaction chamber 4 was 7.5 Torr. Silane gas and hydrogen gas were used as the mixed gas, and the flow rate of the hydrogen gas relative to the silane gas was 18 times. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The power density per unit area of the cathode electrode 3 was 0.15 W / cm ² . The film thickness was 1800 nm.

Next, an n-type amorphous silicon oxide 15a was formed as follows. The pressure in the third reaction chamber 4 was 0.22 Torr. As the mixed gas, a mixed gas containing silane gas, hydrogen gas, phosphine gas, and carbon dioxide gas was used. After introducing the mixed gas and stabilizing the pressure in the reaction chamber 4, AC power of 13.56 MHz was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . In addition, after the plasma is generated, the mixed gas is supplied so that the supply amount of carbon dioxide gas per unit time becomes 1/3 of the supply amount of silane gas per unit time, and then the supply amount of carbon dioxide gas per unit time Thus, a graded structure having the largest band gap on the light incident side and the smallest band gap on the back electrode (second electrode 16) side was formed. At this time, the band gap (maximum band gap) on the light incident side was 1.89 eV, and the band gap (minimum band gap) on the back electrode side was 1.80 eV.

Here, the film thickness of the n-type amorphous silicon oxide layer 15a was prepared in three types of 1 nm, 2 nm, and 5 nm, and Examples 1 to 3 were used respectively. Next, an n-type amorphous silicon layer 15b was formed. The n-type amorphous silicon oxide layer 15a and the n-type amorphous silicon layer 15b were continuously formed in the same reaction chamber. The pressure in the reaction chamber 4 was 0.22 Torr. As a mixed gas, a mixed gas containing silane gas, hydrogen gas, and phosphine gas was used. Carbon dioxide gas was not used as a raw material gas. The cathode electrode 3 was supplied with 13.56 MHz AC power. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . Here, the thickness of the n-type amorphous silicon layer 15b was set to 9 nm, 8 nm, and 5 nm, respectively, with respect to Examples 1 to 3.

Next, an n-type microcrystalline silicon layer 15c was formed. The pressure in the third reaction chamber 4 was 1.8 Torr. As a mixed gas, a mixed gas containing silane gas, hydrogen gas, and phosphine gas was used. Carbon dioxide gas was not used as a raw material gas. After introducing the mixed gas and stabilizing the pressure in the reaction chamber 4, AC power of 13.56 MHz was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The film thickness was 25 nm. The power density per unit area of the cathode electrode 3 was 0.25 W / cm ² .

  Next, the second electrode 16 was formed as follows. The second electrode 16 was composed of a transparent conductive film 16a and a metal film 16b, which were sequentially formed. A 80 nm ZnO film was formed as the transparent conductive film 16a by magnetron sputtering, and a 120 nm silver layer was stacked as the metal film 16b by magnetron sputtering. Thus, the super straight type photoelectric conversion apparatus 100 of Examples 1-3 was produced.

  The photoelectric conversion device of Comparative Example 1 was produced in the same manner as in Examples 1 to 3 except that the n-type amorphous silicon oxide layer 15a was not provided and the n-type amorphous silicon layer 15b was 10 nm.

(Measurement of phosphorus concentration and oxygen concentration)
About the photoelectric conversion apparatus of Example 3 and Comparative Example 1, after etching the 2nd electrode 16 with a chemical | medical solution, the phosphorus concentration and oxygen concentration of the film thickness direction were measured by secondary ion mass spectrometry (SIMS). 4 shows the measurement results of Example 3, and FIG. 5 shows the measurement results of Comparative Example 1. 4 and 5, the horizontal axis represents the distance (depth) in the film thickness direction, and the vertical axis represents the atomic concentration. In this measurement, the acceleration voltage of the primary ion beam was 5.0 kV, and the detection area was 60 × 60 μm ² . The primary ion beam was incident from the back electrode (second electrode) side of the n-type microcrystalline silicon layer 15c. 4 and 5, the depth of 0 nm is the position where the n-type microcrystalline silicon layer 15 c is in contact with the back electrode (second electrode 16), and the depth value is from the position of the depth of 0 nm to the substrate 11. This represents the distance in the film thickness direction toward the side, and the closer to the substrate 11 (light incident side), the greater the depth value.

  As can be seen from FIGS. 4 and 5, in both Example 3 and Comparative Example 1, the oxygen concentration tends to increase as it progresses toward the back electrode (second electrode 16). This is understood to be due to the indentation of oxygen from the surface oxide film on the back surface side. Further, the surface of the Asahi-VU substrate manufactured by Asahi Glass Co., Ltd. used as the substrate 11 on the side where the first electrode 12 was provided had a textured structure, and its roughness was about 50 to 200 nm. Even when the first photoelectric conversion layer 10 is formed on the substrate 11, it is understood that the roughness of 50 to 200 nm still remains on the surface. Therefore, since the detection region in the SIMS measurement includes a plurality of texture particles, it is understood that the peaks shown in FIGS. 4 and 5 are measured as broader signals than actual.

In FIG. 4, the oxygen concentration has a maximum value near a depth of 30 nm (second region P2). In Example 3 shown in FIG. 4, since the n-type amorphous silicon oxide layer 15a is formed at 5 nm, the n-type amorphous silicon layer 15b is formed at 5 nm, and the n-type microcrystalline silicon layer 15c is formed at 25 nm, the depth is 30 nm. The neighborhood just corresponds to the position of the n-type amorphous silicon oxide 15a. Therefore, in Example 3, it can be considered that the 2nd site | part P2 from which oxygen concentration takes the maximum value is contained in the n-type amorphous silicon oxide layer 15a. It can be seen that the second portion P2 has a depth value larger than that of the first portion P1 where the phosphorus concentration is maximum, and thus is closer to the i-type silicon-based semiconductor layer 14. The maximum value of the oxygen concentration in the second site P2 was 6.1 × 10 ²⁰ (atoms / cm ³ ), and the phosphorus concentration was 2.1 × 10 ²⁰ (atoms / cm ³ ).

  In Examples 1 and 2, since the n-type amorphous silicon oxide layer 15a was formed in the same manner as in Example 3, the n-type amorphous silicon oxide layer 15a was formed in the same manner as in Example 3. The second portion where the oxygen concentration is maximized is included, and the second portion can be regarded as being closer to the i-type silicon-based semiconductor layer 14 than the first portion where the phosphorus concentration is maximum.

  In FIG. 5, it can be seen that the oxygen concentration does not take the maximum value, and the oxygen concentration monotonously decreases from the depth of 0 nm to the depth of 150 nm. It is understood that the higher the oxygen concentration is measured at the position closer to the depth of 0 nm, the influence of the surface oxide film on the second electrode 16 side.

(Evaluation of electrical characteristics)
The electrical characteristics of Examples 1 to 3 and Comparative Example 1 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 1 shows the measurement results. FIG. 6 is a diagram showing the relationship between the open circuit voltage (Voc) and the film thickness of the n-type amorphous silicon oxide layer 15a. 7 is a diagram showing the relationship between the fill factor (FF) and the film thickness of the n-type amorphous silicon oxide layer 15a.

  As shown in Table 1, in Examples 1 to 3 having an n-type amorphous silicon oxide layer on the n-layer side of the i / n interface, the n-type amorphous silicon oxide layer on the n-layer side of the i / n interface Both the open-circuit voltage and the fill factor were improved as compared with Comparative Example 1 that did not have the. That is, it can be seen that both the open-circuit voltage and the fill factor are improved by the n-type amorphous silicon oxide layer 15a including the second portion where the oxygen concentration has the maximum value.

[Examples 4 and 5]
(Configuration, manufacturing)
At the time of forming the n-type amorphous silicon oxide layer 15a, the supply amount of carbon dioxide gas, which is an oxygen supply source, is not changed, and the n-type amorphous silicon oxide layer 15a has no graded structure and n Examples 4 and 5 are photoelectric conversion devices manufactured in the same manner as in Examples 1 to 3, except that the thickness of the n-type amorphous silicon oxide layer 15a and the thickness of the n-type amorphous silicon layer 15b were determined. It was. The thickness of the n-type amorphous silicon oxide layer 15a was set to 1 nm and 2 nm in Examples 4 and 5, respectively.

(Evaluation of electrical characteristics)
The electrical characteristics of Examples 4 and 5 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 2 shows the measurement results. In Table 2, the measurement results of Examples 1 to 3 are also shown. FIG. 8 shows the relationship between the open circuit voltage (Voc) and the film thickness of the n-type amorphous silicon oxide layer 15a for the photoelectric conversion devices of Examples 1 to 3 having a graded structure and Examples 4 and 5 having no graded structure. It is a figure which shows a relationship. FIG. 9 is a diagram showing the relationship between the fill factor (FF) and the film thickness of the n-type amorphous silicon oxide layer 15a for the photoelectric conversion devices of Examples 1 to 3 and Examples 4 and 5. .

  8 and 9, the photoelectric conversion devices of Examples 1 to 3 in which the n-type amorphous silicon oxide layer 15a has a graded structure even if the n-type amorphous silicon oxide layer 15a has the same film thickness. However, from Examples 4 and 5 in which the n-type amorphous silicon oxide layer 15a does not have a graded structure, it was found that both the open circuit voltage and the fill factor were higher.

[Example 6]
(Configuration, manufacturing)
A photoelectric conversion device manufactured in the same manner as in Example 2 except that the n-type amorphous silicon oxide layer 15a has a graded structure with a maximum band gap of 1.97 eV and a minimum band gap of 1.80 eV. It was. In Example 6, as in Example 3, the n-type amorphous silicon oxide layer 15a includes the second region where the oxygen concentration is maximized, and the second region has the maximum phosphorus concentration. It can be considered that the position is closer to the i-type silicon-based semiconductor layer 14 than the part.

(Evaluation of electrical characteristics)
The electrical characteristics of Example 6 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 3 shows the measurement results. In Table 3, the measurement results of Example 2 and Comparative Example 1 are also shown.

  From the results shown in Table 3, both the Example 2 in which the maximum band gap of the n-type amorphous silicon oxide layer 15a is 1.89 eV and the Example 6 in which it is 1.97 eV have an open circuit voltage and a fill factor that are higher than those in Comparative Example 1. It can be seen that it has improved.

[Comparative Example 2]
A photoelectric conversion device manufactured in the same manner as in Example 2 except that an n-type amorphous silicon carbide layer was provided instead of the n-type amorphous silicon oxide layer 15a was used as Comparative Example 2. In Comparative Example 2, since the CO ₂ gas serving as the oxygen source was not used during film formation, and CH ₄ gas was used instead, there was a region where the oxygen concentration was maximized in the n-type silicon-based semiconductor layer 15. Can be considered not included.

The electrical characteristics of Comparative Example 2 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 4 shows the measurement results. In Table 4, the measurement results of Example 2 and Comparative Example 1 are also shown.

  From the results shown in Table 4, in Comparative Example 2 in which the amorphous silicon carbide layer was provided on the n layer side of the i / n interface, the effect of improving the open-circuit voltage and the fill factor compared to Comparative Example 1 was not obtained. It was.

[Example 7, Comparative Example 3]
(Configuration of photoelectric conversion device)
As Example 7, a photoelectric conversion device having the same configuration as that of the photoelectric conversion device 200 of the second embodiment illustrated in FIG. 3 was produced. Further, as Comparative Example 3, a photoelectric conversion device different from Example 7 was manufactured only in that the n-type amorphous silicon oxide layer 15a was not formed and the film thickness of the n-type amorphous silicon layer 15b was different.

(Manufacture of photoelectric conversion devices)
According to the manufacturing method of the second embodiment, a glass substrate 11 having an SnO ₂ film as the first electrode 12 (Asahi-VU substrate manufactured by Asahi Glass Co., Ltd.) is used to perform the first process. Two photoelectric conversion layers 20 were formed.

  In forming the second photoelectric conversion layer 20, the p-type silicon-based semiconductor layer 23, the i-type silicon-based semiconductor layer 24, and the n-type silicon-based semiconductor layer 25 were deposited in this order. Further, the first photoelectric conversion layer 10 was deposited in the order of a p-type silicon-based semiconductor layer 13, an i-type silicon-based semiconductor layer 14, and an n-type silicon-based semiconductor layer 15 under the conditions described later. Thereafter, a superconducting photoelectric conversion device 200 was obtained by forming a 80 nm thick zinc oxide layer as the transparent conductive film 16a and depositing a 120 nm thick silver layer as the metal film 16b by magnetron sputtering.

In the first photoelectric conversion layer 20, the p-type silicon-based semiconductor layer 23 is made of p-type amorphous silicon carbide, and SiH ₄ , H ₂ , CH ₄ , and B ₂ H ₆ are used as source gases. The film thickness was 8 nm. The i-type silicon-based semiconductor layer 24 is made of amorphous silicon, and SiH ₄ and H ₂ are used as source gases. The film thickness was 220 nm. In forming the n-type amorphous silicon-based semiconductor layer 25a, SiH ₄ , H ₂ , and PH ₃ were used as source gases. The film thickness was 10 nm. In forming the n-type microcrystalline silicon-based semiconductor layer 25b, SiH ₄ , H ₂ , and PH ₃ were used as source gases. The film thickness was 25 nm.

  The configuration and film forming conditions of the first photoelectric conversion layer 10 were the same as those in Example 2. Therefore, the n-type amorphous silicon oxide layer 15a has a graded structure, and its film thickness is 2 nm.

  Comparative Example 3 is a super straight type photoelectric conversion under the same conditions as in Example 7 except that the n-type amorphous silicon oxide layer 15a is not provided and the film thickness of the n-type amorphous silicon layer 15b is 10 nm. A device was made. Therefore, the configuration of the first photoelectric conversion layer 10 was the same as that of Comparative Example 1.

(Evaluation of electrical characteristics)
The electrical characteristics of Example 7 and Comparative Example 3 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 5 shows the measurement results.

  As can be seen from the results shown in Table 5, in the first photoelectric conversion layer 10, an n-type amorphous silicon oxide layer 15 a having a portion where the oxygen concentration has a maximum value is provided on the n layer side of the i / n interface. In Example 7, the open-circuit voltage and the fill factor were improved as compared with Comparative Example 3 in which this was not provided, and high photoelectric conversion efficiency was obtained.

  As described above, also in the stacked photoelectric conversion device, by providing the n-type amorphous silicon oxide layer 15a so as to be in contact with the i-type silicon-based semiconductor layer, the same as the single-layer photoelectric conversion devices of Examples 1 to 6. Further, it has been found that the open circuit voltage and the fill factor can be improved and the photoelectric conversion efficiency can be improved.

  DESCRIPTION OF SYMBOLS 1 Heater, 2 Anode electrode, 3 Cathode electrode, 4 Reaction chamber, 5 Matching circuit, 6 High frequency power supply, 10 1st photoelectric converting layer, 11 board | substrate, 12 1st electrode, 13 p-type silicon type semiconductor layer, 14 i-type silicon Semiconductor layer, 15 n-type silicon semiconductor layer, 15a n-type amorphous silicon oxide layer, 15b n-type amorphous silicon layer, 15cn n-type microcrystalline silicon layer, 16 second electrode, 16a transparent conductive film, 16b Metal film, 20 second photoelectric conversion layer, 23 p-type silicon-based semiconductor layer, 24 i-type silicon-based semiconductor layer, 25 n-type silicon-based semiconductor layer, 25a n-type amorphous silicon-based semiconductor layer, 25b n-type microcrystal Silicon-based semiconductor layer.

Claims (12)

A photoelectric conversion device in which a first electrode, a first photoelectric conversion layer, and a second electrode are laminated in this order,
The first photoelectric conversion layer includes a p-type silicon-based semiconductor layer and an i-type silicon-based semiconductor layer made of a microcrystalline silicon-based semiconductor, which are sequentially stacked from the first electrode side toward the second electrode side. An n-type silicon-based semiconductor layer containing phosphorus and oxygen,
The n-type silicon-based semiconductor layer has a second portion where the oxygen concentration is maximized at the same position in the layer thickness direction as the first portion where the phosphorus concentration is maximum or at a position closer to the i-type silicon-based semiconductor layer. , Photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein the second portion has a phosphorus concentration of 1 × 10 ¹⁹ (atoms / cm ³ ) or more. ^{3. The} photoelectric conversion device according to claim 1, wherein the second portion has an oxygen concentration of 1 × 10 ²⁰ (atoms / cm ³ ) or more.   The n-type silicon-based semiconductor layer has an n-type amorphous silicon oxide layer including the second portion, and the n-type amorphous silicon oxide layer has a thickness of 10 nm or less. 4. The photoelectric conversion device according to any one of 3.   5. The photoelectric conversion device according to claim 4, wherein a band gap of the n-type amorphous silicon oxide layer continuously decreases in a layer thickness direction from the first electrode side toward the second electrode side.   The photoelectric conversion device according to claim 1, wherein the i-type silicon-based semiconductor layer has a crystallization rate of 2 or more and 15 or less.   The photoelectric conversion device according to claim 1, further comprising a second photoelectric conversion layer between the first electrode and the second electrode. A translucent insulating substrate;
The photoelectric conversion device according to claim 1, wherein the first electrode, the first photoelectric conversion layer, and the second electrode are stacked in this order on the translucent substrate. A non-translucent insulating substrate;
The photoelectric conversion device according to claim 1, wherein the second electrode, the first photoelectric conversion layer, and the first electrode are laminated in this order on the non-translucent insulating substrate. It is a manufacturing method of the photoelectric conversion device according to claim 1,
A method for manufacturing a photoelectric conversion device, comprising a step of supplying a gas containing oxygen atoms to form the n-type silicon-based semiconductor layer.   The step of forming the n-type silicon-based semiconductor layer is a step of forming the n-type silicon-based semiconductor layer on the i-type silicon-based semiconductor layer, and a supply amount of the gas containing oxygen atoms per unit time is set. The manufacturing method of the photoelectric conversion apparatus of Claim 10 including the process to reduce continuously. Gas containing the oxygen atom, CO ₂ gas, O ₂ gas, and N ₂ containing at least one of _O gas, a method for manufacturing a photoelectric conversion device according to claim 10 or 11.

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