JPWO2012077228A1 - Lead-free solder alloy, semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

An object of the present invention is to obtain a lead-free solder alloy having high bonding reliability with respect to a power cycle in a semiconductor device operating at a high temperature and a semiconductor device using the same. As lead-free solder alloy, antimony (Sb) is 5 mass% to 15 mass%, copper (Cu) is 0.5 mass% to 3 mass%, nickel (Ni) is 0.01 mass% to 0.15 mass. The composition was optimized so that it contains 0.1% by mass or less, indium (In) 0.1% by mass or more and 5% by mass or less, and the balance is tin (Sn) and inevitable impurities.

Description

  The present invention relates to a lead-free solder alloy, a semiconductor device using the lead-free solder alloy, and a method for manufacturing the semiconductor device, and more particularly to a Sn-based lead-free solder alloy suitable for a semiconductor device that operates at a high temperature.

  In recent years, there has been an increasing demand for reliability of semiconductor devices, and in particular, there has been a demand for improvement in lifetime reliability of a junction between a semiconductor element having a large difference in thermal expansion coefficient and a circuit board. Conventionally, many semiconductor elements based on silicon (Si) or gallium arsenide (GaAs) are used, and the operating temperature is 100 ° C. to 125 ° C. Solder materials for bonding these elements to circuit boards are required to have a high melting point to support multi-step solder bonding during manufacturing, crack resistance to repeated thermal stresses associated with start / stop, and device contamination resistance. . In response to this requirement, 95Pb-5Sn (mass%) has been used for Si devices, and 80Au-20Sn (mass%) has been used for gallium arsenide devices. However, 95Pb-5Sn containing a large amount of harmful lead (Pb) has a problem from the viewpoint of reducing the environmental load, and 80Au-20Sn containing a large amount of noble metal has a problem from the viewpoint of rising noble metal and reserves. In both cases, alternative materials were strongly desired.

  On the other hand, development of devices based on silicon carbide (SiC) or gallium nitride (GaN) as a next-generation device from the viewpoint of energy saving has been actively conducted. These have an operating temperature of 175 ° C. or higher from the viewpoint of reducing loss, and are said to be 300 ° C. in the future.

  As described above, high-temperature solder alloys having high melting points and excellent heat resistance (power cycle resistance, heat cycle resistance) are required in conventional and next-generation devices. Sn-based lead-free solder alloys have been proposed as solder alloys that meet these requirements. For example, Patent Document 1 discloses excellent wettability and mechanical properties (particularly excellent ductility and little aging change at high temperature), and further, the interface reaction layer grows slowly and has excellent joint reliability. As a high temperature lead-free solder alloy, Sb is 3.0 to 10.0% by mass, Cu is 1.0% by mass or less (not including the lower limit of zero), Ni is 0.01 to 1.0% by mass, Ge Discloses an alloy composition containing 0.01 to 1.0% by mass. Patent Document 2 discloses a highly reliable Sn-based lead-free solder alloy that controls the hardness of the solder material to suppress cracking of the semiconductor element during the heat cycle and further improve the crack resistance of the solder material. An alloy composition in which Sb is 5 to 15 wt% or less, Cu is 3 to 8 wt% or less, Ni is 0.01 to 0.15 wt% or less, and In is 0.5 to 5 wt% or less is disclosed. Yes.

JP 2008-221330 A (paragraphs 0031 to 0048, FIGS. 1 to 7) International Publication Number WO2010 / 047139A1 (paragraphs 0013 to 0046, FIGS. 5 to 8)

  By the way, in the semiconductor device that operates at a high temperature, the present inventors not only have the mechanical characteristics as a material and the heat cycle resistance as a single component applied, but also the reliability as a device by the power cycle accompanied by the actual operation. The reliability test in the power cycle was carried out. As a result, in the power cycle, it was found that suppression of vertical cracks generated in the direction perpendicular to the bonding layer is important for improving the bonding reliability. However, the alloy disclosed in Patent Document 1 does not take measures for improving reliability with respect to heat cycle and power cycle. Moreover, in patent document 2, although the countermeasure for suppressing the horizontal crack produced in a horizontal direction with respect to a joining layer at the time of a heat cycle is made, the countermeasure for suppressing the generation | occurrence | production of the vertical crack in a power cycle is not made. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a lead-free solder alloy having high bonding reliability with respect to a power cycle in a semiconductor device operating at a high temperature and a semiconductor device using the same. And

  In the lead-free solder alloy according to the present invention, Sb is 5 to 15% by mass, Cu is 0.5 to 3% by mass, Ni is 0.01 to 0.15% by mass, In 0.1 mass% or more and 5 mass% or less is contained, and it consists of remainder Sn and an unavoidable impurity.

  The semiconductor device according to the present invention includes a circuit board on which a circuit pattern is formed and a semiconductor element mounted on the circuit pattern, and the lead-free lead mentioned above is bonded to the circuit pattern of the semiconductor element. It is characterized by using a solder alloy.

  In addition, a method of manufacturing a semiconductor device according to the present invention includes a step of arranging a solder material formed of the above lead-free solder alloy in a predetermined range on a circuit pattern of a circuit board constituting the semiconductor device, and the arranged solder. A step of installing a semiconductor element on the material; and a step of heating the solder material so as to melt and bonding the semiconductor element to a predetermined position of the circuit pattern.

  According to the present invention, in a semiconductor device that operates at a high temperature, not only cracking due to metallization diffusion at high temperatures but also peeling due to vertical cracks in a power cycle can be prevented. Can be obtained.

It is a figure for demonstrating the structure of the semiconductor device manufactured using the lead-free solder alloy concerning Embodiment 1 of this invention. It is a figure for demonstrating the method to manufacture a semiconductor device using the lead-free solder alloy concerning Embodiment 1 of this invention. It is a figure which shows the part of the semiconductor device for demonstrating the peeling mechanism of the junction part at the time of hold | maintaining high temperature what joined the semiconductor element using Sn type lead-free solder alloy. It is a figure which shows the part of the semiconductor device for demonstrating the peeling mechanism of the junction part when a power cycle test is performed with the semiconductor device manufactured using Sn system lead-free solder alloy. It is a figure which shows the relationship between Sb content rate and a mechanical characteristic in a lead-free solder alloy. It is a figure which shows the relationship between In content rate and the void rate at the time of joining in a lead-free solder alloy.

Embodiment 1 FIG.
FIGS. 1-6 is for demonstrating the lead-free solder alloy concerning Embodiment 1 of this invention, and the semiconductor device for electric power manufactured using it. FIG. 1 illustrates a power semiconductor device manufactured using a lead-free solder alloy solder material. Of the power semiconductor device, a semiconductor element mounted on an insulating substrate, the semiconductor element, and a ribbon FIG. 1 (a) is a top view, FIG. 1 (b) is a cross-sectional view taken along the line AA of FIG. 1 (a), and FIG. 1 (a) is a top view. FIG.1 (c) is the elements on larger scale for demonstrating the layer structure formed in the base material of the semiconductor element in FIG.1 (b). FIG. 2 shows changes for each process for explaining a method of mounting a semiconductor element on an insulating substrate using a lead-free solder alloy solder material, and corresponds to the part of FIG. FIG. 3 is a diagram for explaining the change in the layer structure of the joint and the occurrence of peeling when a semiconductor element joined with a lead-free solder alloy solder material is held at a high temperature, and FIG. FIG. 3 (b) shows a state in the middle stage when held at a high temperature after bonding, and FIG. 3 (c) shows a state when peeling tends to occur due to holding at a high temperature after bonding. FIG. 4 is a diagram for explaining a mechanism of occurrence of peeling when a semiconductor device manufactured by joining semiconductor elements with a lead-free solder alloy solder material is subjected to a power cycle. 5 and 6 are diagrams showing test results when the alloy composition is changed in order to determine the optimum range of the composition of the lead-free solder alloy.

  Here, before describing the composition of the lead-free solder alloy, the configuration of the semiconductor device to which the lead-free solder alloy according to the first embodiment of the present invention (strictly, the solder material formed from the lead-free solder alloy) is applied, and The peeling mechanism that could be found in the power cycle test based on the configuration will be described.

<Configuration of semiconductor device>
As shown in FIG. 1, the power semiconductor device 10 includes a circuit pattern 4Ea bonded to a circuit surface 4f of an insulating ceramic plate 4 made of a ceramic material such as aluminum nitride, silicon nitride, or alumina by a brazing material (not shown). 4Eb (4E collectively including 4Er described later) is arranged. The circuit pattern 4E is made of a conductive material such as copper or aluminum or an alloy material containing them as a main component. Furthermore, the surface of the circuit pattern 4E is formed with a plating film such as nickel in consideration of oxidation prevention and wettability of the solder material. Hereinafter, the entire insulating ceramic plate having the circuit pattern 4E on both sides will be referred to as a circuit board 4. Although not shown, a heat sink may be formed on the surface of the circuit board 4 opposite to the circuit surface 4f (the surface on which the circuit pattern 4Er is formed in the drawing).

  In FIG. 1, a semiconductor element (chip) 2 is joined via solder formed of a lead-free solder alloy on the circuit pattern 4Ea (the solder before joining is distinguished from the solder material 3M and the solder after joining from the solder layer 3). Has been. The semiconductor element 2 may be a general element based on a silicon wafer. In the present invention, the semiconductor element 2 has a wider band gap than silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond. It is intended to be applied to a band gap semiconductor material, and is particularly applied to a semiconductor element using silicon carbide. Device types include switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors), or rectifying elements such as diodes. In the case of a MOSFET, a drain electrode is formed on the surface of the semiconductor element 2 on the circuit pattern 4Ea side. A gate electrode and a source electrode are formed on the surface opposite to the drain electrode (upper side in the figure), but a large current flows on the upper surface to simplify the explanation. Only the source electrode will be described.

  One end of a wiring member 5 such as a ribbon of aluminum (Al) or copper (Cu) or a wire is joined to the upper surface of the semiconductor element 2, and the other end is joined to the electrode 4Eb. Thereby, a power feeding path from the semiconductor element 2 to an external circuit (not shown) or the like is formed. In FIG. 1, only one ribbon is shown as the wiring member 5 for simplification of description, but a plurality of them may be arranged side by side in order to ensure current capacity.

Thus, in order to join the upper surface and the lower surface of the semiconductor element 2 to another metal material, the semiconductor element 2 has a plurality of coating layers on both sides of the semiconductor substrate 2B as shown in FIG. Is formed. For example, the semiconductor element 2 has a substrate-side ohmic layer 2L _r1 and a Ni plating layer on the surface side (lower side in the figure) that is bonded to the circuit board 4 by the solder material 3M with respect to the silicon carbide material base material 2B. A substrate side metallization layer 2L _r2 and an alloy layer 2L _r3 are formed. Further, a wiring member side ohmic layer 2L _f1 and a wiring member side metallization layer 2L _f2 are formed on the surface side (lower side in the figure) to which the ribbon 5 is connected. The substrate-side ohmic layer 2L _r1 is for making the junction between the base material 2B, which is a semiconductor material, and a metal an ohmic junction, and is formed so as to be in contact with the base material 2B. The substrate side metallized layer 2L _r2 is for obtaining a good bond between the substrate side ohmic layer 2L _r1 and the solder layer 3, and is formed so as to be in contact with the substrate side ohmic layer 2L _r1 . As will be described later, the alloy layer 2L _r3 includes the solder layer 3 (solder bonding layer) and the metallized layer 2L _r2 generated when the semiconductor element 2 is bonded to the circuit board 4 (strictly 4Ea) with the solder material 3M. It is a layer that occurs between

The wiring member side ohmic layer 2L _f1 formed on the upper surface side of the semiconductor element 2 is for making the junction between the base material 2B, which is a semiconductor material, and a metal an ohmic junction, and is formed so as to be in contact with the base material 2B. Has been. The wiring member side metallized layer 2L _f2 is for obtaining a good bond between the wiring member side ohmic layer 2L _f1 and the solder layer 3, and is formed so as to be in contact with the wiring member side ohmic layer 2L _f1 .

As the substrate-side ohmic layer 2L _r1 , for example, Ti (titanium) having a thickness of about 100 nm is used. As the substrate side metallization layer 2L _r2 , for example, Ni having a thickness of about 500 nm is used. As alloy layer 2L _r3, for example, a Ni—Sn (tin) —Cu (copper) phase is formed from the semiconductor element 2 side, and then a mixed phase of a Cu—Sn phase and a Sn—Sb (antimony) phase is formed. Yes. As will be described later, the solder layer 3 has Sb of 5% by mass to 15% by mass, Cu of 0.5% by mass to less than 3% by mass, Ni of 0.01% by mass to 0.15% by mass, In Is a so-called lead-free solder alloy in which the balance Sn is 0.1 mass% or more and 5 mass% or less. Of course, other inevitable impurities may be included.

As the wiring member side ohmic layer 2L _f1 , for example, Ti (titanium) having a thickness of about 100 nm is used. As the wiring member side metallization layer 2L _f2 , for example, Al having a thickness of about 1000 nm is used. As the wiring member 5, for example, a ribbon having a thickness of 200 μm and a width of 2000 μm or an Al wire having a diameter of 100 μm is used and bonded by applying predetermined ultrasonic energy by an ultrasonic device or the like.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG.
For example, as shown in FIG. 2A, a substrate-side ohmic layer 2L _r1 , a substrate-side metallized layer 2L _r2 , and a wiring member-side ohmic are formed on the surface of a silicon carbide semiconductor substrate 2B having a thickness of 0.25 mm and a 7 mm square. The layer 2L _f1 and the wiring member side metallization layer 2L _f2 are sequentially stacked to form the semiconductor element 2. Next, the semiconductor element 2 is joined to the circuit board 4 (the electrode 4Ea thereof) with the solder material 3M. In this solder joining, first, solder pellets 3M to be the solder layer 3 are placed on the surface of the circuit board 4. This solder pellet 3M is made of an alloy having a composition of Sn-10Sb-2Cu-0.1Ni-1In (indium), for example, and flux 3f is applied to both surfaces thereof. Moreover, this solder pellet 3M has a dimension of 8 mm square with a thickness of 0.1 mm, for example. Then, the semiconductor element 2 is further placed on the placed solder pellet 3M. At this time, the semiconductor element 2 is placed so that the substrate-side metallized layer 2L _r2 is in contact with the solder pellet 3M.

In this manner, the stack of the circuit board 4, the solder pellet 3M, and the semiconductor element 2 is placed on a hot plate set at a temperature of 300 ° C. with the circuit board 4 down, and heated for 2 minutes. . As a result, the solder pellets 3M are melted to form a molten solder layer 3. Then, the components in the substrate side metallized layer 2L _r2 and the components in the solder layer 3 diffuse to each other, and as shown in FIG. 2B, between the substrate side metallized layer 2L _r2 and the solder layer 3 Alloy layer 2L _r3 is formed. Upon completion of heating, the molten solder layer 3 is cooled and solidified. Thereafter, the flux residue is removed, and an Al ribbon having a thickness of 200 μm is bonded to the wiring member side metallization layer 2L _f2 by applying predetermined ultrasonic energy with a bonding tool (not shown). Through the above process, the semiconductor device 10 as shown in FIG. 1 is manufactured.

  In addition, “Sn-10Sb-2Cu-0.1Ni-1In (mass%)” operated above includes 10% by mass of Sb, 2% of Cu, 0.1% of Ni, and 1% of In. In addition, a solder alloy in which the balance is Sn is shown, and naturally, inevitable impurities are not described. In the following description, the same notation shall mean the composition in the same mass% (denoted wt% in the figures and tables). Moreover, although the example of the solder pellet 3M was shown as a solder material, other forms, such as not only a pellet but a bar, a paste, or powder, may be sufficient.

<Peeling mechanism>
Next, peeling of two types of joints, which occurs in the semiconductor device having the above-described configuration and is an object to be overcome by the lead-free solder alloy according to the embodiment of the present invention, will be described. The first is delamination due to metallization diffusion that occurs when held at a high temperature, and the second is delamination due to longitudinal cracks in the power cycle found by the present inventors.

First, peeling that occurs between the substrate-side ohmic layer 2L _r1 and the alloy layer 2L _r3 due to metallization diffusion will be described. FIG. 3 shows the change over time of the schematic cross-sectional view in which the portion from the base material 2B side of the semiconductor element 2 to the solder layer 3 in the joint portion between the semiconductor element 2 and the circuit board 4 is expanded. 3A is a state immediately after joining, FIG. 3B is a state after joining and holding at 200 ° C. for a while, and FIG. 3C is a state after being left at 200 ° C. for a longer time. It is. As shown in the figure, when the semiconductor device is held at a high temperature of about 200 ° C., the metallized layer 2L _r2 between the alloy layer 2L _r3 and the substrate-side ohmic layer 2L _r1 gradually becomes thin, and eventually disappears to form an alloy. The layer 2L _r3 and the substrate-side ohmic layer 2L _r1 come into direct contact. At this time, the thickness of the substrate-side ohmic layer 2L _r1 hardly changes, but the alloy layer 2L _r3 grows by taking in the substrate-side metallized layer 2L _r2 and a part of the solder layer 3 by thermal diffusion and becomes thicker. Go. As shown in FIG. 3C, when the metallized layer 2L _r2 disappears and the substrate-side ohmic layer 2L _r1 and the alloy layer 2L _r3 are in direct contact with each other, between the two layers 2L _r1 and 2L _r3 Since the adhesion strength of is low, peeling _BD occurs between the substrate-side ohmic layer 2L _r1 and the alloy layer 2L _r3 even with a relatively small force.

A description will be given of peeling due to a vertical crack generated when a power cycle is performed as the second semiconductor device 1. FIG. 4 shows an example in which a power cycle of about 5 k cycles is performed by using a current supply device and a temperature control device (not shown) for 10 seconds at 40 ° C. and 10 seconds at 200 ° C., and then in the solder layer 3 (joint). This shows the state of occurrence of cracks C. In the drawing, a crack generated in the vertical (v) direction is referred to as a vertical crack Cv, and a crack generated in the horizontal (h) direction is referred to as a horizontal crack Ch. In the figure, the portion immediately below the ribbon 5 is locally heated when energized, and the solder layer 3 tends to thermally expand. However, since it is constrained by the peripheral portion having a low temperature, a compressive stress is generated inside. At this time, if there is a fragile portion such as the precipitate 3p in the structure of the solder layer 3, a vertical crack Cv is generated starting from the precipitate 3p. If the above is repeated further, the vertical crack width of the solder layer 3 increases and the crack generation area increases, and if it continues further, for example, a horizontal crack Ch is generated along a plurality of vertical cracks Cv _{1 and} Cv _2. Peels off. This horizontal crack Ch is related to the void ratio at the time of joining and the amount of the vertical crack Cv after the power cycle, but is also related to the strength and elongation of the material itself (bulk), and must be a material having a certain strength and elongation. For example, the horizontal crack Ch occurs at an early stage along the vertical crack Cv or the precipitate 3p or a void described later.

  The above-described precipitate 3p which becomes a weak part has various compositions, mainly the material constituting the solder layer 3, and among them, the Cu precipitate is particularly caused by an increase in the vertical crack Cv. I understood it. This is because the Sn-Cu eutectic alloy composition is Sn-0.7Cu, and when Cu is further added (increased), a part of Cu forms a Cu-rich phase at the bonding interface, but at the same time in the parent phase. Precipitate. The Cu-rich phase precipitated in the matrix phase aggregates and becomes coarse due to heat generated by the power cycle. Then, compared to the parent phase, the Cu rich phase is hard and difficult to be plastically deformed, and therefore vertical cracks Cv are generated based on the Cu rich phase due to the difference in plasticity and creep properties between the two. In addition, although Sb and In were also examined, when the content of Sb and In is increased, precipitates increase. In this case, since strength and elongation are improved at the same time, the vertical crack Cv is changed to the horizontal crack Ch. It was found that no fatal failure (abrupt increase in resistance at the joint) occurred.

  In addition, although the said aggregation of a precipitate generate | occur | produces also in a heat cycle, it does not reach until a clear vertical crack Cv generate | occur | produces. This is because, in the case of a power cycle, once the above-described bonding deterioration occurs, the heat dissipation of the bonding portion decreases and the amount of heat generated increases. As a result, the temperature of the joint rises and the joint deterioration further accelerates. In this way, while the set temperature is fixed in the heat cycle, the temperature is not fixed in the power cycle, and the semiconductor device undergoes thermal runaway, resulting in junction deterioration (vertical crack Cv) different from the heat cycle. This vertical crack Cv is particularly likely to occur near the high temperature portion immediately below the joint with the wiring member such as the ribbon 5 or the wire. For example, if the ribbon 5 is bonded near the center, the vertical crack Cv is generated from the central portion, There is no vertical crack Cv at the end.

Therefore, the joint deterioration during the power cycle mainly consists of peeling due to the vertical crack Cv and the accompanying horizontal crack Ch, and the evaluation is based on the resistance increase rate IR _R (the resistance after the power cycle is R _AP , If the previous resistance is R _BP , it can be performed as (R _AP −R _BP ) / R _BP ). Then, the test on, the resistance increase rate was found to increase the acceleration a resistance R _AP from around more than 10% increase in resistance Cycles resistance increase rate IR _R is 10%, or at a predetermined number of cycles rate IR _R is a whether or not the power cycle evaluation criteria product increased to 10%.

<Reason for optimization of alloy composition>
Next, as countermeasures against the above two cracks, the role of each component of the lead-free solder alloy according to the embodiment of the present invention and the concept for optimization will be described.

<Sb: 5 wt% to 15 wt%>
As a result of the parameter test 1 described later, Sb is defined as an optimal range of 5% by mass or more and 15% by mass or less, and basically adjusts tensile strength and elongation which are important physical properties as a solder material. Optimized for.
In a parameter test (results will be described later), for example, Sn-xSb-2Cu-1In-0.1Ni (mass%: x = 0 to 20), a Sn-based material containing predetermined Cu, Ni, and In is used. The tensile strength and elongation were measured by changing the Sb content in the lead-free solder alloy so as to determine the optimum range. As a result, the tensile strength increased with an increase in the Sb content, but it was found that unless the content was increased to 5% by mass or more, the tensile strength could not be increased effectively. On the other hand, it has been found that the elongation decreases dramatically when the Sb content exceeds 15% by mass.

  When the tensile strength of the solder material is high and the elongation is low, the stress is not relaxed in the solder layer 3 and, as described above, the horizontal crack Ch tends to occur along the vertical crack Cv during the power cycle. On the other hand, if the Sb content is increased too much, the amount of Sb deposited on the solder layer 3 increases, and vertical cracks Cv are likely to occur during power cycling. Therefore, it is desirable that both the tensile strength and the elongation of the solder layer 3 are high and the amount of Sb deposited is small. From this, the Sb content is 5% by mass, which is the lower limit for maintaining the tensile strength, The range defined by 15%, which is the upper limit for maintaining the elongation, was determined as the optimum range.

<Cu: 0.5 wt% to 3 wt%, and Ni: 0.01 wt% to 0.15 wt%>
Cu and Ni are defined as the optimum ranges of 0.5 mass% to 3 mass% and 0.01 mass% to 0.15 mass%, respectively, as a result of a parameter test 2 described later. As an index, the composition of Cu and Ni is used as a matrix-like parameter, a range in which ductility indicating difficulty in cracking as a solder material can be secured, and a void ratio serving as a guideline for the generation of precipitates as the starting point of the longitudinal crack Cv is predetermined. The range where the ratio is less than or equal to, the range in which cracking due to Ni diffusion during power cycling is acceptable, and the range in which the performance degradation determined by the increase in resistance due to vertical cracking due to power cycling is within the allowable value The range satisfying all of the above was set as the optimum value.

For Cu, increasing the Cu content tends to decrease ductility, increase the void fraction, and increase the residual Ni thickness. The ductility decreases because an intermetallic compound phase such as Cu ₆ Sn ₅ precipitates at the grain boundaries of Sn, which occupies most due to the addition of Cu, and the amount of precipitation increases as the Cu content increases. This is because Sn grain boundary sliding is less likely to occur. In addition, the void ratio increases because the liquidus temperature rises as the Cu content increases, and the viscosity increases due to an increase in the precipitated solid phase, making it difficult for the flux gas to escape. . Furthermore, the remaining Ni thickness increases because the added Cu moves to the joint interface in the molten solder layer, and a ternary alloy is formed by Ni as the metallization and Sn as the main component. This is because the growth rate is lower than that of the binary alloy with Sn.

Regarding the ductility, in the region where the Ni content is low, the lower the Cu content, the better. When the Ni content is high, a certain amount or more is necessary, but the range of the Ni content is assumed. Thus, no significant change was observed due to the Cu content. As for the void ratio, there was no significant change in the range of the Cu content of about 5% by mass. On the other hand, it was found from the results of Ni cracking that it is necessary to add 0.5 mass% or more of Cu in order to suppress diffusion of Ni in the metallized layer 2L _r1 . However, regarding Cu, as the present inventors have found, since the main cause of Cv of vertical cracks is Cu precipitates, it is necessary to determine an upper limit value for suppressing Cu precipitates. When a power cycle test is carried out paying attention to this point, it is clear that when the Cu content exceeds 3 mass%, the amount of precipitates 3p in the Cu compound phase increases and becomes the base point of the vertical crack Cv. It became. Therefore, the upper limit of the Cu content is 3% by mass.

  Based on the above results, in an alloy based on Sn-10Sb-1In, Cu is contained in a range of 0.5 mass% or more and 3 mass% or less, whereby a highly reliable joint is obtained. The Cu content is most preferably about 2% by mass due to the balance of Ni diffusion suppression effect, void ratio, ductility, and Cu compound precipitation. Regarding the power cycle, when the Ni content is set to 0.01% by mass or more and 0.15% by mass or less, if the Cu content is 0.5% by mass or more and 3% by mass or less, the resistance increase is A highly reliable bond of 10% or less is obtained.

  As for the Ni content, as the Ni content increases, the metallization diffusion rate decreases and the bonding strength at a high temperature is maintained longer. That is, heat resistance is excellent. The effect is remarkable at 0.01 mass% or more. On the other hand, when the Ni content exceeds 0.15% by mass, voids increase remarkably. When there are many voids, it is disadvantageous in that the heat generated by the semiconductor device is released, so at present, the reference is about 0.15% by mass or less. Therefore, highly reliable joining is obtained by controlling the Ni content to 0.15% by mass or less. In addition, about the minimum of Ni content rate, although an effect is acquired even if it is less than 0.01 mass%, 0.01 mass% or more from which an effect appears notably is desirable. The Ni content is most preferably about 0.1% by mass, which is close to the solid solution limit in Sn at a soldering temperature of 270 ° C.

<In: 0.1 wt% to 5 wt%>
As a result of performing parameter test 3 to be described later, In is defined as 0.1% by mass or more and 5% by mass or less as an optimum range, and basically, ductility strengthening and void ratio which are important physical properties as a solder material. Optimized to suppress.
The solder material is cured by the above-described addition of Sb. Therefore, In is added to the solder material that has become too hard, and a ductile strengthening due to the dispersion of the In phase forms a metal structure that is hard to crack and can relieve stress. Moreover, the wettability of the solder material is improved by adding In. This is because the reactivity is improved by lowering the melting point. However, since In is an active element, if it is added too much, the solder material is oxidized and the wettability is lowered. The wettability can also be evaluated by the void ratio. For In, the optimum range of the composition is defined by the upper limit and the lower limit for the void ratio to be below a certain value.

Next, a detailed description will be given of a parameter test performed to determine the optimum range of each composition described above.
<Parameter test 1: Sb>
In the test, a round bar was made of a lead-free solder alloy in which the composition of Cu, Ni, and In was constant and the Sb composition was changed based on Sn, and the tensile strength and elongation were measured. As a test object, Sn-xSb-2Cu-1In-0.1Ni (mass%: x = 0, 2.5, 5, 10, 15, 16, 18, 20, 30, 40) was used. Prototype. Specifically, Sn, Sb, Cu, In, and Ni having a purity of 99.5% are weighed for each alloy having a different value of x so that the total is 2 kg. And it heats with a high frequency melting furnace until the maximum temperature becomes about 700 degreeC, After confirming that there is no unmelted, it casts with the casting mold of diameter 40x length 250mm, and produces a casting sample. Further, after solidification, it was machined into a round bar having a diameter of 25 mm × length of 180 mm with the center as a reference, and further machined as a chuck part for tensile testing to a diameter of 25 mm × length of 40 mm and a parallel part diameter of 8 mm × length of 90 mm. Tensile test pieces were prepared. Tensile tests were performed at a tensile rate of 0.5 mm / min on the tensile test specimens of lead-free solder alloys having different compositions.

  In addition, when processing the above-described tensile test piece, chips were collected from the vicinity of the two chuck portions and quantitative analysis was performed by emission analysis. As a result, for each composition, it was confirmed that the content was as intended with a single significant digit. The appearance check confirmed that there were no solder voids, surface defects, and discoloration.

  FIG. 5 shows the measurement results of tensile strength and elongation in the above tensile test, where the horizontal axis is the Sb content, the vertical axis is the tensile strength (●: black circle) on the left side, and the elongation on the right side (◇ : Diamond). As shown in the figure, the tensile strength improves as Sb is added, but the tensile strength increases remarkably with respect to the Sb content up to 5% by mass, and thereafter, the tensile strength increases slowly. It becomes. In other words, if the Sb content is less than 5% by mass, the tensile strength is greatly reduced, and changes sensitively to changes in the content. Since a high and stable tensile strength is desirable for the solder material, it is understood that the Sb content is preferably 5% or more from the viewpoint of tensile strength. On the other hand, it was found that the elongation decreased with an increase in the Sb content, and rapidly decreased after 15% by mass. Since high and stable elongation is desirable for the solder material, it is understood that it is desirable to suppress the Sb content to 15% by mass or less from the viewpoint of elongation.

That is, in order to achieve both tensile strength and elongation, the range OR _Sb (5 wt% to 15 wt%) sandwiched between the lower limit value of 5 mass% due to mechanical strength and the upper limit value of 15 mass% due to elongation is the optimum range of Sb. It can be said that there is.

  Further, among the above cast samples, those having an Sb content of 0 to 30% by mass, about several tens mg from the central part are taken out as DSC samples (DSC-1 to DSC-9), and DSC (Differential Scanning) Calorimeter: differential scanning calorimeter) was used to calculate the solidus temperature and the liquidus temperature. Here, the solidus temperature is defined as the lowest temperature of the peak first appearing in the endothermic curve obtained when heating at a constant rate of temperature increase (5 K / min). The liquidus temperature is defined as the maximum temperature of the peak first appearing in the exothermic curve obtained when cooling at a constant cooling rate (−K / min). Therefore, the solidus temperature and the liquidus temperature can be calculated from the lowest peak temperature during heating and the highest peak temperature during cooling, respectively. Table 1 shows the Sb content dependency of the solidus temperature and the liquidus temperature calculated by DSC measurement.

  As shown in Table 1, the liquidus temperature rises with increasing Sb content. The increase is gradual until the Sb content is 15% by mass (DSC-5), but is abrupt when it exceeds 15% by mass (DSC-6). The decrease in elongation shown in FIG. 1 is thought to be due to the fact that the finely dispersed Sb becomes coarser as the Sb content increases, and that the Sb precipitation amount increases abruptly when the Sb content exceeds 15 mass%. It is done. In the DSC test, the correlation between the Sb content value at which the liquidus increases rapidly and the threshold value for the change in elongation is obtained, so it is confirmed that the threshold value for elongation is certain. did it. Since it is desirable that the solder material 3M has both high tensile strength and elongation and a small amount of Sb is precipitated, the Sb content is determined to be in the range of 5% by mass to 15% by mass.

  Moreover, as shown in Table 1, the liquidus temperature rises with increasing Sb content, but the solidus temperature does not rise so much. Voids are easily formed when the bonding temperature is in the solid-liquid coexistence region (the region between the solidus temperature and the liquidus temperature), so the soldering temperature for obtaining good wettability is usually the liquidus. A temperature of about + 30 ° C or higher is desirable. When the Sb content is 15 mass% (DSC-5), the liquidus temperature is 255 ° C. Since the upper limit of a general heater is 300 ° C., there is no need to use a special heating device exceeding 300 ° C. if Sb is added in an amount of 15% by mass or less. On the other hand, when the Sb content is 16% by mass or more (DSC-6), the liquidus temperature is 290 ° C. In that case, a special heater is required to obtain good wettability. Therefore, it is desirable to set the Sb content to 15% by mass or less from the viewpoint of simplification of the apparatus and cost reduction.

Further, since the diffusion rate of the substrate-side metallization layer 2L _r2 is significantly increased above the solidus temperature, it is desirable that the solid-liquid coexistence region (region above the solidus temperature and below the liquidus temperature) is narrow. When the Sb content is 15% by mass (DSC-5), the temperature difference in the solid-liquid coexistence region is 21 ° C., and when 16% by mass (DSC-6) is 56 ° C. or 20% by mass ( Narrower than 81 ° C. of DSC-8). Therefore, it can be said that setting the Sb content to 15% by mass or less is a desirable composition for resistance to power cycle.

  As for the optimization of the Sb composition, the Cu content corresponding to the upper limit and lower limit of the optimum range obtained in the parameter test of other components described later is 0.5 mass% or more and less than 3 mass%, In content The same test was performed in the range where the rate was 0.1% by mass or more and 5% by mass or less and the Ni content was 0.01% by mass or more and 0.15% by mass or less, but it was confirmed that the same effect was obtained. did it.

<Parameter test 2: Cu, Ni>
In the test, a lead-free solder alloy in which the composition of Sb and In is constant and the composition of Cu and Ni is changed on the basis of Sn is prepared, and the semiconductor is formed using ductility as a material and a solder material formed of the lead-free solder alloy. The void ratio in the solder layer when the device was created, the presence or absence of Ni cracking due to metallization diffusion when the created semiconductor device was subjected to power cycle, and the peeling caused by the longitudinal crack during power cycle found by the present inventors The resistance increase rate for evaluation was measured. As a test object, Sn-10Sb-1In-xCu-yNi (mass%: x = 0, 0.25, 0.5, 1, 2, 2.5, 3, 5, y = 0, 0.01, Trial of 56 types of alloys (0.1, 0.15, 0.16, 0.17, 0.20). Specifically, Sn, Sb, Cu, In, and Ni having a purity of 99.5% are weighed for each alloy having different values of x and y so as to be 2 kg in total. Each material was melted at high frequency in a nitrogen atmosphere, and after confirming that the temperature reached 700 ° C. and that there was no undissolved material, an ingot was cast with a mold having a width of 20 mm × height of 10 mm × length of 150 mm.

  For both ends and the center of this ingot, the chips are collected with a drill, the Sb, Cu, and Ni of the chips are quantitatively analyzed by plasma fusion emission spectrometry, and the ingot is exactly as intended with a single digit. It was confirmed that Thereafter, this ingot was processed into a thickness of 0.1 mm with a rolling mill, and the surface was washed with 10% hydrochloric acid, then sufficiently washed with water, and cut into 8 mm square pellets with a cutter as a test sample. . Table 2 shows the composition of Cu and Ni of 56 kinds of lead-free solder alloys to be tested. Moreover, in Table 2, what is described as "Example" in the sample name is an alloy having a composition that fits the optimal range set by comprehensively setting the test results of Parameter Test 2, and what is described as "Comparative Example" An alloy with a composition deviating from the optimum range.

<Parameter test 2A: Ductility evaluation>
The ductility of the lead-free solder alloy as a material was evaluated by whether or not cracking occurred when the ingot was rolled to a thickness of 0.1 mm with a rolling mill. At this time, the case where a partial crack was generated during cutting was determined to be unacceptable (x: x), and the sample that did not crack was determined to be good (o: circle). Further, considering only ductility, the case where Ni and Cu are not contained is excellent. Therefore, the state when separately rolled for an alloy of Sn-10Sb-1In (x = y = 0) is best, ○ Out of the evaluation, the case where it was comparable to the best state by visual relative evaluation was evaluated as excellent (優: double circle). The evaluation results are shown in Table 3.

  As shown in Table 3, the most excellent ductility is excellent in a region where both Cu and Ni contents are low (Cu: 1 wt% or less, Ni: 0.01% or less). Further, when the Ni content exceeds 0.16%, the Cu content is 1% by mass or less, 0.25% by mass or less, and the result is that it becomes impossible unless the content is further lowered. When looking at the overall combination of Cu and Ni compositions, the composition that yields “good” or higher is in the range located on the left side of the thick line in the table.

<Parameter test 2B: Void rate evaluation>
The void ratio was evaluated by manufacturing a semiconductor device for each type of alloy and using a transmission X-ray image of the solder layer 3 portion in the manufactured semiconductor device. Specifically, ten semiconductor devices 1 are manufactured for each type of alloy by the above-described manufacturing method (FIG. 2). Then, using a transmission X-ray device, X-rays are made incident from the surface of the semiconductor element 2 of the manufactured semiconductor device 1, the obtained image is binarized by the image processing device, and the average value of the sum of the obtained areas Was calculated as an average void fraction. Table 4 shows the void ratio in the solder layer 3 for each type of alloy (Example, Comparative Example) of the manufactured semiconductor device 1. In addition, the value of a void ratio is an average value of the void ratio calculated with respect to each of ten semiconductor devices created for each type of alloy (Examples and Comparative Examples).

  As shown in Table 4, the void ratio is mainly influenced by the Ni content, and as the Ni content increases, the void ratio increases, particularly when the Ni content exceeds 0.15% by mass. Void rate increased. If the void ratio increases (the number of voids increases), the thermal conductivity decreases, which is disadvantageous in terms of releasing the heat generated by the semiconductor device. Therefore, it has been experimentally obtained that the void ratio needs to be suppressed to 14% or less in order to obtain an effective thermal conductivity. Therefore, from the results shown in Table 4, the composition that can suppress the void ratio that can keep the thermal conductivity above a certain level has a Ni content located to the left of the thick line in the table in the range of 0.15% or less.

<Parameter test 2C: Power cycle life evaluation>
Of the two main causes of deterioration of the solder joints, peeling due to metallization diffusion was evaluated by Ni cracking during power cycle, and peeling due to vertical cracking was evaluated by a resistance increase rate. Specifically, ten semiconductor devices 1 are manufactured for each type of alloy as in the parameter test 2B. As the power cycle, the power off process was set to 40 ° C., the power on time was set to 200 ° C., and the power cycle process of 5000 cycles was performed with the power off 10 seconds and the power on 10 seconds as one cycle. When the power was turned on, a current was passed between the ribbon 5 and the terminal 4Ea, the surface temperature of the semiconductor element 2 was measured by thermography, and the current was adjusted so that the maximum surface temperature was 200 ° C. It should be noted that the condition that the maximum surface temperature was 200 ° C. at the beginning of the cycle was 170 A (applied voltage 15 V).

  Then, after power cycling, an alloy in which peeling (Ni cracking) occurred in all samples due to Ni diffusion was evaluated as a fatal failure, and “x: x”, “Δ: Triangle”, an alloy that did not peel off was evaluated as good, and “◯: Circle” was attached. In Table 5, the evaluation result about the Ni crack after the power cycle for every kind (Example, comparative example) of the alloy of the manufactured semiconductor device 1 is shown.

As shown in Table 5, in the case of Sn-10Sb-1In solder alloy, when Ni is not added (0.00%), it is partially or All samples have delamination. Further, when the Cu content is less than 0.5% (0.25% or less), peeling is caused in a part or all of the sample due to diffusion of Ni as metallization regardless of the Ni content. That is, from the result of Ni cracking, in order to suppress diffusion of Ni in the metallized layer 2L _r1 , Cu located at the upper right of the thick line in the table is 0.5% by mass or more and Ni is 0.01% or more. It was found that the contained composition is effective.

Moreover, as a result of calculating the rate of increase in resistance after power cycle ((R _AP -R _BP ) / R _BP ), an alloy in which all the samples were 10% or less was evaluated as good. The average value of the rate of increase in resistance was 10% or less. However, an alloy having a sample with 10% or more individually was evaluated as △, and an alloy with a resistance increase rate of 10% or more in all samples was evaluated as defective. "X: Batsu". Table 6 shows the evaluation results based on the resistance increase rate after the power cycle for each type of alloy (Example, Comparative Example) of the manufactured semiconductor device 1.

  Among the evaluation results shown in Table 6, in the lower left region from the broken line, Ni cracking occurs as described above, and therefore it is unclear whether or not the vertical crack Cv is involved as a cause of the increase in resistance. However, since the Ni crack does not occur in the upper right area from the broken line, the resistance has increased due to a cause other than the Ni crack. Therefore, the upper right area from the broken line is examined. When the Cu content exceeds 3% by mass (5 wt%), the amount of the precipitate 3p in the Cu compound phase increases, which becomes the base point of the vertical crack Cv. Further, when the Ni content exceeds 0.15% by mass, the rate of determination as defective due to the resistance increase rate increases rapidly. When the Ni content is 0.16% by mass, the Cu content is 0.5 wt% and 1 wt%. Except for, x or Δ. This is considered to be because the base point of the vertical crack increased as the content of Ni or Cu increased, and the horizontal crack occurred along the void or along the vertical crack. And this idea is based on the fact that in Table 4 in which the void ratio at the time of initial bonding, which is an index of the precipitate that becomes the starting point of the vertical crack Cv, was evaluated, the void ratio rapidly increased when the Ni content was 0.16% by mass or more, Is consistent with the tendency for ductility to decrease as shown in Table 3.

  That is, from the result of the resistance increase rate with the vertical crack Cv, it is possible to suppress the Cu content to 3% or less and to set the upper limit value so that the Ni content is also on the right side of the thick line in the table. It can be seen that it is desirable to prevent joint degradation due to cracks.

  Therefore, as a result of the parameter tests 2A and 2B and 2C in consideration of the power cycle, the Cu content is 0.5% by mass or more and 3% by mass or less and the Ni content is 0. 01% or more and 0.15%. In addition, about the minimum of Ni content rate, although an effect is acquired even if it is less than 0.01 mass%, 0.01 mass% by which expression of the effect was confirmed was made into the minimum value.

  The Sb content set in the parameter test 1 is in the range of 5 to 15% by mass, and the In content set in the parameter test 3 to be described later is in the range of 0.1 to 5% by mass. It was confirmed that the same effect was obtained with the lead-free solder alloy obtained in the same experiment as described above.

<Parameter test 3: In>
In the test, the composition of Sb, Cu, and Ni was made constant, and the In composition was changed based on Sn to create solder pellets. Similar to the parameter test 2B, a semiconductor device was prototyped and the void ratio was evaluated by image analysis. As test objects, nine types of alloys of Sn-10Sb-2Cu-xIn-0.1Ni (mass%: x = 0, 0.1, 0.5, 1, 3, 5, 6, 7, 8) were used. Prototype. In addition, since In is a kind of rare metal, the cost for each alloy composition was also estimated. The cost was calculated as a price ratio with respect to the price of In-free alloy (Comparative Example 37) with Sn-10Sb-2Cu-0.1Ni of 3000 yen per kg and indium of 60,000 yen per kg. Table 7 shows the average value of the void ratio measured for each alloy type (Example, Comparative Example) and the estimated cost ratio.

Moreover, FIG. 6 has shown the measurement result of the void rate in the parameter test 3, and a horizontal axis is In content rate in a figure, and a vertical axis | shaft is an average void rate. Since In has a low melting point (156 ° C.), the addition of a slight amount (0.1% by mass) lowers the melting point and improves the reactivity, so that the void ratio is greatly reduced (improved). On the other hand, In is easily oxidized as compared with other materials, if it is added in an amount of more than 5% by mass, the precipitated In is oxidized and the wettability is inhibited, so that the void ratio is increased (deteriorated). Therefore, assuming that the upper limit threshold Th _V of the void ratio is 14%, in order to keep the void ratio below the threshold Th _V , the In content is set to a range OR _In of 0.1 mass% or more and 5 mass% or less. I understand that things are desirable.

  In addition, as shown in the table, since In is expensive, the cost increases as more In is added. Therefore, the In content is more preferably suppressed to 3% by mass or less.

  As for the optimization of the In composition, the Sb content is 5% by mass or more and 15% by mass or less and the Cu content is 0. 0% corresponding to the upper and lower limits of the optimum range set in the other parameter test described above. The same test was performed in the range of 5% by mass to less than 3% by mass, In content of 0.1% by mass to 5% by mass, and Ni content of 0.01% by mass to 0.15% by mass. However, it was confirmed that the same effect (void ratio reduction effect) was obtained.

<Effect confirmation test of other additive materials>
As described above, one or more selected from the group consisting of P, Ge, Ga, and Bi is added in a total of 0.01% by mass or more to the lead-free solder alloy having the optimized composition range of Sb, Cu, In, and Ni. The lead-free solder alloy added so that it might contain below mass% was manufactured. Then, the semiconductor device 1 in which the silicon carbide semiconductor element 2 is bonded to the metal electrode 4Ea of the circuit board 4 using the solder alloy under the same conditions as described above is manufactured, and the void ratio is measured in the same manner as the parameter test 2B. did. As a result, in all the alloy compositions, an improvement effect of 2% to 10% (reduction in average void ratio) was observed. In addition, the remarkable improvement effect was not able to be confirmed in the alloy composition which contained 1 or more types chosen from the group which consists of P, Ge, Ga, Bi in total 0.005 mass%. Moreover, in the alloy composition containing 1.5% by mass and 3% by mass in total of one or more selected from the group consisting of P, Ge, Ga, and Bi, the void ratio tended to increase.

<Effect confirmation test with other bonding partner>
In the parameter test for optimizing the composition and the test of other additive materials, the counterpart to join the semiconductor element 2 with the solder material 3M was the copper circuit pattern 4Ea formed on the circuit board 4. In this confirmation test, a circuit pattern made of Cu / Inver / Cu and Cu / Mo / Cu formed on the circuit board was used as a bonding partner. The thickness of each layer in the case of Cu / Inver / Cu is 0.4 / 0.4 / 0.4 mm. The thickness of each layer in the case of Cu / Mo / Cu is 0.4 / 0.4 / 0.4 mm. The crack rate when Cu / Inver / Cu is used as the bonding partner is about 1/2 compared to the Cu circuit pattern 4Ea, and the crack rate when Cu / Mo / Cu is used as the bonding partner is about 1/3. Was confirmed. In addition, a similar experiment was conducted in the case where Ni plating was not applied to the circuit pattern surface including Cu, but both the crack rate and the diffusion of metallization were improved by about 20%. From the above, it was confirmed that the effect can be obtained regardless of the electrode material and the surface treatment.

  Further, the same effect was obtained in the same experiment as described above with several different sizes of metal elements and chips with metallized specifications. Furthermore, the same test was performed on a semiconductor device based on GaN (gallium nitride) or diamond or a conventional Si (silicon) device, and the same effect was obtained.

  The semiconductor device may be any of a module, a package, and a device mounted on a substrate. In this embodiment, Ti (titanium) is used as the ohmic layer, but metals other than Ti, for example, Ni (nickel), Al (aluminum), Mo (molybdenum), or Ti are contained. It is possible to use compounds such as elemental silicides and a multilayer structure combining these compounds. It is also possible to remove the ohmic layer.

  When the semiconductor device 10 made using the solder material 3M formed of the lead-free solder alloy having the optimized composition as described above is operated, the operating temperature rises to 200 ° C. or higher, and temporarily rises to several hundred degrees. There are things to do. However, when the semiconductor element 2 is bonded to the electrode 4E using the lead-free solder alloy solder material 3M as in the present embodiment, the bonding strength is firmly maintained within the operating temperature of the semiconductor element. Can do.

  Here, for example, when silicon carbide, a gallium nitride-based material, or diamond is used for a semiconductor element that functions as a switching element or a rectifying element, power loss is lower than that of a conventionally formed element made of silicon. Therefore, the efficiency of the power semiconductor device can be increased. Further, since the withstand voltage is high and the allowable current density is also high, the power semiconductor device can be downsized. In addition, wide band gap semiconductor elements have high heat resistance, so they can operate at high temperatures, and the heat sink fins can be downsized and the water cooling section can be air cooled. Is possible.

  On the other hand, in order to exhibit the performance of the wide band gap semiconductor element, it is necessary to reduce the electrical resistance when current flows through the semiconductor element and to efficiently dissipate the heat generated in the semiconductor element. Therefore, if a semiconductor element is mounted using the lead-free solder alloy solder material described in the embodiment of the present invention, it has excellent heat dissipation characteristics and electrical conductivity, and is strong even under the thermal cycle during manufacturing and driving. Since the bonding can be maintained, a highly reliable semiconductor device or semiconductor module can be obtained.

  As described above, according to the lead-free solder alloy according to the present embodiment, Sb is 5% by mass to 15% by mass, Cu is 0.5% by mass to 3% by mass, and Ni is 0.01% by mass or more. Containing 0.15% by mass or less, In 0.1% by mass or more and 5% by mass or less, and composed of the remainder Sn and inevitable impurities, so that the deterioration of the junction due to metallization diffusion at high temperature is suppressed. Needless to say, deterioration during power cycle can also be suppressed, so that it is possible to improve junction reliability with respect to power cycle in a semiconductor device operating at a high temperature.

  If the lead-free solder alloy is further added with at least one of P, Ge, Ga, and Bi so as to contain a total of 0.01% by mass to 1% by mass, the life against power cycle is further increased. Reliability is improved.

  As described above, the semiconductor device according to the present embodiment includes the circuit board 4 on which the circuit pattern 4Ea is formed and the semiconductor element 2 mounted on the circuit pattern 4Ea. Since the lead-free solder alloy described above (solder material 3M formed of) is used for bonding to 4Ea, a highly reliable semiconductor device that maintains strong bonding even after repeated high-temperature operation and power cycle Can be obtained.

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment, the solder material 3M formed of the above lead-free solder alloy is arranged in a predetermined range on the circuit pattern 4Ea of the circuit board 4 constituting the semiconductor device 1. A step, a step of installing the semiconductor element 2 on the arranged solder material 3M, and a step of heating the solder material 3M so as to melt and joining the semiconductor element 2 to a predetermined position of the circuit pattern 4Ea. Therefore, even when high-temperature operation or power cycle is repeated, a strong bonding can be maintained and a highly reliable semiconductor device can be obtained.

2 semiconductor element, 2B semiconductor substrate, 2L _f1 wiring member side ohmic layer, 2L _f2 wiring member side metallization layer, 2L _r1 substrate side ohmic layer, 2L _r2 substrate side metallization layer, 2L _r3 alloy layer, 3 solder (after bonding) Solder layer), 3M solder pellet (solder material), 3p precipitate, 4 circuit board, 4E circuit pattern, 5 ribbon (wiring member),
10 Semiconductor device, Ch horizontal crack, Cv vertical crack

Claims (6)

Sb is 5 mass% or more and 15 mass% or less,
Cu is 0.5 mass% or more and 3 mass% or less,
Ni is 0.01 mass% or more and 0.15 mass% or less,
Containing 0.1% by mass or more and 5% by mass or less of In,
A lead-free solder alloy comprising the remaining Sn and inevitable impurities.   2. The lead-free solder alloy according to claim 1, wherein at least one of P, Ge, Ga, and Bi is added so as to contain 0.01% by mass or more and 1% by mass or less in total. A circuit board on which a circuit pattern is formed;
A semiconductor element mounted on the circuit pattern,
A semiconductor device using the lead-free solder alloy according to claim 1 or 2 for joining the semiconductor element to the circuit pattern.   The semiconductor device according to claim 3, wherein the semiconductor element is formed of a wide band gap semiconductor material.   The semiconductor device according to claim 4, wherein the wide band gap semiconductor material is any one of silicon carbide, gallium nitride, diamond, and gallium arsenide. Placing a solder material formed of a lead-free solder alloy according to claim 1 or 2 in a predetermined range on a circuit pattern of a circuit board constituting a semiconductor device;
Installing a semiconductor element on the arranged solder material;
Heating the solder material so as to melt, and bonding the semiconductor element to a predetermined position of the circuit pattern;
A method for manufacturing a semiconductor device, comprising:

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