JPWO2012011390A1 - Input device and manufacturing method thereof - Google Patents

Input device and manufacturing method thereof Download PDF

Info

Publication number
JPWO2012011390A1
JPWO2012011390A1 JP2011551369A JP2011551369A JPWO2012011390A1 JP WO2012011390 A1 JPWO2012011390 A1 JP WO2012011390A1 JP 2011551369 A JP2011551369 A JP 2011551369A JP 2011551369 A JP2011551369 A JP 2011551369A JP WO2012011390 A1 JPWO2012011390 A1 JP WO2012011390A1
Authority
JP
Japan
Prior art keywords
wiring
region
width
input
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011551369A
Other languages
Japanese (ja)
Other versions
JP4963524B2 (en
Inventor
高橋　亨
亨 高橋
佐藤　清
清 佐藤
義人 佐々木
義人 佐々木
秀幸 橋本
秀幸 橋本
恭輔 尾崎
恭輔 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP2011551369A priority Critical patent/JP4963524B2/en
Application granted granted Critical
Publication of JP4963524B2 publication Critical patent/JP4963524B2/en
Publication of JPWO2012011390A1 publication Critical patent/JPWO2012011390A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)

Abstract

配線層は、電極層の端部との接続位置に設けられた接続端部２３ａ〜２３ｅと、前記接続端部から引き出された配線延出部２４ａ〜２４ｅとを備える。複数本の前記配線層における配線延出部２４ａ〜２４ｅが、夫々、入力領域から見て同じ側のＸ１側非入力領域１２ａでＸ１−Ｘ２方向に間隔を空けた状態でＹ１−Ｙ２方向に延出しているとともに、各配線延出部２４ａ〜２４ｅの配線幅は、前記Ｘ１−Ｘ２にて並設される前記配線層の本数が少ない領域ほど、大きく形成されている。The wiring layer includes connection end portions 23a to 23e provided at connection positions with the end portions of the electrode layers, and wiring extension portions 24a to 24e drawn from the connection end portions. The wiring extension portions 24a to 24e in the plurality of wiring layers extend in the Y1-Y2 direction with the X1-side non-input area 12a on the same side as viewed from the input area spaced apart in the X1-X2 direction. In addition, the wiring width of each of the wiring extending portions 24a to 24e is formed larger in a region where the number of the wiring layers arranged in parallel at the X1-X2 is smaller.

Description

本発明は、入力領域の外側に位置する非入力領域に複数の配線層が延出して形成されて成る入力装置に関し、特に配線層の構造に関する。   The present invention relates to an input device formed by extending a plurality of wiring layers in a non-input region located outside an input region, and more particularly to a structure of a wiring layer.

以下の特許文献１，２には、入力装置（タッチパネル）の構造が開示されている。入力装置の入力領域には複数本の電極層が配置されている。そして操作者が指等で入力領域を操作すると、その操作位置を静電容量変化等で検出できるようになっている。入力領域の外側の非入力領域には、各電極層に電気的に接続された配線層が形成されている。   The following Patent Documents 1 and 2 disclose the structure of an input device (touch panel). A plurality of electrode layers are arranged in the input area of the input device. When the operator operates the input area with a finger or the like, the operation position can be detected by a change in capacitance or the like. A wiring layer electrically connected to each electrode layer is formed in the non-input region outside the input region.

特許文献１等に示す前記配線層は、図９に示すように、各電極層の端部との接続位置に設けられた幅の太い接続端部１（特許文献１には太幅部と記載されている）と、接続端部１から延出する配線延出部２（特許文献１には細幅部と記載されている）とで構成される。   As shown in FIG. 9, the wiring layer shown in Patent Document 1 or the like has a thick connection end 1 provided at a connection position with the end of each electrode layer (described as a wide width part in Patent Document 1). And a wiring extension portion 2 extending from the connection end portion 1 (described as a narrow width portion in Patent Document 1).

図９に示すように、各配線層の配線延出部２は、ほぼ同じ幅寸法で細長く形成されている。なお特許文献１には前記配線延出部の配線幅について記載されていないが、特許文献１の図面から判断すると、各配線層の配線延出部の配線幅は図９に示すように、全て、ほぼ同じ幅寸法で形成されていると考えられる。   As shown in FIG. 9, the wiring extension part 2 of each wiring layer is formed to be elongated with substantially the same width dimension. In addition, although the wiring width of the said wiring extension part is not described in patent document 1, but judging from the drawing of patent document 1, the wiring width of the wiring extension part of each wiring layer is as shown in FIG. It is considered that they are formed with substantially the same width dimension.

しかしながら、かかる形態では、特に配線延出部２の長い配線層ほど異物の混入等で断線する確率が高くなる構造となっている。また各配線層の配線抵抗のばらつきが大きくなる問題がある。   However, in such a configuration, the wiring layer having a long wiring extension portion 2 has a structure in which the probability of disconnection due to foreign matters is increased. In addition, there is a problem that variation in wiring resistance of each wiring layer becomes large.

また、特許文献２に記載された発明では、配線層の長さ寸法が長いものほど、配線幅が細くなるように形成されているため、ますます断線の問題が生じやすく配線抵抗のばらつきが更に大きくなってしまう。   Further, in the invention described in Patent Document 2, since the wiring layer is formed so that the wiring width becomes narrower as the length of the wiring layer becomes longer, the problem of disconnection is more likely to occur, and the variation in wiring resistance further increases. It gets bigger.

特開２０１０−６１３８４号公報JP 2010-61384 A 特開２００９−２５８９３５号公報JP 2009-258935 A

そこで本発明は上記従来の課題を解決するためのものであり、特に、配線構造を改良して、断線の確率を低減し、更に各配線層の配線抵抗のばらつきを抑制することが可能な入力装置及びその製造方法を提供することを目的とする。   Therefore, the present invention is for solving the above-described conventional problems, and in particular, an input capable of improving the wiring structure, reducing the probability of disconnection, and further suppressing variations in the wiring resistance of each wiring layer. An object is to provide an apparatus and a method for manufacturing the same.

本発明における入力装置は、
入力領域に設けられた電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有し、
前記配線層は、前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備え、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部が、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出しているとともに、各配線延出部の配線幅は、前記第１の方向にて並設される前記配線層の本数が少ない領域ほど、大きく形成されていることを特徴とするものである。The input device in the present invention is
Having an electrode layer provided in the input region and a wiring layer routed in a non-input region outside the input region;
The wiring layer includes a connection end portion provided at a connection position with the end portion of the electrode layer, and a wiring extension portion led out from the connection end portion,
When two directions orthogonal to each other in the plane are defined as a first direction and a second direction, the wiring extension portions in the plurality of wiring layers are each non-input on the same side as viewed from the input region. The wiring layer that extends in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is arranged in parallel in the first direction The region having a smaller number of is larger in size.

また本発明は、入力領域に電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有して成る入力装置の製造方法において、
前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備える前記配線層を形成し、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部を、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出させるとともに、各配線延出部の配線幅を、前記第１の方向にて並設される前記配線層の本数が少ないほど、大きく形成することを特徴とするものである。Further, the present invention provides an input device manufacturing method comprising an electrode layer in an input region and a wiring layer routed in a non-input region outside the input region.
Forming the wiring layer comprising a connection end provided at a connection position with the end of the electrode layer, and a wiring extension drawn from the connection end;
When the two directions orthogonal to each other in the plane are defined as the first direction and the second direction, the non-inputs on the same side as viewed from the input region, the wiring extension portions in the plurality of wiring layers, respectively. The wiring layer is extended in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is set to be parallel to the first direction. The smaller the number, the larger the formation.

このように本発明では、各配線延出部の配線幅を従来のように同じ幅で形成するのではなく、並設される配線層の本数が少ない領域ほど大きく形成した。よって、長さの長い配線延出部に対して、並設される配線層の本数が少ない領域で配線幅を大きく形成でき、断線の確率を従来に比べて効果的に低くすることが出来る。さらに、配線延出部の配線幅は、配線延出部の長さ寸法が長くなるほど、平均して大きくすることができるため、各配線層の配線抵抗のばらつきを小さくすることが可能になる。   As described above, in the present invention, the wiring width of each wiring extension portion is not formed with the same width as in the prior art, but is formed larger in a region where the number of wiring layers arranged in parallel is smaller. Therefore, the wiring width can be increased in a region where the number of wiring layers arranged in parallel is small with respect to the long wiring extension portion, and the probability of disconnection can be effectively reduced as compared with the conventional case. Furthermore, since the wiring width of the wiring extension portion can be increased on average as the length dimension of the wiring extension portion becomes longer, it is possible to reduce variations in the wiring resistance of each wiring layer.

本発明では、前記配線延出部には、前記第２の方向に向けて徐々に配線幅が変化する幅変化領域が形成されていることが好ましい。また前記幅変化領域における側端部の前記第２の方向に対する傾き角度θ１は４５°以下であることが好ましい。更に、前記配線延出部は、前記第２の方向に向けて、前記幅変化領域と、前記第２の方向に平行に延びる配線幅が一定の幅一定領域とが交互に繰り返して形成されており、前記幅変化領域は前記幅一定領域から折れ曲がって形成されていることが好ましい。   In the present invention, it is preferable that a width change region in which the wiring width gradually changes toward the second direction is formed in the wiring extension portion. In addition, the inclination angle θ1 of the side end portion in the width change region with respect to the second direction is preferably 45 ° or less. Further, the wiring extension portion is formed by alternately repeating the width changing region and a constant width region extending in parallel to the second direction toward the second direction. The width change region is preferably bent from the constant width region.

上記のように幅変化領域を形成することで、配線層を、エッチングにて所定形状に形成する際に、配線延出部の側端部に形成されるコーナー部分にエッチング液の液溜りができるのを抑制でき、各配線層を所定形状にて適切に形成することが可能になる。また、非入力領域の限られた非入力領域内に効率良く各配線延出部を形成することができる。   By forming the width change region as described above, when the wiring layer is formed into a predetermined shape by etching, the etching liquid can be accumulated in the corner portion formed at the side end portion of the wiring extension portion. Therefore, each wiring layer can be appropriately formed in a predetermined shape. Moreover, each wiring extension part can be efficiently formed in the non-input area where the non-input area is limited.

本発明では、並設される配線層の本数が少ない領域ほど配線幅を大きく形成するため、長さの長い配線延出部に対して、並設される配線層の本数が少ない領域で配線幅を大きく形成できる。よって断線の確率を従来に比べて効果的に低くすることが出来る。さらに、配線延出部の配線幅は、配線延出部の長さ寸法が長くなるほど、平均して大きくすることができるため、各配線層の抵抗抵抗のばらつきを小さくすることが可能になる。   In the present invention, the wiring width is increased in a region where the number of wiring layers arranged in parallel is smaller, so that the wiring width is reduced in a region where the number of wiring layers arranged in parallel is smaller than a long wiring extension portion. Can be formed large. Therefore, the probability of disconnection can be effectively reduced as compared with the conventional case. Furthermore, since the wiring width of the wiring extension portion can be increased on average as the length dimension of the wiring extension portion becomes longer, it is possible to reduce variations in resistance resistance of each wiring layer.

本実施形態の静電容量式の入力装置（タッチパネル）の下部基板の平面図、The top view of the lower board | substrate of the electrostatic capacitance type input device (touch panel) of this embodiment, 本実施形態の上部基板の平面図、A plan view of the upper substrate of this embodiment, 本実施形態における入力装置をＸ１−Ｘ２方向に向けて切断したときの部分縦断面図、The partial longitudinal cross-sectional view when the input device in this embodiment is cut | disconnected toward X1-X2 direction, 図４（ａ）は、本実施形態における配線層の部分拡大平面図、図４（ｂ）は、図４（ａ）に示す各配線層の配線延出部の配線幅を示す模式図、図４（ｃ）は、図４（ｂ）と異なる形態を示す配線幅を示す模式図、FIG. 4A is a partially enlarged plan view of the wiring layer in the present embodiment, and FIG. 4B is a schematic diagram showing the wiring width of the wiring extension portion of each wiring layer shown in FIG. 4 (c) is a schematic diagram showing a wiring width showing a different form from FIG. 4 (b), 図３とは異なる形態の入力装置の部分縦断面図、FIG. 3 is a partial vertical cross-sectional view of an input device in a form different from FIG. 図３とは異なる形態の入力装置の部分縦断面図、FIG. 3 is a partial vertical cross-sectional view of an input device in a form different from FIG. 図７（ａ）は、図１〜図３と異なる形態の入力装置の部分平面図、図７（ｂ）は、部分縦断面図、FIG. 7A is a partial plan view of an input device having a different form from those in FIGS. 1 to 3, and FIG. 本実施形態の入力装置の下部基板の製造方法を示す一工程図（部分縦断面図）、1 process drawing (partial longitudinal cross-sectional view) which shows the manufacturing method of the lower board | substrate of the input device of this embodiment, 従来の配線層の平面図。The top view of the conventional wiring layer.

図１は、本実施形態の静電容量式の入力装置（タッチパネル）の下部基板の平面図、図２は上部基板の平面図、図３は、本実施形態における入力装置をＸ１−Ｘ２方向に向けて切断したときの部分縦断面図、図４（ａ）は、本実施形態における配線層の部分拡大平面図、図４（ｂ）は、図４（ａ）に示す各配線層の配線延出部の配線幅を示す模式図、図４（ｃ）は、図４（ｂ）と異なる形態を示す配線幅を示す模式図である。   1 is a plan view of a lower substrate of the capacitive input device (touch panel) of the present embodiment, FIG. 2 is a plan view of the upper substrate, and FIG. 3 is a diagram illustrating the input device according to the present embodiment in the X1-X2 direction. FIG. 4A is a partially enlarged plan view of a wiring layer in the present embodiment, and FIG. 4B is a wiring extension of each wiring layer shown in FIG. 4A. FIG. 4C is a schematic diagram showing the wiring width of the protruding portion, and FIG. 4C is a schematic diagram showing the wiring width showing a different form from FIG. 4B.

図１，図３に示す下部基板２２は、下部基材３２と下部基材３２の表面に形成された複数本の下部電極層１４とを有して構成される。各下部電極層１４は入力領域（センサ領域）１１内に形成される。   The lower substrate 22 shown in FIGS. 1 and 3 includes a lower base 32 and a plurality of lower electrode layers 14 formed on the surface of the lower base 32. Each lower electrode layer 14 is formed in the input region (sensor region) 11.

図１に示すように各下部電極層１４は、いずれも複数の第１電極部４０がＸ１−Ｘ２方向（第１の方向）に、前記第１電極部４０より細い連結部４１を介して連設された形態である。なお図１では一つの第１電極部４０及び連結部４１にのみ符号を付した。図１では、第１電極部４０の形状が略菱形形状で形成されているが、この形状に限定するものではない。   As shown in FIG. 1, each lower electrode layer 14 includes a plurality of first electrode portions 40 connected in the X1-X2 direction (first direction) via a connecting portion 41 that is thinner than the first electrode portion 40. It is a set form. In FIG. 1, only one first electrode part 40 and one connection part 41 are denoted by reference numerals. In FIG. 1, although the shape of the 1st electrode part 40 is formed in the substantially rhombus shape, it is not limited to this shape.

そして図１に示すように各下部電極層１４は、Ｘ１−Ｘ２方向に直交するＹ１−Ｙ２方向（第２の方向）に所定の間隔を空けて配列されている。   As shown in FIG. 1, the lower electrode layers 14 are arranged at a predetermined interval in the Y1-Y2 direction (second direction) orthogonal to the X1-X2 direction.

なお、この実施形態では、Ｘ１−Ｘ２方向を第１の方向とし、Ｙ１−Ｙ２方向を第２の方向と設定したが、方向を限定するものではない。   In this embodiment, the X1-X2 direction is set as the first direction, and the Y1-Y2 direction is set as the second direction. However, the direction is not limited.

図１に示すように入力領域１１の周囲は額縁状の非入力領域１２となっている。
図１に示すように、非入力領域１２には各下部電極層１４のＸ１−Ｘ２方向における端部と電気的に接続される複数本の配線層１５ａ〜１５ｊが形成されている。なお図１では、各配線層１５ａ〜１５ｊを全て同じ線状にて模式的に示したが、実際には後述する図４（ａ）に示すような配線形状で形成されている。図１に示すように、各配線層１５ａ〜１５ｅは、一つ置きに配列された各下部電極層１４のＸ１側端部に電気的に接続されている。また各配線層１５ｆ〜１５ｊは、残りの各下部電極層１４のＸ２側端部に電気的に接続されている。As shown in FIG. 1, the periphery of the input area 11 is a frame-shaped non-input area 12.
As shown in FIG. 1, a plurality of wiring layers 15 a to 15 j that are electrically connected to the end portions in the X1-X2 direction of the respective lower electrode layers 14 are formed in the non-input region 12. In FIG. 1, all of the wiring layers 15a to 15j are schematically shown in the same line shape, but in actuality, they are formed in a wiring shape as shown in FIG. As shown in FIG. 1, the wiring layers 15 a to 15 e are electrically connected to the X1 side end portions of the lower electrode layers 14 that are arranged every other line. The wiring layers 15 f to 15 j are electrically connected to the X2 side end portions of the remaining lower electrode layers 14.

図１に示すように、各配線層１５ａ〜１５ｅは、入力領域１１から見てＸ１側に位置するＸ１側非入力領域１２ａ内にて引き回されている。各配線層１５ａ〜１５ｅはＸ１−Ｘ２方向（第１の方向）に間隔を空けた状態で、Ｙ１−Ｙ２方向（第２の方向）に直線状に延出して形成されている。また図１に示すように各配線層１５ａ〜１５ｅの先端は入力領域１１から見てＹ２側に位置するＹ２側非入力領域１２ｂに位置して、フレキシブルプリント基板（図示しない）と電気的に接続される外部接続部２７を構成している。   As shown in FIG. 1, each of the wiring layers 15 a to 15 e is routed in the X1 side non-input area 12 a located on the X1 side when viewed from the input area 11. Each of the wiring layers 15a to 15e is formed to extend linearly in the Y1-Y2 direction (second direction) with a space in the X1-X2 direction (first direction). As shown in FIG. 1, the tips of the wiring layers 15a to 15e are located in the Y2 side non-input area 12b located on the Y2 side when viewed from the input area 11, and are electrically connected to a flexible printed circuit board (not shown). The external connection unit 27 is configured.

また図１に示すように、各配線層１５ｆ〜１５ｊは、入力領域１１から見てＸ２側に位置するＸ２側非入力領域１２ｃ内にて引き回されている。各配線層１５ｆ〜１５ｊはＸ１−Ｘ２方向（第１の方向）に間隔を空けた状態で、Ｙ１−Ｙ２方向（第２の方向）に直線状に延出して形成されている。また図１に示すように各配線層１５ｆ〜１５ｊの先端は入力領域１１から見てＹ２側に位置するＹ２側非入力領域１２ｂに位置して、フレキシブルプリント基板（図示しない）と電気的に接続される外部接続部１７を構成している。   As shown in FIG. 1, the wiring layers 15 f to 15 j are routed in the X2 side non-input area 12 c located on the X2 side when viewed from the input area 11. Each of the wiring layers 15f to 15j is formed to extend linearly in the Y1-Y2 direction (second direction) with an interval in the X1-X2 direction (first direction). Further, as shown in FIG. 1, the tips of the wiring layers 15f to 15j are located in the Y2 side non-input area 12b located on the Y2 side when viewed from the input area 11, and are electrically connected to a flexible printed circuit board (not shown). The external connection unit 17 is configured.

図３に示すように配線層１５（図３では統一して符号１５と示した）は、透明導電層１６上に重ねて形成されている。この透明導電層１６は入力領域１１に位置する各下部電極層１４と一体に形成されたＩＴＯ膜等であり、非入力領域１２では、各配線層１５と略同一の配線パターン形状にて形成されている。   As shown in FIG. 3, the wiring layer 15 (generally indicated by reference numeral 15 in FIG. 3) is formed on the transparent conductive layer 16. The transparent conductive layer 16 is an ITO film or the like formed integrally with each lower electrode layer 14 located in the input region 11. In the non-input region 12, the transparent conductive layer 16 is formed in a wiring pattern shape substantially the same as each wiring layer 15. ing.

図２，図３に示す上部基板２１は、上部基材３３と上部基材３３の表面に形成された複数本の上部電極層１３とを有して構成される。各上部電極層１３は入力領域（センサ領域）１１内に形成される。   The upper substrate 21 shown in FIGS. 2 and 3 includes an upper base material 33 and a plurality of upper electrode layers 13 formed on the surface of the upper base material 33. Each upper electrode layer 13 is formed in the input region (sensor region) 11.

図２に示すように各上部電極層１３は、いずれも複数の第２電極部４２がＹ１−Ｙ２方向（第２の方向）に、前記第２電極部４２より細い連結部４３を介して連設された形態である。なお図２では一つの第２電極部４２及び連結部４３にのみ符号を付した。図２では、第２電極部４２の形状が略菱形形状で形成されているが、この形状に限定するものではない。   As shown in FIG. 2, each upper electrode layer 13 includes a plurality of second electrode portions 42 connected in the Y1-Y2 direction (second direction) via a connecting portion 43 that is thinner than the second electrode portion 42. It is a set form. In FIG. 2, only one second electrode portion 42 and the connecting portion 43 are denoted by reference numerals. In FIG. 2, the shape of the second electrode portion 42 is formed in a substantially rhombus shape, but is not limited to this shape.

そして図２に示すように各上部電極層１３は、Ｘ１−Ｘ２方向（第１の方向）に所定の間隔を空けて配列されている。   As shown in FIG. 2, the upper electrode layers 13 are arranged at predetermined intervals in the X1-X2 direction (first direction).

図２に示すように、非入力領域１２には各上部電極層１３のＹ１−Ｙ２方向における端部と電気的に接続される複数本の配線層１８ａ〜１８ｇが形成されている。図２に示すように、各配線層１８ａ〜１８ｇは、各上部電極層１３のＹ２側端部に電気的に接続されている。   As shown in FIG. 2, in the non-input region 12, a plurality of wiring layers 18 a to 18 g that are electrically connected to the end portions of the upper electrode layers 13 in the Y1-Y2 direction are formed. As shown in FIG. 2, the wiring layers 18 a to 18 g are electrically connected to the Y2 side end portions of the upper electrode layers 13.

図２に示すように、各配線層１８ａ〜１８ｇは、入力領域１１から見てＹ２側に位置するＹ２側非入力領域１２ｂ内にて引き回されている。そして図２に示すように各配線層１８ａ〜１８ｇの先端は、Ｙ２側非入力領域１２ｂ内にて、フレキシブルプリント基板（図示しない）と電気的に接続される外部接続部１９を構成している。上部基板２１に形成された外部接続部１９と、下部基板２２に形成された外部接続部２７，１７（図１参照）とは平面的に重ならないように形成されている。   As shown in FIG. 2, the wiring layers 18 a to 18 g are routed in the Y2 side non-input area 12 b located on the Y2 side when viewed from the input area 11. And as shown in FIG. 2, the front-end | tip of each wiring layer 18a-18g comprises the external connection part 19 electrically connected with a flexible printed circuit board (not shown) in the Y2 side non-input area 12b. . The external connection portion 19 formed on the upper substrate 21 and the external connection portions 27 and 17 (see FIG. 1) formed on the lower substrate 22 are formed so as not to overlap in plan view.

図３に示すように下部基板２２と上部基板２１との間は粘着層３０を介して接合されている。   As shown in FIG. 3, the lower substrate 22 and the upper substrate 21 are bonded via an adhesive layer 30.

各電極層１３，１４はいずれも基材表面にＩＴＯ（Indium Tin Oxide）等の透明導電材料でスパッタや蒸着により成膜される。また基材３２，３３は、ポリエチレンテレフタレート（ＰＥＴ）等のフィルム状の透明基材やガラス基材等で形成される。また各配線層１５ａ〜１５ｊ，１８ａ〜１８ｇは、Ｃｕ、Ｃｕ合金、ＣｕＮｉ合金、Ｎｉ、Ａｇ等の金属材料で形成される。各配線層１５ａ〜１５ｊ，１８ａ〜１８ｇは、単層構造であってもよいし積層構造であってもよい。   Each of the electrode layers 13 and 14 is formed on the surface of the substrate by sputtering or vapor deposition with a transparent conductive material such as ITO (Indium Tin Oxide). The base materials 32 and 33 are formed of a film-like transparent base material such as polyethylene terephthalate (PET) or a glass base material. Moreover, each wiring layer 15a-15j, 18a-18g is formed with metal materials, such as Cu, Cu alloy, CuNi alloy, Ni, and Ag. Each of the wiring layers 15a to 15j and 18a to 18g may have a single layer structure or a laminated structure.

図３に示すように、上部基材２１の上面側に粘着層３１を介して表面部材２０が接合されている。粘着層３０，３１は光学透明粘着層（ＯＣＡ）、両面粘着テープ等である。表面部材２０は特に材質を限定するものではないが、ガラスや透明なプラスチック等で形成される。表面部材２０の非入力領域１２の裏面には加飾層３４が形成されている。これにより、入力領域１１を透光性に、非入力領域１２を非透光性にできる。   As shown in FIG. 3, the surface member 20 is bonded to the upper surface side of the upper base member 21 via the adhesive layer 31. The adhesive layers 30 and 31 are an optical transparent adhesive layer (OCA), a double-sided adhesive tape, or the like. The surface member 20 is not particularly limited in material, but is formed of glass, transparent plastic, or the like. A decorative layer 34 is formed on the back surface of the non-input area 12 of the front surface member 20. Thereby, the input area 11 can be made translucent and the non-input area 12 can be made non-translucent.

図３に示すように指Ｆを入力領域１１の操作面２０ａ上に接触させると、指Ｆと、指Ｆに近い各電極層１３，１４の電極部４０，４２との間で静電容量が生じる。よって、指Ｆを操作面２０ａ上に接触させたときと接触させないときとで容量変化が生じる。そして、この容量変化に基づいて指Ｆの接触位置を算出することが可能である。なお、操作位置の検出方法は本実施形態以外のものであってもよい。   As shown in FIG. 3, when the finger F is brought into contact with the operation surface 20 a of the input area 11, the capacitance is generated between the finger F and the electrode portions 40 and 42 of the electrode layers 13 and 14 close to the finger F. Arise. Therefore, the capacitance changes between when the finger F is brought into contact with the operation surface 20a and when the finger F is not brought into contact therewith. Then, it is possible to calculate the contact position of the finger F based on this capacitance change. Note that the operation position detection method may be other than that of the present embodiment.

図４（ａ）は、図１に示すＸ１側非入力領域１２ａに配列された各配線層１５ａ〜１５ｅの部分拡大平面図である。図４（ａ）に示すように、各配線層１５ａ〜１５ｅは、各下部電極層１４の端部との接続位置に設けられた接続端部２３ａ〜２３ｅと、各接続端部２３ａ〜２３ｅからＹ１−Ｙ２方向に延出する配線延出部２４ａ〜２４ｅとを備えて構成される。   FIG. 4A is a partially enlarged plan view of the wiring layers 15a to 15e arranged in the X1 side non-input area 12a shown in FIG. As shown in FIG. 4A, each of the wiring layers 15a to 15e includes connection end portions 23a to 23e provided at connection positions with the end portions of the lower electrode layers 14, and connection end portions 23a to 23e. Wiring extending portions 24a to 24e extending in the Y1-Y2 direction are provided.

ここで各接続端部２３ａ〜２３ｅと各配線延出部２４ａ〜２４ｅとの境界であるが、図４の実施形態では、前記境界が段差部２３ａ１〜２３ｅ１で規定され、各配線層１５ａ〜１５ｅにおいて、前記段差部２３ａ１〜２３ｅ１よりもＹ１側が、接続端部２３ａ〜２３ｅ、前記段差部２３ａ１〜２３ｅ１よりもＹ２側が、配線延出部２４ａ〜２４ｅとして定義される。各接続端部２３ａ〜２３ｅは、各配線層１５ａ〜１５ｅの中で、最も配線幅が大きい領域を有している。なお接続端部２３ａ〜２３ｅと配線延出部２４ａ〜２４ｅとの境界をどこにするかは、配線層の形態等により適宜、設定することができる。各接続端部２３ａ〜２３ｅのＸ２側端部２３ａ２〜２３ｅ２は、Ｙ１−Ｙ２方向に直線形状で形成され、一列に並んでいる。配線層１５ｅの接続端部２３ｅは他の接続端部２３ａ〜２３ｄに比べて最も大きく形成され、また略矩形状で形成される。一方、接続端部２３ａ〜２３ｄは、Ｘ１側端部に傾斜面２３ａ３〜２３ｄ３を有しており、接続端部２３ｅとは異なる形状である。各接続端部２３ａ〜２３ｅの大きさは、接続端部２３ａ＜接続端部２３ｂ＜接続端部２３ｃ＜接続端部２３ｄ＜接続端部２３ｅの順となっている。   Here, it is a boundary between each connection end portion 23a to 23e and each wiring extension portion 24a to 24e. In the embodiment of FIG. 4, the boundary is defined by step portions 23a1 to 23e1, and each wiring layer 15a to 15e. The Y1 side of the step portions 23a1 to 23e1 is defined as the connection end portions 23a to 23e, and the Y2 side of the step portions 23a1 to 23e1 is defined as the wiring extension portions 24a to 24e. Each of the connection end portions 23a to 23e has a region having the largest wiring width among the wiring layers 15a to 15e. Note that where the boundaries between the connection end portions 23a to 23e and the wiring extension portions 24a to 24e can be set as appropriate depending on the form of the wiring layer and the like. The X2 side end portions 23a2 to 23e2 of the connection end portions 23a to 23e are formed in a linear shape in the Y1-Y2 direction, and are arranged in a line. The connection end portion 23e of the wiring layer 15e is formed to be the largest compared to the other connection end portions 23a to 23d, and is formed in a substantially rectangular shape. On the other hand, the connection end portions 23a to 23d have inclined surfaces 23a3 to 23d3 at the end portion on the X1 side, and have a shape different from that of the connection end portion 23e. The sizes of the connection end portions 23a to 23e are in the order of connection end portion 23a <connection end portion 23b <connection end portion 23c <connection end portion 23d <connection end portion 23e.

次に、配線延出部２４ａ〜２４ｅについて説明する。配線延出部２４ａ〜２４ｅは、配線層１５ａ〜１５ｅのうち、接続端部２３ａ〜２３ｅ及び図１に示す外部接続部２７以外の部分を指す。各配線延出部２４ａ〜２４ｅは、Ｘ１側非入力領域１２ａとＹ２側非入力領域１２ｂに引き回される。Ｘ１側非入力領域１２ａに形成される配線延出部２４ａ〜２４ｅの長さ寸法は、配線延出部２４ａ＜配線延出部２４ｂ＜配線延出部２４ｃ＜配線延出部２４ｄ＜配線延出部２４ｅの順となっている。   Next, the wiring extension parts 24a to 24e will be described. The wiring extension portions 24a to 24e indicate portions other than the connection end portions 23a to 23e and the external connection portion 27 illustrated in FIG. 1 in the wiring layers 15a to 15e. Each of the wiring extending portions 24a to 24e is routed to the X1 side non-input area 12a and the Y2 side non-input area 12b. The length dimension of the wiring extension parts 24a to 24e formed in the X1 side non-input area 12a is as follows: wiring extension part 24a <wiring extension part 24b <wiring extension part 24c <wiring extension part 24d <wiring extension The order is the part 24e.

本実施形態では、各配線延出部２４ａ〜２４ｅの配線幅（Ｘ１−Ｘ２方向における幅寸法）は、Ｘ１−Ｘ２方向にて並設される前記配線層の本数が少ない領域ほど、大きく形成される点に特徴的部分がある。   In this embodiment, the wiring width (width dimension in the X1-X2 direction) of each wiring extension part 24a-24e is formed so that it is so large that the area | region where the number of the said wiring layers arranged in parallel by the X1-X2 direction is few. There is a characteristic part in the point.

図４（ｂ）の各図は、図４（ａ）と対応する領域の各配線延出部２４ａ〜２４ｅの配線幅を図示したものである。図４（ｂ−５）の領域では、図４（ａ）に示すように、全ての配線延出部２４ａ〜２４ｅがＸ１−Ｘ２方向に所定の間隔を空けて並設されている。よって、図４（ｂ−５）に示す各配線延出部２４ａ〜２４ｅの領域では、各配線延出部２４ａ〜２４ｅの中で最も配線幅が小さく形成される。   Each drawing in FIG. 4B illustrates the wiring width of each wiring extension portion 24a to 24e in the region corresponding to FIG. 4A. In the region of FIG. 4B-5, as shown in FIG. 4A, all the wiring extending portions 24a to 24e are arranged in parallel at a predetermined interval in the X1-X2 direction. Therefore, in the area | region of each wiring extension part 24a-24e shown in FIG.4 (b-5), wiring width is formed smallest in each wiring extension part 24a-24e.

次に、図４（ｂ−５）に示す領域よりもＹ１側に位置する図４（ｂ−４）に示す領域では、図４（ａ）に示すように、配線延出部２４ａが形成されておらず、図４（ｂ−５）に示す領域よりも一本少ない配線延出部２４ｂ〜２４ｅがＸ１−Ｘ２方向に所定の間隔を空けて並設されている。よって、図４（ｂ−４）の領域における各配線延出部２４ｂ〜２４ｅの配線幅は、図４（ｂ−５）における各配線延出部２４ｂ〜２４ｅの配線幅よりも大きく形成される。   Next, in the region shown in FIG. 4 (b-4) located on the Y1 side from the region shown in FIG. 4 (b-5), a wiring extension 24a is formed as shown in FIG. 4 (a). However, the wiring extension portions 24b to 24e, which are one fewer than the region shown in FIG. 4B-5, are arranged in parallel at a predetermined interval in the X1-X2 direction. Therefore, the wiring width of each wiring extension part 24b-24e in the area | region of FIG.4 (b-4) is formed larger than the wiring width of each wiring extension part 24b-24e in FIG.4 (b-5). .

次に、図４（ｂ−４）に示す領域よりもＹ１側に位置する図４（ｂ−３）に示す領域では、図４（ａ）に示すように、配線延出部２４ａ，２４ｂが形成されておらず、図４（ｂ−４）に示す領域よりも一本少ない配線延出部２４ｃ〜２４ｅがＸ１−Ｘ２方向に所定の間隔を空けて並設されている。よって、図４（ｂ−３）の領域における各配線延出部２４ｃ〜２４ｅの配線幅は、図４（ｂ−４）における各配線延出部２４ｃ〜２４ｅの配線幅よりも大きく形成される。   Next, in the region shown in FIG. 4 (b-3) located on the Y1 side from the region shown in FIG. 4 (b-4), as shown in FIG. 4 (a), the wiring extension portions 24a and 24b are provided. The wiring extension portions 24c to 24e that are not formed and are one line smaller than the region shown in FIG. 4B-4 are arranged in parallel at a predetermined interval in the X1-X2 direction. Therefore, the wiring width of each wiring extension part 24c-24e in the area | region of FIG.4 (b-3) is formed larger than the wiring width of each wiring extension part 24c-24e in FIG.4 (b-4). .

次に、図４（ｂ−３）に示す領域よりもＹ１側に位置する図４（ｂ−２）に示す領域では、図４（ａ）に示すように、配線延出部２４ａ〜２４ｃが形成されておらず、図４（ｂ−３）よりも一本少ない配線延出部２４ｄ，２４ｅがＸ１−Ｘ２方向に所定の間隔を空けて並設されている。よって、図４（ｂ−２）の領域における各配線延出部２４ｄ，２４ｅの配線幅は、図４（ｂ−３）における各配線延出部２４ｄ，２４ｅの配線幅よりも大きく形成される。   Next, in the region shown in FIG. 4 (b-2) located on the Y1 side from the region shown in FIG. 4 (b-3), as shown in FIG. 4 (a), the wiring extension portions 24a to 24c are provided. The wiring extension portions 24d and 24e, which are not formed and are one fewer than in FIG. 4B-3, are arranged in parallel in the X1-X2 direction at a predetermined interval. Therefore, the wiring widths of the wiring extension portions 24d and 24e in the region of FIG. 4B-2 are formed larger than the wiring widths of the wiring extension portions 24d and 24e in FIG. 4B-3. .

次に、図４（ｂ−２）に示す領域よりもＹ１側に位置する図４（ｂ−１）に示す領域では、図４（ａ）に示すように、配線延出部２４ａ〜２４ｄが形成されておらず、配線延出部２４ｅのみがＸ１−Ｘ２方向に設けられる。よって、図４（ｂ−１）の領域における配線延出部２４ｅの配線幅は、図４（ｂ−２）における各配線延出部２４ｅの配線幅よりも大きく形成される。   Next, in the region shown in FIG. 4 (b-1) located on the Y1 side from the region shown in FIG. 4 (b-2), as shown in FIG. 4 (a), the wiring extending portions 24a to 24d are provided. Not formed, only the wiring extension 24e is provided in the X1-X2 direction. Therefore, the wiring width of the wiring extension portion 24e in the region of FIG. 4B-1 is formed larger than the wiring width of each wiring extension portion 24e in FIG. 4B-2.

よって、図４（ｂ−１）〜図４（ｂ−５）に示すように、配線延出部２４ｅの各領域での配線幅を見てみると、図４（ｂ−５）での幅寸法Ｔ５＜図４（ｂ−４）での幅寸法Ｔ４＜図４（ｂ−３）での幅寸法Ｔ３＜図４（ｂ−２）での幅寸法Ｔ２＜図４（ｂ−１）での幅寸法Ｔ１の順となっている。   Therefore, as shown in FIGS. 4B-1 to 4B-5, when the wiring width in each region of the wiring extension 24e is viewed, the width in FIG. 4B-5 is shown. Dimension T5 <Width dimension T4 in FIG. 4 (b-4) <Width dimension T3 in FIG. 4 (b-3) <Width dimension T2 in FIG. 4 (b-2) <In FIG. 4 (b-1) The width dimension T1 is in this order.

図４（ｂ−１）〜図４（ｂ−５）では、各領域において、Ｘ１−Ｘ２方向で並設される各配線延出部２４ａ〜２４ｅの配線幅は同じ幅寸法Ｔ２〜Ｔ５で形成されていたが、例えば、図４（ｃ−１）〜図４（ｃ−３）に示すように、各領域においてＸ１−Ｘ２方向で並設される各配線延出部２４ａ〜２４ｅの配線幅を異なる幅寸法で形成することも可能である。図４（ｃ−１）〜図４（ｃ−３）の各領域では、夫々、配線長さの長い配線延出部２４ｅ＞配線延出部２４ｄ・・の順に配線幅が大きくなるように調整している。   4 (b-1) to 4 (b-5), the wiring widths of the wiring extending portions 24a to 24e arranged in parallel in the X1-X2 direction in each region are formed with the same width dimensions T2 to T5. However, for example, as shown in FIGS. 4 (c-1) to 4 (c-3), the wiring widths of the wiring extending portions 24a to 24e arranged in parallel in the X1-X2 direction in each region. It is also possible to form with different width dimensions. 4 (c-1) to 4 (c-3), adjustment is made so that the wiring width increases in the order of the wiring extension portion 24e having a longer wiring length> the wiring extension portion 24d. doing.

このように本実施形態では、各配線延出部２４ａ〜２４ｅの配線幅を従来のように細い一定幅で形成するのでなく、並設される配線層の本数が少ない領域ほど、各配線延出部２４ａ〜２４ｅの配線幅を大きく形成した。よって、配線延出部の長さ寸法が長くても、並設される配線層の本数が少ない領域では、それだけ、配線幅を大きく形成することができるため、断線の確率を従来よりも効果的に低くすることが出来る。最も配線長さの長い配線延出部２４ｅを見てみると、図４（ｂ−５）から図４（ｂ−１）の各領域にかけて、徐々に配線幅を大きくすることができ、よって並設される配線層の本数に関わらず、配線幅を一律に細い幅で形成していた従来に比べて、配線延出部２４ｅにおける断線の確率を効果的に減少させることが可能である。   As described above, in the present embodiment, each wiring extension portion 24a to 24e is not formed with a thin constant width as in the prior art, but each wiring extension is provided in a region where the number of wiring layers arranged in parallel is small. The wiring widths of the portions 24a to 24e were increased. Therefore, even if the length of the wiring extension portion is long, the wiring width can be increased in an area where the number of wiring layers arranged in parallel is small, so the probability of disconnection is more effective than before. Can be lowered. Looking at the wiring extension portion 24e having the longest wiring length, the wiring width can be gradually increased from each region of FIG. 4 (b-5) to FIG. 4 (b-1). Regardless of the number of wiring layers provided, it is possible to effectively reduce the probability of disconnection in the wiring extension 24e as compared with the conventional case where the wiring width is uniformly narrow.

更に本実施形態では、各配線延出部の配線幅は、配線延出部の長さ寸法が長くなるほど、平均して大きく形成することができる。つまり配線延出部２４ａの配線幅（平均）＜配線延出部２４ｂの配線幅（平均）＜配線延出部２４ｃの配線幅（平均）＜配線延出部２４ｄの配線幅（平均）＜配線延出部２４ｅの配線幅（平均）の順にできる。よって各配線層１５ａ〜１５ｅの配線抵抗のばらつきを従来に比べて小さくすることが可能になる。   Furthermore, in this embodiment, the wiring width of each wiring extension part can be formed larger on average as the length dimension of the wiring extension part becomes longer. That is, the wiring width (average) of the wiring extension 24a <the wiring width (average) of the wiring extension 24b <the wiring width (average) of the wiring extension 24c <the wiring width (average) of the wiring extension 24d <wiring This can be done in the order of the wiring width (average) of the extending portion 24e. Therefore, it is possible to reduce the variation in the wiring resistance of each of the wiring layers 15a to 15e as compared with the conventional case.

また本実施形態では、配線延出部２４ｄを例にとると、配線延出部２４ｄには、Ｙ１−Ｙ２方向に向けて徐々にＸ１−Ｘ２方向の配線幅が変化する幅変化領域２４ｄ１〜２４ｄ３が形成されている。また幅変化領域２４ｄ１〜２４ｄ３には、Ｙ１−Ｙ２方向に平行に延出する幅一定領域が連続して接続されており、幅一定領域−幅変化領域２４ｄ１−幅一定領域−幅変化領域２４ｄ２−幅一定領域−幅変化領域２４ｄ３−幅一定領域の順に接続された形状となっている。図４（ａ）に示すように各幅変化領域２４ｄ１〜２４ｄ３は、幅一定領域から折れ曲がって形成されている。このように幅変化領域２４ｄ１〜２４ｄ３を折れ曲がるように形成することで、限られたＸ１側非入力領域１２ａ内に効率よく、複数本の配線延出部２４ａ〜２４ｅを配置することが可能である。なお幅変化領域について、配線延出部２４ｄを例にして説明したが、他の配線延出部２４ｂ〜２４ｅにつても同様に幅変化領域を設けることができる。ただし、配線延出部２４ａは、最も配線長さが短いうえ、Ｘ１側非入力領域１２ａでは常に全配線延出部と対向した位置関係にあるため、幅変化領域を形成して、更に、配線延出部２４ａの配線幅を細くすることが必要ではない。つまり、配線延出部２４ａについては一定の配線幅で形成することができる。最も外側に位置する配線延出部２４ｅにも、徐々に配線幅が変化する幅変化領域が形成されるが、幅一定領域から折れ曲がるように形成されておらず、配線延出部２４ｅのＸ１側端部２４ｅ１はＹ１−Ｙ２方向に直線的に延びる形状で形成されている。   Further, in this embodiment, taking the wiring extension 24d as an example, the wiring extension 24d has width change regions 24d1 to 24d3 in which the wiring width in the X1-X2 direction gradually changes in the Y1-Y2 direction. Is formed. Further, constant width regions extending in parallel with the Y1-Y2 direction are continuously connected to the width change regions 24d1 to 24d3, and the constant width region-width change region 24d1-constant width region-width change region 24d2- The shape is connected in the order of constant width region-width changing region 24d3-constant width region. As shown in FIG. 4A, each of the width change regions 24d1 to 24d3 is formed by being bent from a constant width region. By thus forming the width change regions 24d1 to 24d3 so as to be bent, it is possible to efficiently arrange a plurality of wiring extension portions 24a to 24e in the limited X1 side non-input region 12a. . The width change region has been described by taking the wiring extension portion 24d as an example, but the width change region can be similarly provided for the other wire extension portions 24b to 24e. However, the wiring extension portion 24a has the shortest wiring length and is always in a positional relationship facing the entire wiring extension portion in the X1 side non-input region 12a. It is not necessary to reduce the wiring width of the extending portion 24a. That is, the wiring extension portion 24a can be formed with a constant wiring width. A width change region in which the wiring width gradually changes is also formed in the outermost wiring extension portion 24e, but it is not formed so as to bend from the constant width region, and the X1 side of the wiring extension portion 24e. The end 24e1 is formed in a shape extending linearly in the Y1-Y2 direction.

また図４（ａ）に示すように、各幅変化領域２４ｄ１〜２４ｄ３における側端部２５のＹ１−Ｙ２方向に対する傾き角度θ１は、０°より大きく４５°以下であることが好適である。このような傾き角度θ１で幅変化領域を形成することで、特に製造方法における以下の効果を期待することができる。   Further, as shown in FIG. 4A, the inclination angle θ1 with respect to the Y1-Y2 direction of the side end portion 25 in each of the width change regions 24d1 to 24d3 is preferably greater than 0 ° and 45 ° or less. By forming the width change region at such an inclination angle θ1, the following effects in the manufacturing method can be expected.

図８は、本実施形態における下部基板２２における製造方法を示す一工程図である。図８（ａ）に示す工程では、下部基材３２上の全面にＩＴＯ等の透明導電層１６をスパッタ法や蒸着法等で形成する。更に、透明導電層１６の表面全面に金属材料層３５をスパッタ法や蒸着法等で形成する。   FIG. 8 is a process diagram showing a manufacturing method of the lower substrate 22 in the present embodiment. In the step shown in FIG. 8A, the transparent conductive layer 16 such as ITO is formed on the entire surface of the lower substrate 32 by sputtering or vapor deposition. Further, a metal material layer 35 is formed on the entire surface of the transparent conductive layer 16 by sputtering or vapor deposition.

次に図８（ｂ）の工程では、金属材料層３５の非入力領域１２の表面に、各配線層１５ａ〜１５ｊのパターンから成るレジスト層３６をフォトリソグラフィ技術により形成する。すなわち図４に示す配線層１５ａ〜１５ｅの平面パターンを備えるレジスト層３６を形成する。よってレジスト層３６には、図４（ａ）に示す傾き角度θ１を有して幅変化領域を形成する。このときの傾き角度θ１は、０°より大きく４５°以下であることが好適である。   Next, in the process of FIG. 8B, a resist layer 36 having a pattern of each of the wiring layers 15a to 15j is formed on the surface of the non-input region 12 of the metal material layer 35 by a photolithography technique. That is, a resist layer 36 having a planar pattern of the wiring layers 15a to 15e shown in FIG. 4 is formed. Therefore, a width change region is formed in the resist layer 36 with the inclination angle θ1 shown in FIG. The tilt angle θ1 at this time is preferably greater than 0 ° and not greater than 45 °.

そして前記レジスト層３６に覆われていない金属材料層３５を例えばウエットエッチングにより除去する。このとき、０°よりも大きく４５°以下の傾き角度θ１を有して幅変化領域の側部を形成することで、幅一定領域から幅変化領域にかけてのコーナー部分（例えば図４（ａ）の符号Ａの部分）が直角にならず、なだらかに傾きが変化するため、前記コーナー部分にエッチング液の液溜りができるのを抑制できる。したがって各配線層１５ａ〜１５ｅの配線延出部２４ａ〜２４ｅを所定の配線幅にて適切に形成することができる。   Then, the metal material layer 35 not covered with the resist layer 36 is removed by, for example, wet etching. At this time, by forming the side portion of the width change region with an inclination angle θ1 of greater than 0 ° and 45 ° or less, a corner portion (for example, as shown in FIG. 4A) from the constant width region to the width change region is formed. The portion A) does not form a right angle and the inclination changes gently, so that it is possible to suppress the accumulation of the etching solution in the corner portion. Therefore, the wiring extending portions 24a to 24e of the wiring layers 15a to 15e can be appropriately formed with a predetermined wiring width.

図８（ｃ）の工程では、各配線層１５（図８（ｃ）では統一して符号１５で示した）上から透明導電層１６上にかけてレジスト層３７を形成する。前記レジスト層３７を、フォトリソグラフィ技術により、入力領域１１では、各下部電極層１４と同じ電極パターンにて形成し、更に前記電極パターンに連続して非入力領域１２では、各配線層１５上を覆う配線パターンにて形成する。そして前記レジスト層３７に覆われていない透明導電層１６を除去する。これにより、入力領域１１には、図１に示す各下部電極層１４を形成でき、非入力領域１２では、各配線層１５の下に透明導電層１６を残すことができる。上記した製造方法を用いて上部基板２１も形成することが可能である。なお上記した製造方法はあくまでも一例であり、他の製造方法により各基板２１，２２を形成することが可能である。   In the step of FIG. 8C, a resist layer 37 is formed from above each wiring layer 15 (indicated by reference numeral 15 in FIG. 8C) to the transparent conductive layer 16. The resist layer 37 is formed with the same electrode pattern as that of each lower electrode layer 14 in the input region 11 by a photolithography technique, and further on each wiring layer 15 in the non-input region 12 continuously to the electrode pattern. The wiring pattern is covered. Then, the transparent conductive layer 16 not covered with the resist layer 37 is removed. Thereby, each lower electrode layer 14 shown in FIG. 1 can be formed in the input region 11, and the transparent conductive layer 16 can be left under each wiring layer 15 in the non-input region 12. The upper substrate 21 can also be formed using the manufacturing method described above. The manufacturing method described above is merely an example, and the substrates 21 and 22 can be formed by other manufacturing methods.

なお各配線層をスクリーン印刷、グラビア印刷、インクジェット印刷等の印刷法で形成することもできる。また、配線層としては、Ａｇペースト、Ａｇナノ材料、Ｃｕナノ材料等を用いることができる。   Each wiring layer can also be formed by a printing method such as screen printing, gravure printing, or ink jet printing. As the wiring layer, Ag paste, Ag nanomaterial, Cu nanomaterial, or the like can be used.

なお、図４に示す配線構造は、下部基板２２のみならず上部基板２１にも適用することが可能である。図２に示すように上部基板２１の配線層１８ａ〜１８ｇは、Ｙ１−Ｙ２方向にて並設される配線層の本数がＸ１−Ｘ２方向に向けて変化している。よって、各配線層１８ａ〜１８ｇのＸ１−Ｘ２方向に延びる配線延出部の配線幅（Ｙ１−Ｙ２方向の幅寸法）を、Ｙ１−Ｙ２方向にて並設される配線層の本数が少ない領域ほど大きく形成することが可能である。   Note that the wiring structure shown in FIG. 4 can be applied not only to the lower substrate 22 but also to the upper substrate 21. As shown in FIG. 2, in the wiring layers 18a to 18g of the upper substrate 21, the number of wiring layers arranged in parallel in the Y1-Y2 direction changes in the X1-X2 direction. Therefore, a region in which the wiring width (width dimension in the Y1-Y2 direction) of the wiring extension portion extending in the X1-X2 direction of each wiring layer 18a-18g is small in the number of wiring layers arranged in parallel in the Y1-Y2 direction. It can be formed as large as possible.

図３では、下部基板２２の下部電極層１４及び上部基板２１の上部電極層１３を全て操作面２０ａ側に向けた状態で、下部基板２２と上部基板２１間が粘着層３０を介して接合されているが、図５のように、下部基板２２の下部電極層１４を操作面２０ａ側に向けて、上部基板２１の上部電極層１３を、操作面２０ａ側とは逆側に向けた状態にして、下部基板２２と上部基板２１間が粘着層３０を介して接合されていてもよいし、あるいは、図６に示すように、一つの基材３８の上下面に下部電極層１４及び上部電極層１３が形成された形態としてもよい。   In FIG. 3, the lower substrate 22 and the upper substrate 21 are bonded via the adhesive layer 30 with the lower electrode layer 14 of the lower substrate 22 and the upper electrode layer 13 of the upper substrate 21 all directed toward the operation surface 20a. However, as shown in FIG. 5, the lower electrode layer 14 of the lower substrate 22 faces the operation surface 20a, and the upper electrode layer 13 of the upper substrate 21 faces the operation surface 20a. The lower substrate 22 and the upper substrate 21 may be bonded via the adhesive layer 30. Alternatively, as shown in FIG. 6, the lower electrode layer 14 and the upper electrode are formed on the upper and lower surfaces of one substrate 38. A form in which the layer 13 is formed may be employed.

または、図７（ａ）（ｂ）に示す構成であってもよい。図７（ａ）は部分平面図であるが（ｂ）に示す絶縁層等を省略した。また図７（ｂ）は図７（ａ）のＡ−Ａ線に沿って切断し矢印方向から見た部分縦断面図である。図７（ａ）（ｂ）では、一つの基材３８の表面に複数の電極層５０，５１を配列し、このうち電極層５０をＸ方向に向けて接続するとともに、電極層５０の連結部５２上を絶縁層５３で覆う。そして、絶縁層５３上に各電極層５１を接続するための連結部５４を形成し、連結部５４を介して各電極層５１をＹ方向に繋げている。図７の構成では、同じ基材３８の同じ表面に、Ｘ方向に繋がる電極層５０とＹ方向に繋がる電極層５１とが形成されている。   Or the structure shown to Fig.7 (a) (b) may be sufficient. FIG. 7A is a partial plan view, but the insulating layer and the like shown in FIG. 7B are omitted. FIG. 7B is a partial longitudinal sectional view taken along the line AA in FIG. 7 (a) and 7 (b), a plurality of electrode layers 50 and 51 are arranged on the surface of a single substrate 38, and the electrode layer 50 is connected in the X direction, and the connecting portion of the electrode layer 50 is connected. 52 is covered with an insulating layer 53. And the connection part 54 for connecting each electrode layer 51 on the insulating layer 53 is formed, and each electrode layer 51 is connected to the Y direction via the connection part 54. In the configuration of FIG. 7, an electrode layer 50 connected in the X direction and an electrode layer 51 connected in the Y direction are formed on the same surface of the same base material 38.

上記実施形態では、静電容量式の入力装置を用いて説明したが、本実施形態における配線構造は、静電容量式以外の、例えば、マルチタッチ方式の抵抗式入力装置にも適用できる。   In the embodiment described above, the capacitance type input device has been described. However, the wiring structure in the present embodiment can be applied to, for example, a multi-touch type resistance input device other than the capacitance type.

本実施形態における入力装置は、携帯電話機、デジタルカメラ、ＰＤＡ、ゲーム機、カーナビゲーション等に使用される。   The input device in this embodiment is used for a mobile phone, a digital camera, a PDA, a game machine, a car navigation system, and the like.

１１ 入力領域
１２、１２ａ〜１２ｃ 非入力領域
１３ 上部電極層
１４ 下部電極層
１５、１５ａ〜１５ｊ、１８ａ〜１８ｇ 配線層
２１ 上部基板
２２ 下部基板
２３ａ〜２３ｅ 接続端部
２４ａ〜２４ｅ 配線延出部
３６、３７ レジスト層
２４ｄ１〜２４ｄ３ 幅変化領域
５０、５１ 電極層11 Input region 12, 12a-12c Non-input region 13 Upper electrode layer 14 Lower electrode layer 15, 15a-15j, 18a-18g Wiring layer 21 Upper substrate 22 Lower substrates 23a-23e Connection end portions 24a-24e Wiring extension portion 36 37 Resist layers 24d1-24d3 Width changing regions 50, 51 Electrode layer

本発明における入力装置は、
入力領域に設けられた電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有し、
前記配線層は、前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備え、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部が、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出しているとともに、各配線延出部の配線幅は、前記第１の方向にて並設される前記配線層の本数が少ない領域ほど、大きく形成されており、
前記配線延出部には、前記第２の方向に向けて徐々に配線幅が変化する幅変化領域が形成されていることを特徴とするものである。 The input device in the present invention is
Having an electrode layer provided in the input region and a wiring layer routed in a non-input region outside the input region;
The wiring layer includes a connection end portion provided at a connection position with the end portion of the electrode layer, and a wiring extension portion led out from the connection end portion,
When two directions orthogonal to each other in the plane are defined as a first direction and a second direction, the wiring extension portions in the plurality of wiring layers are each non-input on the same side as viewed from the input region. The wiring layer that extends in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is arranged in parallel in the first direction more regions the number of small, are larger,
The wiring extension portion is formed with a width change region in which the wiring width gradually changes in the second direction .

また本発明は、入力領域に設けられた電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有して成る入力装置の製造方法において、
前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備える前記配線層をエッチングにて所定形状に形成し、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部を、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出させるとともに、各配線延出部の配線幅を、前記第１の方向にて並設される前記配線層の本数が少ないほど、大きく形成するとともに、前記配線延出部に、前記第２の方向に向けて徐々に配線幅が変化する幅変化領域を形成することを特徴とするものである。 Further, the present invention provides an input device manufacturing method comprising an electrode layer provided in an input region and a wiring layer routed in a non-input region outside the input region.
Forming the wiring layer comprising a connection end provided at a connection position with the end of the electrode layer and a wiring extension extending from the connection end into a predetermined shape by etching ;
When the two directions orthogonal to each other in the plane are defined as the first direction and the second direction, the non-inputs on the same side as viewed from the input region, the wiring extension portions in the plurality of wiring layers, respectively. The wiring layer is extended in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is set to be parallel to the first direction. The smaller the number, the larger and the width extension region in which the wiring width gradually changes in the second direction is formed in the wiring extension portion .

また前記幅変化領域における側端部の前記第２の方向に対する傾き角度θ１は４５°以下であることが好ましい。更に、前記配線延出部は、前記第２の方向に向けて、前記幅変化領域と、前記第２の方向に平行に延びる配線幅が一定の幅一定領域とが交互に繰り返して形成されており、前記幅変化領域は前記幅一定領域から折れ曲がって形成されていることが好ましい。
また本発明では、前記各配線延出部における前記幅一定領域の配線幅は、前記第１の方向にて並設される前記配線層の本数が同じ各領域にて、同じ幅寸法で形成されることが好ましい。 Tilt angle θ1 with respect to the second direction side end portion in the width change region was or is preferably 45 ° or less. Further, the wiring extension portion is formed by alternately repeating the width changing region and a constant width region extending in parallel to the second direction toward the second direction. The width change region is preferably bent from the constant width region.
In the present invention, the wiring width of the constant width region in each wiring extension portion is formed with the same width dimension in each region where the number of the wiring layers arranged in parallel in the first direction is the same. It is preferable.

Claims (8)

入力領域に設けられた電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有し、
前記配線層は、前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備え、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部が、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出しているとともに、各配線延出部の配線幅は、前記第１の方向にて並設される前記配線層の本数が少ない領域ほど、大きく形成されていることを特徴とする入力装置。Having an electrode layer provided in the input region and a wiring layer routed in a non-input region outside the input region;
The wiring layer includes a connection end portion provided at a connection position with the end portion of the electrode layer, and a wiring extension portion led out from the connection end portion,
When two directions orthogonal to each other in the plane are defined as a first direction and a second direction, the wiring extension portions in the plurality of wiring layers are each non-input on the same side as viewed from the input region. The wiring layer that extends in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is arranged in parallel in the first direction An input device characterized in that a region having a smaller number of is formed larger. 前記配線延出部には、前記第２の方向に向けて徐々に配線幅が変化する幅変化領域が形成されている請求項１記載の入力装置。   The input device according to claim 1, wherein a width change region in which a wiring width gradually changes in the second direction is formed in the wiring extension portion. 前記幅変化領域における側端部の前記第２の方向に対する傾き角度θ１は４５°以下である請求項２記載の入力装置。   The input device according to claim 2, wherein an inclination angle θ <b> 1 of the side end portion in the width change region with respect to the second direction is 45 ° or less. 前記配線延出部は、前記第２の方向に向けて、前記幅変化領域と、前記第２の方向に平行に延びる配線幅が一定の幅一定領域とが交互に繰り返して形成されており、前記幅変化領域は前記幅一定領域から折れ曲がって形成されている請求項２または３に記載の入力装置。   The wiring extension portion is formed by alternately repeating the width change region and the constant width region extending in parallel with the second direction toward the second direction, The input device according to claim 2, wherein the width change region is formed by being bent from the constant width region. 入力領域に設けられた電極層と、入力領域の外側の非入力領域にて引き回された配線層とを有して成る入力装置の製造方法において、
前記電極層の端部との接続位置に設けられた接続端部と、前記接続端部から引き出された配線延出部とを備える前記配線層を形成し、
平面内にて直交する２方向を第１の方向と第２の方向としたとき、複数本の前記配線層における前記配線延出部を、夫々、前記入力領域から見て同じ側の前記非入力領域で前記第１の方向に間隔を空けた状態で前記第２の方向に延出させるとともに、各配線延出部の配線幅を、前記第１の方向にて並設される前記配線層の本数が少ないほど、大きく形成することを特徴とする入力装置の製造方法。In an input device manufacturing method comprising an electrode layer provided in an input region and a wiring layer routed in a non-input region outside the input region,
Forming the wiring layer comprising a connection end provided at a connection position with the end of the electrode layer, and a wiring extension drawn from the connection end;
When the two directions orthogonal to each other in the plane are defined as the first direction and the second direction, the non-inputs on the same side as viewed from the input region, the wiring extension portions in the plurality of wiring layers, respectively. The wiring layer is extended in the second direction with a space in the first direction in the region, and the wiring width of each wiring extension portion is set to be parallel to the first direction. A method for manufacturing an input device, characterized in that the smaller the number, the larger the number. 前記配線層をエッチングにて所定形状に形成し、この際、前記配線延出部に、前記第２の方向に向けて徐々に配線幅が変化する幅変化領域を形成する請求項５記載の入力装置の製造方法。   6. The input according to claim 5, wherein the wiring layer is formed into a predetermined shape by etching, and at this time, a width changing region in which the wiring width gradually changes in the second direction is formed in the wiring extension portion. Device manufacturing method. 前記幅変化領域における側端部の前記第２の方向に対する傾き角度θ１を４５°以下に設定する請求項６記載の入力装置の製造方法。   The manufacturing method of the input device according to claim 6, wherein an inclination angle θ <b> 1 of the side end portion in the width change region with respect to the second direction is set to 45 ° or less. 前記配線延出部を、前記第２の方向に向けて、前記幅変化領域と、前記第２の方向に平行に延びる配線幅が一定の幅一定領域とを交互に繰り返して形成し、このとき、前記幅変化領域を前記幅一定領域から折れ曲がるように形成する請求項６または７に記載の入力装置の製造方法。   The wiring extension portion is formed by alternately repeating the width change region and the constant width region extending in parallel to the second direction in the second direction. The method of manufacturing an input device according to claim 6, wherein the width change region is formed to be bent from the constant width region.
JP2011551369A 2010-07-22 2011-07-06 Input device and manufacturing method thereof Active JP4963524B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011551369A JP4963524B2 (en) 2010-07-22 2011-07-06 Input device and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2010164642 2010-07-22
JP2010164642 2010-07-22
JP2011551369A JP4963524B2 (en) 2010-07-22 2011-07-06 Input device and manufacturing method thereof
PCT/JP2011/065513 WO2012011390A1 (en) 2010-07-22 2011-07-06 Input device and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011272516A Division JP5255111B2 (en) 2010-07-22 2011-12-13 Input device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP4963524B2 JP4963524B2 (en) 2012-06-27
JPWO2012011390A1 true JPWO2012011390A1 (en) 2013-09-09

Family

ID=45496817

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2011551369A Active JP4963524B2 (en) 2010-07-22 2011-07-06 Input device and manufacturing method thereof
JP2011272516A Active JP5255111B2 (en) 2010-07-22 2011-12-13 Input device and manufacturing method thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011272516A Active JP5255111B2 (en) 2010-07-22 2011-12-13 Input device and manufacturing method thereof

Country Status (4)

Country Link
JP (2) JP4963524B2 (en)
KR (3) KR101333000B1 (en)
CN (3) CN102844730B (en)
WO (1) WO2012011390A1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101737963B1 (en) * 2012-03-15 2017-05-19 후지필름 가부시키가이샤 Photosensitive film, method for producing capacitance type input device, capacitance type input device, and image display apparatus using the same
JP5991709B2 (en) 2012-05-01 2016-09-14 株式会社ジャパンディスプレイ LCD with built-in touch panel
JP2014128925A (en) * 2012-12-28 2014-07-10 Dic Corp Gravure offset printing method
KR101725033B1 (en) * 2013-07-31 2017-04-10 엘지디스플레이 주식회사 Display Device Integrated With Touch Screen and Method for Driving The Same
US20150060120A1 (en) * 2013-08-29 2015-03-05 Samsung Electro-Mechanics Co., Ltd. Touch panel
CN105204671A (en) * 2014-05-27 2015-12-30 宸鸿科技(厦门)有限公司 Touch panel and manufacturing method
KR102281850B1 (en) * 2015-02-25 2021-07-26 삼성디스플레이 주식회사 Touch sensor, manufacturing method thereof and display device including the same
CN105446533B (en) * 2015-11-19 2018-08-31 业成光电（深圳）有限公司 The line construction of touch panel
CN108139826A (en) * 2015-12-25 2018-06-08 株式会社藤仓 With wire body, wiring substrate and touch sensor
CN106066740B (en) * 2016-08-02 2019-02-12 厦门天马微电子有限公司 Touch-control display panel and touch control display apparatus
JP6240278B2 (en) * 2016-08-10 2017-11-29 株式会社ジャパンディスプレイ LCD with built-in touch panel
JPWO2018225633A1 (en) * 2017-06-06 2020-04-09 パナソニックＩｐマネジメント株式会社 Components for touch panel sensor
JP6410908B2 (en) * 2017-11-02 2018-10-24 株式会社ジャパンディスプレイ LCD with built-in touch panel
JP7101213B2 (en) * 2020-08-06 2022-07-14 グンゼ株式会社 Capacitive touch panel

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173239A (en) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd Wiring substrate, its manufacturing method, and electronic equipment using the same
JP5260912B2 (en) * 2007-07-31 2013-08-14 パナソニック液晶ディスプレイ株式会社 Display device
JP4582169B2 (en) * 2008-03-26 2010-11-17 ソニー株式会社 Capacitance type input device, display device with input function, and electronic device
JP5103254B2 (en) * 2008-04-16 2012-12-19 株式会社ジャパンディスプレイイースト Capacitive touch panel and screen input type display device including the same
JP2010061384A (en) * 2008-09-03 2010-03-18 Rohm Co Ltd Input device and portable information processor using the same
US8269744B2 (en) * 2008-09-05 2012-09-18 Mitsubishi Electric Corporation Touch screen, touch panel and display device
CN101510383B (en) * 2009-03-26 2011-12-07 友达光电股份有限公司 Flat display panel

Also Published As

Publication number Publication date
CN102844730B (en) 2015-04-01
KR101333000B1 (en) 2013-11-25
KR20130058062A (en) 2013-06-03
JP5255111B2 (en) 2013-08-07
CN102844730A (en) 2012-12-26
KR20120116464A (en) 2012-10-22
JP2012053924A (en) 2012-03-15
JP4963524B2 (en) 2012-06-27
KR20120123394A (en) 2012-11-08
CN103324369A (en) 2013-09-25
CN103324369B (en) 2016-02-10
KR101318610B1 (en) 2013-10-15
WO2012011390A1 (en) 2012-01-26
CN103076913B (en) 2016-01-20
CN103076913A (en) 2013-05-01

Similar Documents

Publication Publication Date Title
JP4963524B2 (en) Input device and manufacturing method thereof
US8209861B2 (en) Method for manufacturing a touch screen sensor assembly
JP5520162B2 (en) Input device and manufacturing method thereof
CN105302398A (en) Touch input device and electrode sheet
US20150060120A1 (en) Touch panel
US20150234495A1 (en) Single layer solution touch panel
KR102262530B1 (en) Touch window and display with the same
JP6311129B2 (en) Touch panel
JP2013164698A (en) Input apparatus
JP5846953B2 (en) Input device and manufacturing method thereof
TWI630517B (en) Touch window and touch device including the same
JP2015049888A (en) Touch panel
JP2015032315A (en) Touch sensor
KR101386333B1 (en) Input device and method for manufacturing the same
KR102262553B1 (en) Touch panel
TW201512943A (en) Touch sensing electrode
US9342171B2 (en) Touch panel with first and second electrodes extending in the same direction but on opposite surfaces of a substrate
JP6134968B2 (en) Display device
JP2013164827A (en) Input apparatus
US20150103261A1 (en) Touch panel and manufacturing method thereof
KR20150031805A (en) Touch Panel
JP3163718U (en) Capacitive touch sensor
JP2011186977A (en) Manufacturing method of input device
KR102303069B1 (en) Touch window
JP2015153400A (en) Method for manufacturing input device

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120321

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120323

R150 Certificate of patent or registration of utility model

Ref document number: 4963524

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150406

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350