JPWO2011138906A1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JPWO2011138906A1
JPWO2011138906A1 JP2012513787A JP2012513787A JPWO2011138906A1 JP WO2011138906 A1 JPWO2011138906 A1 JP WO2011138906A1 JP 2012513787 A JP2012513787 A JP 2012513787A JP 2012513787 A JP2012513787 A JP 2012513787A JP WO2011138906 A1 JPWO2011138906 A1 JP WO2011138906A1
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semiconductor device
manufacturing
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大見　忠弘
忠弘 大見
耕平 綿貫
耕平 綿貫
信之 真鍋
信之 真鍋
鈴木　宏和
宏和 鈴木
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Tohoku University NUC
Ube-Nitto Kasei Co Ltd
Ube Corp
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Ube Industries Ltd
Ube-Nitto Kasei Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

素子分離領域を備えた半導体装置の製造方法は、半導体基板に前記素子分離領域を形成するためのシャロートレンチを形成する工程と、前記シャロートレンチを含む前記半導体基板上に、塗布液を塗布する工程と、前記塗布された塗布膜を素子分離用絶縁物に改質する工程とを含む。前記塗布液は、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物の一種又は二種以上および溶媒を含んで構成される。前記改質する工程は、前記塗布膜を酸化性雰囲気中で、かつ１０Ｔｏｒｒ乃至２００Ｔｏｒｒの減圧下で、熱処理することによってＳｉＯ２膜に改質する工程を有する。改質工程では、粒状化及び／又はボイドの発生のないＳｉＯ２膜に改質する。A method of manufacturing a semiconductor device having an element isolation region includes a step of forming a shallow trench for forming the element isolation region in a semiconductor substrate, and a step of applying a coating liquid on the semiconductor substrate including the shallow trench. And a step of modifying the applied coating film into an element isolation insulator. The coating solution is one or two of the compositions represented by the general formula ((CH3) nSiO2-n / 2) x (SiO2) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0). It is composed of more than one species and a solvent. The step of modifying includes a step of modifying the coating film to an SiO 2 film by performing a heat treatment in an oxidizing atmosphere and under a reduced pressure of 10 Torr to 200 Torr. In the reforming process, the SiO2 film is free of granulation and / or voids.

Description

本発明は、半導体装置に関し、特に、シャロートレンチアイソレイション（以下、ＳＴＩと略称する）構造を備えた半導体装置の製造方法に関する。   The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a shallow trench isolation (hereinafter abbreviated as STI) structure.

ＳＴＩ構造を備えた半導体装置は、半導体基板の表面に設けられたシャロートレンチ（浅溝）内に、絶縁膜からなる素子分離領域を形成し、素子分離領域で互いに分離された複数の素子形成領域に半導体素子を形成してなるものである。このような半導体装置の製造においては、ＣＭＰ(chemical-mechanical polishing)工程を経ることが従来必須であった。すなわち、ＳＴＩ構造形成においてはシャロートレンチを含む半導体基板上に絶縁膜を成膜するが、トレンチの凹凸が絶縁膜表面に現れるため、絶縁膜表面をＣＭＰによって平坦にして、シャロートレンチ内のみに絶縁膜が残るようにして素子分離領域を形成する手法が採用されている。しかしながら、ＣＭＰ工程はエッチング等に比較してコストの高い工程であるため、ＣＭＰの実施は半導体装置のコスト上昇の一因ともなっている。   In a semiconductor device having an STI structure, an element isolation region made of an insulating film is formed in a shallow trench provided on the surface of a semiconductor substrate, and a plurality of element formation regions separated from each other in the element isolation region A semiconductor element is formed on the substrate. In the manufacture of such a semiconductor device, it has heretofore been essential to go through a chemical-mechanical polishing (CMP) process. That is, in the formation of the STI structure, an insulating film is formed on a semiconductor substrate including a shallow trench, but since the irregularities of the trench appear on the surface of the insulating film, the insulating film surface is flattened by CMP and insulated only within the shallow trench. A method of forming an element isolation region so as to leave a film is employed. However, since the CMP process is a costly process compared to etching or the like, the implementation of CMP also contributes to an increase in the cost of the semiconductor device.

特許文献１は、ＳＴＩ溝内を絶縁膜で埋め込むプロセスとして、シリコン基板に平坦化塗布膜を塗布し、それを熱処理でＳｉＯ２膜に改質することで、表面が平坦でかつＳＴＩ溝内を素子分離用ＳｉＯ２膜で埋め込むプロセスを開示している。この方法によればＣＭＰ工程を不要にすることができる。In Patent Document 1, as a process of embedding an STI trench with an insulating film, a flattening coating film is applied to a silicon substrate, and it is reformed to a SiO 2 film by heat treatment, so that the surface is flat and the inside of the STI trench is filled. A process of embedding with an element isolation SiO 2 film is disclosed. According to this method, the CMP process can be eliminated.

国際公開 ＷＯ 2009/022719号公報International Publication WO 2009/022719

特許文献１では、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物一種又は二種以上と溶媒とで構成される塗布膜を用い、シャロートレンチを埋めるように該塗布液を塗布し、この塗布膜を８００℃乃至９００℃で焼成してＳｉＯ２に改質することによって素子分離領域を形成することが開示されている。In Patent Document 1, a composition represented by the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0). Using a coating film composed of one or more types and a solvent, applying the coating solution so as to fill the shallow trench, and baking the coating film at 800 ° C. to 900 ° C. to modify it to SiO 2 To form an element isolation region.

しかしながら、本発明者等が見出した知見によれば、特許文献１の素子分離領域におけるＳｉＯ２層は、粒状になったり（粒状化）、ボイドが生じるという問題がある。このような不均質なＳｉＯ２層は、半導体デバイスの素子間のリーク電流を招き、素子分離に支障が生じることが懸念されとともに、製造プロセス面では平坦化プロセスで素子分離領域を平坦化できない懸念がある。However, according to the knowledge found by the present inventors, there is a problem that the SiO 2 layer in the element isolation region of Patent Document 1 becomes granular (granulated) or a void occurs. Such a heterogeneous SiO 2 layer may cause a leakage current between elements of a semiconductor device, causing troubles in element isolation, and in terms of manufacturing process, the element isolation region may not be flattened by a flattening process. There is.

そこで、本発明の技術的課題は、上記のプロセスにおいて、シャロートレンチを埋める絶縁膜が粒状になること（粒状化）がなく、ボイドが生じることがない半導体装置の製造方法を提供することにある。   Therefore, a technical problem of the present invention is to provide a method for manufacturing a semiconductor device in which the insulating film filling the shallow trench does not become granular (granulation) and no voids are generated in the above process. .

本発明によれば、素子分離領域を備えた半導体装置の製造方法において、半導体基板に前記素子分離領域を形成するためのシャロートレンチを形成する工程と、前記シャロートレンチを含む前記半導体基板上に、塗布液を塗布する工程と、前記塗布された塗布膜を素子分離用絶縁物に改質する工程とを含み、
前記塗布液は、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦x≦１．０）で示される組成物の一種又は二種以上および溶媒を含んで構成され、前記改質する工程は、前記塗布膜を酸化性雰囲気中で、かつ１０Ｔｏｒｒ乃至２００Ｔｏｒｒの減圧下で、熱処理することによってＳｉＯ２膜に改質する工程であることを特徴とする半導体装置の製造方法が得られる。According to the present invention, in a method of manufacturing a semiconductor device having an element isolation region, a step of forming a shallow trench for forming the element isolation region in a semiconductor substrate, and on the semiconductor substrate including the shallow trench, A step of applying a coating solution, and a step of modifying the applied coating film into an element isolation insulator,
The coating solution is a composition represented by the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0). In the step of modifying the coating film, the coating film is modified into a SiO 2 film by heat-treating the coating film in an oxidizing atmosphere and under a reduced pressure of 10 Torr to 200 Torr. Thus, a method for manufacturing a semiconductor device can be obtained.

また、本発明によれば、前記半導体装置の製造方法において、前記熱処理は８００℃乃至９００℃の温度で行われることを特徴とする半導体装置の製造方法が得られる。   According to the present invention, in the method of manufacturing a semiconductor device, the semiconductor device manufacturing method is characterized in that the heat treatment is performed at a temperature of 800 ° C. to 900 ° C.

また、本発明によれば、前記半導体装置の製造方法において、前記酸化性雰囲気が少なくとも水蒸気ガスを含むことを特徴とする半導体装置の製造方法が得られる。   According to the present invention, in the method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device is characterized in that the oxidizing atmosphere contains at least a water vapor gas.

また、本発明によれば、前記半導体装置の製造方法において、更に、前記改質されたＳｉＯ２膜を、ＣＭＰを施すことなく、表面を半導体基板表面と同等の高さにする工程を含むことを特徴とする半導体装置の製造方法が得られる。According to the invention, the method for manufacturing a semiconductor device further includes a step of making the surface of the modified SiO 2 film equal to the surface of the semiconductor substrate without performing CMP. A method for manufacturing a semiconductor device characterized by the above is obtained.

また、本発明によれば、前記半導体装置の製造方法において、前記表面を半導体基板表面と同等の高さにする工程は、エッチング工程であることを特徴とする半導体装置の製造方法が得られる。   According to the present invention, in the method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device is characterized in that the step of making the surface the same height as the surface of the semiconductor substrate is an etching step.

また、本発明によれば、前記半導体装置の製造方法において、前記素子分離領域によって画成された前記半導体基板の素子形成領域にソース領域およびドレイン領域を形成する工程および前記素子形成領域上にゲート絶縁膜を介してゲート電極を形成する工程を含むことを特徴とする半導体装置の製造方法が得られる。   According to the invention, in the method of manufacturing a semiconductor device, a step of forming a source region and a drain region in an element formation region of the semiconductor substrate defined by the element isolation region, and a gate on the element formation region A method for manufacturing a semiconductor device is provided, which includes a step of forming a gate electrode through an insulating film.

また、本発明によれば、前記半導体装置の製造方法において、前記塗布液を塗布する工程は、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０．５≦ｘ≦０．９）で示される組成物一種又は二種以上および溶媒で構成される塗布液を用いることを特徴とする半導体装置の製造方法が得られる。According to the invention, in the method for manufacturing a semiconductor device, the step of applying the coating liquid may be performed by using the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (provided that , N = 1 to 3, 0.5 ≦ x ≦ 0.9), a coating liquid composed of one or more kinds of compositions and a solvent is obtained. .

また、本発明によれば、前記塗布液における前記組成物の濃度を、５重量％乃至２０重量％とすることを特徴とする半導体装置の製造方法が得られる。   In addition, according to the present invention, there is obtained a method for manufacturing a semiconductor device, wherein the concentration of the composition in the coating solution is 5 wt% to 20 wt%.

本発明においては、前記組成物のｘの値は、前記一般式で示される組成物の塗布液中での均一性の点で０．６乃至０．８が好ましく、特に０．７前後が好ましく、塗布液における組成物の濃度は１０重量％前後が特に好ましい。また、塗布液を酸化性雰囲気で熱処理する際の減圧力は２０Ｔｏｒｒ乃至５０Ｔｏｒｒが特に好ましい。酸化性雰囲気とするために、酸素ガスと水蒸気ガスとの混合ガスを流すのが好ましい。前記酸化性雰囲気とするための混合ガスは水蒸気ガスが５容積％の割合以上の割合で流入するのが特に好ましい。   In the present invention, the value of x of the composition is preferably 0.6 to 0.8, particularly preferably about 0.7 in terms of uniformity in the coating solution of the composition represented by the general formula. The concentration of the composition in the coating solution is particularly preferably around 10% by weight. Further, the decompression force when the coating solution is heat-treated in an oxidizing atmosphere is particularly preferably 20 Torr to 50 Torr. In order to obtain an oxidizing atmosphere, it is preferable to flow a mixed gas of oxygen gas and water vapor gas. It is particularly preferable that the mixed gas for forming the oxidizing atmosphere flows in at a rate of 5% by volume or more of water vapor gas.

本発明の好ましい態様においては、塗布膜はまず大気雰囲気で減圧下、２００℃以下の温度で乾燥され、ついで温度を上昇させて不活性ガス雰囲気で８００℃乃至９００℃程度で減圧下熱処理することによって未反応低分子成分や有機分解成分を除去しつつＳｉＯ２膜を成長させ、次いで８００℃乃至９００℃程度の高温に維持しつつ酸化性ガス雰囲気で、減圧下で熱処理することで、ボイドや粒状化のないＳｉＯ２膜を形成することができる。In a preferred embodiment of the present invention, the coating film is first dried in an air atmosphere under reduced pressure at a temperature of 200 ° C. or lower, and then heated to about 800 ° C. to 900 ° C. under reduced pressure in an inert gas atmosphere. The SiO 2 film is grown while removing unreacted low-molecular components and organic decomposition components, and then heat treatment under reduced pressure in an oxidizing gas atmosphere while maintaining a high temperature of about 800 ° C. to 900 ° C. A SiO 2 film without granulation can be formed.

本発明に係る製造方法では、素子分離領域にボイドや粒状化のない優れた特性のＳｉＯ２膜を形成することができる。In the manufacturing method according to the present invention, it is possible to form a SiO 2 film having excellent characteristics without voids or granulation in the element isolation region.

本発明に係る半導体装置の製造工程のうち、絶縁性塗布膜をスピンコートする工程を説明する断面図である。It is sectional drawing explaining the process of spin-coating an insulating coating film among the manufacturing processes of the semiconductor device which concerns on this invention. 本発明の実施例を説明するための図であり、ここでは、図１に示された絶縁性塗布膜を用いたＳＴＩ素子分離領域を説明する断面図を示している。It is a figure for demonstrating the Example of this invention, and shows sectional drawing explaining the STI element isolation region using the insulating coating film shown by FIG. 1 here. 本発明に従って形成されたＳＴＩ素子分離構造を含む半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device containing the STI element isolation structure formed according to this invention. 本発明の実施例において、半導体基板に設けたトレンチを示す断面図である。In the Example of this invention, it is sectional drawing which shows the trench provided in the semiconductor substrate. 本発明の実施例１、２、３及び比較例１において、トレンチを含む半導体基板に絶縁性塗布膜を塗布し焼成して形成されたＳＴＩ素子分離領域の断面を示す写真である。4 is a photograph showing a cross section of an STI element isolation region formed by applying and baking an insulating coating film on a semiconductor substrate including a trench in Examples 1, 2, 3 and Comparative Example 1 of the present invention. 本発明の実施例４から実施例９において、トレンチを含む半導体基板に絶縁性塗布膜を塗布し焼成して形成されたＳＴＩ素子分離領域の断面を示す写真である。6 is a photograph showing a cross section of an STI element isolation region formed by applying and baking an insulating coating film on a semiconductor substrate including a trench in Examples 4 to 9 of the present invention.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明に係る表面平坦化塗布膜（平滑化膜）を用いた半導体装置の製造工程の一部を示す断面図である。具体的に説明すると、シリコン基板１００中に、リン（Ｐ）を打ち込むことによって形成されたｎウェル５１と、ボロン（Ｂ）を打ち込むことによって形成されたｐウェル５２が設けられている。   FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a semiconductor device using a surface flattening coating film (smoothing film) according to the present invention. More specifically, an n well 51 formed by implanting phosphorus (P) and a p well 52 formed by implanting boron (B) are provided in the silicon substrate 100.

更に、ｎウェル５１とｐウェル５２との境界部の表面、及び、ｎウェル及びｐウェルの表面には、素子分離のためのシャロートレンチ（ＳＴ）５７が形成されている。図示されたシャロートレンチ５７は０．２２μｍの幅、０．２５μｍの深さを有している。   Further, shallow trenches (ST) 57 for element isolation are formed on the surface of the boundary between the n well 51 and the p well 52 and on the surfaces of the n well and the p well. The illustrated shallow trench 57 has a width of 0.22 μm and a depth of 0.25 μm.

ｎウェル５１、ｐウェル５２の表面には、ＳｉＯ２膜１１が形成されており、また、シャロートレンチ５７の底面及び側面にもＳｉＯ２膜５８が形成されている。The SiO 2 film 11 is formed on the surface of the n well 51 and the p well 52, and the SiO 2 film 58 is also formed on the bottom and side surfaces of the shallow trench 57.

図示されたＳｉＯ２膜１１及び５８上に、スピンコートによって絶縁性塗布膜１１０が塗布されている。当該絶縁性塗布膜１１０は、例えば、（ＣＨ３ＳｉＯ３／２）ｘ（ＳｉＯ２）１−ｘ（但し、０≦ｘ≦１．０）なる組成を有する材料を塗布することによって形成されている。この組成物は、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦x≦１．０）において、ｎ＝１とした場合の組成物である。An insulating coating film 110 is applied on the illustrated SiO 2 films 11 and 58 by spin coating. The insulating coating film 110 is formed, for example, by applying a material having a composition of (CH 3 SiO 3/2 ) x (SiO 2 ) 1-x (where 0 ≦ x ≦ 1.0). Yes. This composition has a general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0), and n = 1 It is a composition in the case of.

絶縁性塗布膜１１０の組成は、組成物を表す式（ＣＨ３ＳｉＯ３／２）ｘ（ＳｉＯ２）１−ｘからも明らかな通り、絶縁性塗布膜はＳｉ、Ｃ、及びＯを含んでおり、これらの成分の原子の個数の比は、Ｏ＞Ｓｉ＞１／２Ｃである。この組成物は、以下の説明で、ＳｉＣＯと簡略表記されることもある。As is apparent from the formula (CH 3 SiO 3/2 ) x (SiO 2 ) 1-x representing the composition, the composition of the insulating coating film 110 includes Si, C, and O. The ratio of the number of atoms of these components is O>Si> 1 / 2C. This composition may be abbreviated as SiCO in the following description.

また、絶縁性塗布膜１１０はメチル基（ＣＨ３）を含んでおり、当該メチル基は、空気中において３５０℃ぐらいから遊離するが、窒素（Ｎ２）ガス中では４００℃では遊離しない。ここで、ｘ＝１．０、即ち、ＣＨ３ＳｉＯ３／２成分のみの状態では、絶縁性塗布膜の比誘電率ｋは２．７であり、ｘ＝０．９ではｋは２．８、ｘ＝０．７ではｋは２．９、ｘ＝０．５ではｋは３．３となる。塗布液は上記の組成物５重量％以上を溶媒に溶かしたものを用い、塗布後、減圧下（５Ｔｏｒｒ）、大気雰囲気中で、１３０℃程度で、５分間加熱して乾燥させ、次いで不活性ガス（例えば窒素ガス）雰囲気中で減圧下（５Ｔｏｒｒ）、温度を１３０℃から上昇させて溶媒を完全に除去する。４００℃で加熱すると、比誘電率ｋが２．７乃至３．３のものが得られる。いずれもメチル基が遊離せず残存するためである。ここでは高絶縁体とするので、９００℃において１２０分加熱する。その結果、上記メチル基が遊離して、絶縁性塗布膜１１０はＳｉＯ２になる。The insulating coating film 110 includes a methyl group (CH 3 ), and the methyl group is released from about 350 ° C. in the air, but is not released at 400 ° C. in nitrogen (N 2 ) gas. Here, when x = 1.0, that is, only the CH 3 SiO 3/2 component, the dielectric constant k of the insulating coating film is 2.7, and when x = 0.9, k is 2.8. When x = 0.7, k is 2.9, and when x = 0.5, k is 3.3. The coating solution used was a solution in which 5% by weight or more of the above composition was dissolved in a solvent. After coating, the coating solution was dried by heating at about 130 ° C. for 5 minutes under reduced pressure (5 Torr) and then inactive. Under reduced pressure (5 Torr) in a gas (for example, nitrogen gas) atmosphere, the temperature is increased from 130 ° C. to completely remove the solvent. When heated at 400 ° C., a material having a relative dielectric constant k of 2.7 to 3.3 is obtained. In either case, the methyl group is not released and remains. Since it is a high insulator here, it is heated at 900 ° C. for 120 minutes. As a result, the methyl group is liberated and the insulating coating film 110 becomes SiO 2 .

引き続いて、本実施の形態においては、９００℃のまま流入ガスを窒素ガスから酸化性のガス（Ｈ２ＯとＯ２との混合ガス）に切り替え、１０Ｔｏｒｒ乃至２００Ｔｏｒｒに減圧し、６０分間加熱する。その結果、ボイドが発生せず、粒子状物の発生も避けることが出来る。また、このときの比誘電率ｋは４．０となる。なお、本発明における減圧力の表示（Ｔｏｒｒ）は絶対真空における真空圧力を０Ｔｏｒｒとした場合の減圧力表示である。Subsequently, in this embodiment, the inflowing gas is switched from nitrogen gas to oxidizing gas (mixed gas of H 2 O and O 2 ) while maintaining the temperature at 900 ° C., the pressure is reduced to 10 Torr to 200 Torr, and heating is performed for 60 minutes. . As a result, voids are not generated and generation of particulate matter can be avoided. In addition, the relative dielectric constant k at this time is 4.0. The decompression force display (Torr) in the present invention is a decompression force display when the vacuum pressure in the absolute vacuum is 0 Torr.

従来は、９００℃のまま流入ガスを窒素ガスから酸化性のガスに切り替え、常圧（７６０Ｔｏｒｒ）で、６０分間加熱し、高品質のＳｉＯ２に改質していた。しかしながら、ＳｉＯ２膜にボイドが発生したり、粒子状になってしまうという問題の発生が避けられなかった。本実施の形態においては、９００℃で、酸化性のガス雰囲気で、６０分間加熱するという過程は同じであるが、１０Ｔｏｒｒ乃至２００Ｔｏｒｒに減圧して熱処理を行う。その結果、ボイドが発生せず、粒子状物の発生も避けることが出来る。Conventionally, the inflowing gas was switched from nitrogen gas to oxidizing gas at 900 ° C., and heated at normal pressure (760 Torr) for 60 minutes to reform to high quality SiO 2 . However, it has been unavoidable that voids are generated in the SiO 2 film or become particles. In this embodiment, the process of heating at 900 ° C. in an oxidizing gas atmosphere for 60 minutes is the same, but the heat treatment is performed by reducing the pressure to 10 Torr to 200 Torr. As a result, voids are not generated and generation of particulate matter can be avoided.

図１において、絶縁性塗布膜１１０を形成する塗布液は常温では液状であるから、当該絶縁性塗布膜１１０は半導体基板上にスピンコート法により塗布することができ、塗布された状態では、流動性を有しているため、底面の凹凸形状を反映せず、高い平坦性を有している。すなわち、シャロートレンチ５７、ＳｉＯ２膜５８等によるシリコン基板１００上の凹凸には影響を受けることなく、表面を平坦な状態に維持できる。この絶縁性塗布膜１１０を上記のように乾燥・加熱・焼成することによって得られた表面平坦化膜をエッチングした場合、シリコン窒化膜（Ｓｉ３Ｎ４）、シリコン基板１００等と明確に識別することができるから、シリコン窒化膜（Ｓｉ３Ｎ４）をＳｉＯ２膜１１の上に設けておいてそれをストッパーとするか、又はシリコン基板１００をストッパーとして表面平坦化膜を平坦な状態を維持したままエッチングできる。したがって、表面平坦化膜はＣＭＰを用いることなく、エッチングだけで、表面の平坦性を保ちつつ均一に除去することができる。In FIG. 1, since the coating liquid for forming the insulating coating film 110 is liquid at room temperature, the insulating coating film 110 can be applied on the semiconductor substrate by a spin coating method. Therefore, it has high flatness without reflecting the uneven shape on the bottom surface. That is, the surface can be maintained flat without being affected by the unevenness on the silicon substrate 100 due to the shallow trench 57, the SiO 2 film 58, and the like. When the surface flattening film obtained by drying, heating, and baking the insulating coating film 110 as described above is etched, it is clearly distinguished from the silicon nitride film (Si 3 N 4 ), the silicon substrate 100, and the like. Therefore, a silicon nitride film (Si 3 N 4 ) is provided on the SiO 2 film 11 as a stopper, or the silicon substrate 100 is used as a stopper to keep the surface planarizing film flat. Etching can be performed as is. Therefore, the surface flattening film can be uniformly removed while maintaining the flatness of the surface only by etching without using CMP.

図１に示された絶縁性塗布膜１１０は、塗布・乾燥・加熱後、８００℃乃至９００℃の温度で酸化性ガスを流しつつ減圧下で熱処理（焼成）される。この熱処理の結果、絶縁性塗布膜１１０はボイドや粒子化のないＳｉＯ２に改質される。改質後の絶縁性塗布膜１１０は、平坦な表面を維持したＳｉＯ２膜となる。The insulating coating film 110 shown in FIG. 1 is heat-treated (fired) under reduced pressure while flowing an oxidizing gas at a temperature of 800 ° C. to 900 ° C. after coating, drying and heating. As a result of this heat treatment, the insulating coating film 110 is modified to SiO 2 free from voids or particles. The modified insulating coating film 110 is a SiO 2 film that maintains a flat surface.

図２は、改質後の絶縁性塗布膜１１０であるＳｉＯ２膜のうち、シリコン基板１００のｎウェル５１、ｐウェル５２上のＳｉＯ２膜がエッチングされた状態が示されている。2, of the SiO 2 film is an insulating coating film 110 after the modification, the SiO 2 film on the n-well 51, p-well 52 of the silicon substrate 100 is shown while being etched.

この場合、シャロートレンチ５７内には、ＳｉＣＯを完全に改質することによって得られたＳｉＯ２からなるＳＴＩ素子分離領域２ａが残されている。In this case, an STI element isolation region 2a made of SiO 2 obtained by completely modifying SiCO remains in the shallow trench 57.

図２に示すように、シャロートレンチ５７内のＳＴＩ分離領域２ａの表面は、シリコン基板１００の表面と同一平面を形成している。これは、シリコン基板１００をエッチングストッパーとして、ＳｉＯ２膜をエッチングできるからである。As shown in FIG. 2, the surface of the STI isolation region 2 a in the shallow trench 57 forms the same plane as the surface of the silicon substrate 100. This is because the SiO 2 film can be etched using the silicon substrate 100 as an etching stopper.

本発明に係るＳｉＯ２膜は、ＣＭＰが不要であるため、平坦な表面を備えた表面平坦化膜として利用できるだけでなく、ボイドがなく、粒子状物もない絶縁特性に優れたＳＴＩ素子分離領域を形成できる。素子分離領域２ａの誘電率は、ＳｉＯ２の誘電率と等しい４．０である。Since the SiO 2 film according to the present invention does not require CMP, it can be used not only as a surface flattening film having a flat surface, but also has no voids and no particulate matter, and has excellent insulation characteristics. Can be formed. The dielectric constant of the element isolation region 2a is 4.0 which is equal to the dielectric constant of SiO 2 .

図３において、図２に示されるＳＴＩ素子分離領域２ａを形成した後に行なわれる半導体装置の製造工程を説明する。   In FIG. 3, a manufacturing process of the semiconductor device performed after forming the STI element isolation region 2a shown in FIG. 2 will be described.

絶縁性塗布膜１１０を熱処理することによって形成されたＳＴＩ素子分離領域２ａが、シャロートレンチ５７に埋設された図２の構造に、図３に示すように、半導体素子を構成する各領域が形成される。すなわち、図３に示されているように、ＳＴＩ素子分離領域２ａで囲まれたｎウェル５１及びｐウェル５２（それぞれが素子形成領域である）の表面には、窒化シリコン（Ｓｉ３Ｎ４）によって形成されたゲート絶縁膜７０が形成され、各ゲート絶縁膜７０上には、ゲート電極７２が搭載されている。各ゲート電極７２及びゲート絶縁膜７０の側面及び表面は酸化膜１７によって覆われている。In the structure of FIG. 2 in which the STI element isolation region 2a formed by heat-treating the insulating coating film 110 is buried in the shallow trench 57, each region constituting the semiconductor element is formed as shown in FIG. The That is, as shown in FIG. 3, silicon nitride (Si 3 N 4 ) is formed on the surface of the n well 51 and the p well 52 (each of which is an element formation region) surrounded by the STI element isolation region 2a. The gate insulating film 70 formed by the above is formed, and the gate electrode 72 is mounted on each gate insulating film 70. Side surfaces and surfaces of the gate electrodes 72 and the gate insulating film 70 are covered with the oxide film 17.

また、ｎウェル５１の表面には、ｐ型不純物を打ち込むことによって形成されたｐ型素子領域（ソース又はドレイン領域）７４が設けられ、他方、ｐウェル５２の表面には、ｎ型不純物を打ち込むことによって形成されたｎ型素子領域（ソース又はドレイン領域）７６が設けられている。尚、各素子領域（ソース又はドレイン領域）７４、７６の表面にはコンタクトのためのシリサイド層７７が形成されている。   Further, a p-type element region (source or drain region) 74 formed by implanting p-type impurities is provided on the surface of the n-well 51, while n-type impurities are implanted into the surface of the p-well 52. An n-type element region (source or drain region) 76 formed thereby is provided. A silicide layer 77 for contact is formed on the surface of each element region (source or drain region) 74 and 76.

図示された例では、ｎウェル５１及びｐウェル５２上に、それぞれ形成された２つのＭＯＳトランジスタ間のゲート電極７２の間隔は４５ｎｍである。   In the illustrated example, the distance between the gate electrodes 72 between the two MOS transistors respectively formed on the n-well 51 and the p-well 52 is 45 nm.

この構造に従来公知の方法で多層配線を形成し、ＬＳＩを完成させる。   A multilayer wiring is formed in this structure by a conventionally known method to complete an LSI.

なお、上述の実施形態では、先に示した一般式においてｎ＝１の組成物、すなわち、（ＣＨ３ＳｉＯ３／２）ｘ（ＳｉＯ２）１−ｘ（但し、０≦ｘ≦１．０）なる組成の塗布膜を用いた例を示したが、この式のＣＨ３ＳｉＯ３／２の代わりに例えば（ＣＨ３）２ＳｉＯや、（ＣＨ３）３ＳｉＯ１／２等、またはそれらの混合体を使用してもよい。すなわち、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物一種又は二種以上と溶媒とで構成される塗布膜を用いるのが、本発明の特徴である。ここで、前記の一般式の最初の「Ｏ」のサフィックスは、２−（ｎ／２）である。In the above-described embodiment, the composition of n = 1 in the general formula shown above, that is, (CH 3 SiO 3/2 ) x (SiO 2 ) 1-x (where 0 ≦ x ≦ 1.0 In this example, instead of CH 3 SiO 3/2 in this formula, (CH 3 ) 2 SiO, (CH 3 ) 3 SiO 1/2, etc. Mixtures may be used. That is, one or two compositions represented by the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0) It is a feature of the present invention to use a coating film composed of a seed or more and a solvent. Here, the suffix of the first “O” in the above general formula is 2- (n / 2).

なお、上記組成物のｘの値が０．５乃至０．９のものをもちいるとボイドの発生を避けやすいことが判明した。特に、０．７前後が好ましい。塗布液における上記組成物の濃度は、５重量％乃至２０重量％とするとボイドの発生を避けやすいことも判明した。特に、１０重量％前後が好ましい。粒状物の発生（粒状化）を避けるには、塗布膜を酸化性雰囲気で熱処理する際の圧力を１０Ｔｏｒｒ乃至２００Ｔｏｒｒの減圧下で、熱処理すればよいが、２０Ｔｏｒｒ乃至５０Ｔｏｒｒが特に好ましい。   It has been found that the use of the above composition having an x value of 0.5 to 0.9 facilitates the generation of voids. In particular, around 0.7 is preferable. It has also been found that when the concentration of the composition in the coating solution is 5% by weight to 20% by weight, generation of voids can be easily avoided. In particular, about 10% by weight is preferable. In order to avoid the generation (granulation) of the granular material, the heat treatment may be performed under a reduced pressure of 10 Torr to 200 Torr when the coating film is heat-treated in an oxidizing atmosphere, but 20 Torr to 50 Torr is particularly preferable.

塗布膜を酸化するための酸化性雰囲気としては、塗布膜を酸化できるガスであればよく、好ましくは水蒸気ガス又は酸素ガスを含むガスの雰囲気或いは水蒸気ガス又は酸素ガスを含むガスが流れる雰囲気がよい。より好ましくは水蒸気ガスを含むガスの雰囲気或いは水蒸気ガスを含むガスが流れる雰囲気がよい。さらに好ましくは、水蒸気ガスと酸素ガスとを含むガスの雰囲気或いは水蒸気ガスと酸素ガスとを含むガスとが流れる雰囲気がよく、これらの混合ガスでもよい。混合ガスの体積が１００容量％とした場合に、水蒸気ガスが５容量％以上含まれる水蒸気ガスと酸素ガスの混合ガス中がよく、特に、５容積％乃至５０容積％で塗布膜を８００℃乃至９００℃の温度で熱処理焼成することによって酸化すると、電気絶縁性の点で良質なＳｉＯ２膜が得られる。The oxidizing atmosphere for oxidizing the coating film may be any gas that can oxidize the coating film, preferably an atmosphere of a gas containing water vapor gas or oxygen gas or an atmosphere through which a gas containing water vapor gas or oxygen gas flows. . More preferably, an atmosphere of a gas containing water vapor gas or an atmosphere in which a gas containing water vapor gas flows is preferable. More preferably, an atmosphere of a gas containing water vapor gas and oxygen gas or an atmosphere through which a gas containing water vapor gas and oxygen gas flows, or a mixed gas thereof may be used. When the volume of the mixed gas is 100% by volume, the mixed gas of water vapor gas and oxygen gas containing 5% by volume or more of the water vapor gas is preferable. When oxidized by heat treatment baking at a temperature of 900 ° C., a high-quality SiO 2 film can be obtained in terms of electrical insulation.

塗布膜を酸化するための熱処理焼成温度は、８００℃乃至９００℃の温度がよいが、さらに好ましくは８５０℃乃至９００℃の温度で酸化すると、電気絶縁性に優れたより良質なＳｉＯ２膜が得られる。The heat treatment baking temperature for oxidizing the coating film is preferably 800 ° C. to 900 ° C., and more preferably oxidized at a temperature of 850 ° C. to 900 ° C. to obtain a better quality SiO 2 film having excellent electrical insulation. It is done.

トレンチの内壁を覆う膜５８は、厚さは５ｎｍ以下でよく、下地シリコンを直接酸化して形成した酸化シリコンのほか、下地シリコンを直接窒化するかまたはＣＶＤで形成した窒化シリコンでもよく、両方から構成しても良い。あるいは、この膜５８は設けずに、下地シリコン表面に直接平坦化膜を形成してもよい。   The film 58 covering the inner wall of the trench may have a thickness of 5 nm or less, and may be silicon oxide formed by directly oxidizing the base silicon, or silicon nitride formed by directly nitriding the base silicon or CVD. It may be configured. Alternatively, a planarizing film may be formed directly on the underlying silicon surface without providing this film 58.

（実施例１）
図４は、本発明の実施例１におけるシャロートレンチの断面図を示す。これは、シリコン基板４０に複数のトレンチ４１が設けられ、各トレンチは、入り口部の口径ａが１３０ｎｍ、高さｂが５００ｎｍ、底面の口径ｃが４７ｎｍであり、この寸法のトレンチ形成基板を作製した。参考例として、ｂおよびｃは前記寸法と同じで、ａが２２０ｎｍのものと、３８０ｎｍのトレンチ形成基板も作製した。Example 1
FIG. 4 is a cross-sectional view of the shallow trench according to the first embodiment of the present invention. This is because a plurality of trenches 41 are provided in a silicon substrate 40, and each trench has a diameter a of an entrance portion of 130 nm, a height b of 500 nm, and a diameter c of a bottom surface of 47 nm. did. As a reference example, b and c were the same as the above dimensions, and a substrate with a trench of 220 nm and a trench forming substrate of 380 nm were also produced.

図４の、トレンチ入り口部の口径ａが１３０ｎｍのシリコン基板のトレンチ内と基板上を覆うように塗布膜をスピンコートした。塗布膜としては、組成式（ＣＨ３ＳｉＯ３／２）ｘ（ＳｉＯ２）１−ｘで、ｘ＝０．７の組成物を１０重量％含むものを用いた。塗布膜形成後、サンプルを熱処理室へ導入し、（１）減圧下（５Ｔｏｒｒ）、大気雰囲気中で、１３０℃で、５分間加熱して塗布膜を乾燥させ、次いで、（２）熱処理室に窒素ガスを流しつつ減圧下（５Ｔｏｒｒ）、温度を１３０℃から上昇させ、９００℃において１２０分加熱した。引き続いて、（３）９００℃のまま熱処理室への流入ガスを窒素ガスから、酸化性雰囲気のガスとして１０容量％のＨ２Ｏガスと９０容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが２００ｃｃ／ｍｉｎ、Ｏ２ガスが１８００ｃｃ／ｍｉｎの流量で流しつつ、２０Ｔｏｒｒの減圧下で、６０分間加熱し、半導体装置サンプルを作製した。また参考例として、トレンチ入り口部の口径ａが２２０ｎｍ、３８０ｎｍのシリコン基板についても実施例１と同一条件で半導体装置サンプルを作製した。これらの作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ（電子顕微鏡）観察した時の写真を、それぞれ図５に示す。なお、図５において、写真上の線（白線）はＳＴＩ（シャロートレンチアイソレイション）素子分離境界線を視認し易くするために、例示したものである。The coating film was spin-coated so as to cover the inside and the top of the silicon substrate trench having a diameter a of 130 nm in FIG. As the coating film, a compositional formula (CH 3 SiO 3/2 ) x (SiO 2 ) 1-x containing 10% by weight of a composition of x = 0.7 was used. After forming the coating film, the sample is introduced into the heat treatment chamber. (1) The coating film is dried by heating at 130 ° C. for 5 minutes under reduced pressure (5 Torr), and then (2) in the heat treatment chamber. Under reduced pressure (5 Torr) while flowing nitrogen gas, the temperature was raised from 130 ° C. and heated at 900 ° C. for 120 minutes. Subsequently, (3) the gas flowing into the heat treatment chamber is kept at 900 ° C. from nitrogen gas, and a mixed gas of 10% by volume H 2 O gas and 90% by volume O 2 gas is used as an oxidizing atmosphere gas. While flowing 2 O gas at a flow rate of 200 cc / min and O 2 gas at a flow rate of 1800 cc / min, the sample was heated for 60 minutes under a reduced pressure of 20 Torr to produce a semiconductor device sample. As a reference example, a semiconductor device sample was manufactured under the same conditions as in Example 1 for a silicon substrate having a trench entrance diameter a of 220 nm and 380 nm. FIG. 5 shows photographs of these fabricated semiconductor device samples taken by slicing the silicon substrate including the trench portion in the longitudinal direction and observing the cross section with an SEM (electron microscope). In FIG. 5, the line on the photograph (white line) is illustrated for easy recognition of the STI (shallow trench isolation) element isolation boundary line.

図５において、実施例１と表示した列の上段の写真が示すように、トレンチ入り口部の口径ａが１３０ｎｍのシリコン基板に塗布し、酸化性雰囲気ガスが２０Ｔｏｒｒに減圧された状態で熱処理焼成した実施例１の場合、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっており、優れた素子分離領域が形成できていた。なお、減圧力を１０Ｔｏｒｒに下げても（即ち、減圧度を上げても）ほぼ同じ結果が得られた。また、参考例であるトレンチ入り口部の口径ａがより広い２２０ｎｍ、３８０ｎｍにおいても同様の結果が得られた。   In FIG. 5, as shown in the upper photograph of the column labeled as Example 1, it was applied to a silicon substrate having a diameter of a trench entrance of 130 nm and heat-treated and fired in a state where the oxidizing atmosphere gas was reduced to 20 Torr. In the case of Example 1, no void was generated, no formation of particulates was observed, and the STI element isolation region was excellent, and an excellent element isolation region was formed. Even when the decompression force was reduced to 10 Torr (that is, the degree of decompression was increased), almost the same result was obtained. Further, similar results were obtained at 220 nm and 380 nm, which are wider than the diameter a of the trench entrance portion as a reference example.

（実施例２）
実施例２では、実施例１における(３)の工程で、酸化性雰囲気ガスの圧力を４０Ｔｏｒｒにし、この点以外を実施例１と同じ条件にして、半導体装置サンプルを作製した。(Example 2)
In Example 2, a semiconductor device sample was manufactured in the step (3) in Example 1 under the same conditions as in Example 1 except that the pressure of the oxidizing atmosphere gas was set to 40 Torr.

また、参考例として、トレンチ入り口部の口径ａが２２０ｎｍ、３８０ｎｍのシリコン基板についても、実施例２と同一条件で半導体装置サンプルを作製した。   As a reference example, a semiconductor device sample was manufactured under the same conditions as in Example 2 for a silicon substrate having a trench entrance diameter a of 220 nm and 380 nm.

図５において、実施例２と表示した列の上段の写真が示すように、トレンチ入り口部の口径ａが１３０ｎｍのシリコン基板に塗布し、酸化性雰囲気ガスが４０Ｔｏｒｒに減圧された状態で熱処理焼成した実施例２の場合にも、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっており、優れた素子分離領域が形成できていた。また、参考例であるトレンチ入り口部の口径ａがより広い２２０ｎｍ、３８０ｎｍの基板を用い、実施例２と同じ条件化で作製したサンプルについても、同様の結果が得られた。   In FIG. 5, as shown in the upper photograph of the column labeled as Example 2, the trench a is applied to a silicon substrate having a diameter of 130 nm at the entrance of the trench and heat-treated and fired in a state where the oxidizing atmosphere gas is reduced to 40 Torr. In the case of Example 2 as well, no voids were generated and no particulate matter was formed, and the STI element isolation region was excellent, and an excellent element isolation region could be formed. Moreover, the same result was obtained also about the sample produced on the same conditions as Example 2 using the 220 nm and 380 nm board | substrate with wider diameter a of the trench entrance part which is a reference example.

（実施例３）
実施例３では、実施例１における(３)の工程で、酸化性雰囲気ガスの圧力を２００Ｔｏｒｒにし、この点以外を実施例１と同じ条件にして、半導体装置サンプルを作製した。(Example 3)
In Example 3, a semiconductor device sample was manufactured in the step (3) in Example 1 under the same conditions as in Example 1 except that the pressure of the oxidizing atmosphere gas was set to 200 Torr.

また、参考例として、トレンチ入り口部の口径ａが２２０ｎｍ、３８０ｎｍのシリコン基板についても、実施例３と同一条件で半導体装置サンプルを作製した。   As a reference example, a semiconductor device sample was manufactured under the same conditions as in Example 3 for a silicon substrate having a trench entrance diameter a of 220 nm and 380 nm.

図５において、実施例３と表示した列の上段の写真が示すように、トレンチ入り口部の口径ａが１３０ｎｍのシリコン基板に塗布し、酸化性雰囲気ガスが２００Ｔｏｒｒに減圧された状態で熱処理焼成した実施例３場合にも、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっており、優れた素子分離領域が形成できていた。また、参考例であるトレンチ入り口部の口径ａがより広い２２０ｎｍ、３８０ｎｍの基板を用い、実施例３と同じ条件で作製したサンプルについても、同様の結果が得られた。   In FIG. 5, as shown in the upper photograph of the column labeled as Example 3, the film was applied to a silicon substrate having a diameter of 130 nm at the trench entrance and heat-treated and fired in a state where the oxidizing atmosphere gas was reduced to 200 Torr. In Example 3 as well, no voids were generated, no particulate matter was formed, and the STI element isolation region was excellent, and an excellent element isolation region could be formed. Moreover, the same result was obtained also about the sample produced on the same conditions as Example 3 using the 220 nm and 380 nm board | substrate with wider diameter a of the trench entrance part which is a reference example.

（比較例１）
減圧力を４００Ｔｏｒｒ、６００Ｔｏｒｒ、更に減圧ではなく常圧（即ち７６０Ｔｏｒｒ）とした以外は実施例１と同一条件で加熱した半導体装置サンプルを作製した。また参考例として、トレンチ入り口部の口径ａが２２０ｎｍ、３８０ｎｍのシリコン基板についても比較例１と同一条件で半導体装置サンプルを作製した。これらの作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を、それぞれ図５に示す。(Comparative Example 1)
A semiconductor device sample heated under the same conditions as in Example 1 was manufactured except that the decompression force was 400 Torr, 600 Torr, and further normal pressure (ie, 760 Torr) instead of reduced pressure. As a reference example, a semiconductor device sample was fabricated under the same conditions as in Comparative Example 1 for a silicon substrate having a trench entrance diameter a of 220 nm and 380 nm. FIG. 5 shows photographs of these fabricated semiconductor device samples when the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図５において、比較例である４００Ｔｏｒｒ、６００Ｔｏｒｒの減圧下および常圧（７６０Ｔｏｒｒ）下で、Ｈ２Ｏガス１０容積％とＯ２ガス９０容積％との混合ガスの流れる雰囲気中で、９００℃で熱処理焼成した場合は、ＳＴＩ素子分離領域のＳｉＯ２が粒状化しており、粒状物の形成が明瞭に認められた。従って比較例１の結果は実施例１より劣る結果であった。また、参考例であるトレンチ入り口部の口径ａがより広い２２０ｎｍ、３８０ｎｍにおいても同様の結果が得られた。In FIG. 5, in an atmosphere where a mixed gas of 10% by volume of H 2 O gas and 90% by volume of O 2 gas flows under a reduced pressure of 400 Torr and 600 Torr as comparative examples and under normal pressure (760 Torr) at 900 ° C. When the heat treatment was performed, the SiO 2 in the STI element isolation region was granulated, and the formation of granular materials was clearly recognized. Therefore, the result of Comparative Example 1 was inferior to that of Example 1. Further, similar results were obtained at 220 nm and 380 nm, which are wider than the diameter a of the trench entrance portion as a reference example.

（実施例４）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（３）の工程で、酸化性雰囲気のガスとして５容量％のＨ２Ｏガスと９５容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが１００ｃｃ／ｍｉｎ、Ｏ２ガスが１９００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ａ）に示す。なお、図６において、写真上の線（白線）はＳＴＩ（シャロートレンチアイソレイション）素子分離境界線を視認し易くするために、例示したものである。Example 4
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, and in the step (3) of Example 1, 5% by volume of H 2 O gas and 95% by volume of O 2 gas are used as oxidizing atmosphere gases. A semiconductor device sample was produced under the same conditions as in Example 1 except that the mixed gas was heated under reduced pressure of 50 Torr while flowing H 2 O gas at a flow rate of 100 cc / min and O 2 gas at 1900 cc / min. did. FIG. 6A shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM. In FIG. 6, a line on the photograph (white line) is illustrated for easy recognition of the STI (shallow trench isolation) element isolation boundary line.

図６の（Ａ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6A, no void was generated, and no granular material was formed, and the STI element isolation region was satisfactory.

（実施例５）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（３）の工程で、酸化性雰囲気のガスとして２５容量％のＨ２Ｏガスと７５容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが５００ｃｃ／ｍｉｎ、Ｏ２ガスが１５００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ｂ）に示す。(Example 5)
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, and in the process (3) of Example 1, 25% by volume of H 2 O gas and 75% by volume of O 2 gas are used as oxidizing atmosphere gases. A semiconductor device sample was fabricated under the same conditions as in Example 1 except that the mixed gas was heated under reduced pressure of 50 Torr while flowing H 2 O gas at a flow rate of 500 cc / min and O 2 gas at 1500 cc / min. did. FIG. 6B shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図６の（Ｂ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6B, no void was generated, and no granular material was formed, and the STI element isolation region was satisfactory.

（実施例６）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（２）の工程で、加熱昇温温度を８８０℃とし、実施例１の（３）の工程で、酸化性雰囲気のガスとして２５容量％のＨ２Ｏガスと７５容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが５００ｃｃ／ｍｉｎ、Ｏ２ガスが１５００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で、８８０℃で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ｃ）に示す。(Example 6)
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, the heating temperature is set to 880 ° C. in the step (2) of Example 1, and the oxidizing atmosphere is set in the step (3) of Example 1. 25 volume% of the H 2 O gas and 75 volume% of a gas mixture of O 2 gas as the gas, the H 2 O gas is 500 cc / min, O 2 gas while flowing at a flow rate of 1500cc / min, under a reduced pressure of 50Torr Thus, a semiconductor device sample was produced under the same conditions as in Example 1 except that the sample was heated at 880 ° C. FIG. 6C shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図６の（Ｃ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6C, voids were not generated and no granular material was formed, and the STI element isolation region was satisfactory.

（実施例７）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（２）の工程で、加熱昇温温度を８５０℃とし、実施例１の（３）の工程で、酸化性雰囲気のガスとして２５容量％のＨ２Ｏガスと７５容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが５００ｃｃ／ｍｉｎ、Ｏ２ガスが１５００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で、８５０℃で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ｄ）に示す。(Example 7)
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, the heating temperature is set to 850 ° C. in the step (2) of Example 1, and the oxidizing atmosphere is set in the step (3) of Example 1. 25 volume% of the H 2 O gas and 75 volume% of a gas mixture of O 2 gas as the gas, the H 2 O gas is 500 cc / min, O 2 gas while flowing at a flow rate of 1500cc / min, under a reduced pressure of 50Torr Thus, a semiconductor device sample was produced under the same conditions as in Example 1 except that heating was performed at 850 ° C. FIG. 6D shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図６の（Ｄ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6D, no void was generated, and no granular material was formed, and the STI element isolation region was satisfactory.

（実施例８）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（２）の工程で、加熱昇温温度を８８０℃とし、実施例１の（３）の工程で、酸化性雰囲気のガスとして５０容量％のＨ２Ｏガスと５０容量％のＯ２ガスとの混合ガスを、Ｈ２Ｏガスが１０００ｃｃ／ｍｉｎ、Ｏ２ガスが１０００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で、８８０℃で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ｅ）に示す。(Example 8)
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, the heating temperature is set to 880 ° C. in the step (2) of Example 1, and the oxidizing atmosphere is set in the step (3) of Example 1. 50 volume% of the H 2 O gas and 50 volume% of a gas mixture of O 2 gas as the gas, the H 2 O gas is 1000 cc / min, O 2 gas while flowing at a flow rate of 1000 cc / min, under a reduced pressure of 50Torr Thus, a semiconductor device sample was produced under the same conditions as in Example 1 except that the sample was heated at 880 ° C. FIG. 6E shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図６の（Ｅ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6E, no void was generated, and no granular material was observed, and the STI element isolation region was satisfactory.

（実施例９）
トレンチ入り口部の口径ａは１３０ｎｍのシリコン基板を使用し、実施例１の（２）の工程で、加熱昇温温度を８８０℃とし、実施例１の（３）の工程で、酸化性雰囲気のガスとしてＨ２Ｏガスのみを、２０００ｃｃ／ｍｉｎの流量で流しつつ、５０Ｔｏｒｒの減圧下で、８８０℃で加熱した以外は、実施例１と同一な条件で、半導体装置サンプルを作製した。この作製した半導体装置サンプルの、トレンチ部を含むシリコン基板を縦方向に切断し、その断面をＳＥＭ観察した時の写真を図６の（Ｆ）に示す。Example 9
A silicon substrate having a diameter of 130 nm at the entrance of the trench is used, the heating temperature is set to 880 ° C. in the step (2) of Example 1, and the oxidizing atmosphere is set in the step (3) of Example 1. A semiconductor device sample was fabricated under the same conditions as in Example 1 except that only H 2 O gas was flowed at a flow rate of 2000 cc / min and heated at 880 ° C. under a reduced pressure of 50 Torr. FIG. 6F shows a photograph of the manufactured semiconductor device sample, in which the silicon substrate including the trench portion is cut in the vertical direction and the cross section is observed by SEM.

図６の（Ｆ）において、ボイドの発生はなく、粒状物の形成も認められず、良好なＳＴＩ素子分離領域となっていた。   In FIG. 6F, no void was generated, and no granular material was formed, and the STI element isolation region was satisfactory.

本発明の半導体装置の製造方法は、ＳＴＩ構造を含む各種の半導体装置に適用できる。   The method for manufacturing a semiconductor device of the present invention can be applied to various semiconductor devices having an STI structure.

Claims (12)

素子分離領域を備えた半導体装置の製造方法において、半導体基板に前記素子分離領域を形成するためのシャロートレンチを形成する工程と、
前記シャロートレンチを含む前記半導体基板上に、塗布液を塗布する工程と、
前記塗布された塗布膜を素子分離用絶縁物に改質する工程とを含み、
前記塗布液は、一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物の一種又は二種以上および溶媒を含んで構成され、
前記改質する工程は、前記塗布膜を酸化性雰囲気中で、かつ１０Ｔｏｒｒ乃至２００Ｔｏｒｒの減圧下で、熱処理する工程を含むことを特徴とする半導体装置の製造方法。In a manufacturing method of a semiconductor device provided with an element isolation region, a step of forming a shallow trench for forming the element isolation region in a semiconductor substrate;
Applying a coating liquid on the semiconductor substrate including the shallow trench;
Modifying the applied coating film into an element isolation insulator,
The coating solution is a composition represented by the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ x ≦ 1.0). Comprising one or more of these and a solvent,
The modifying step includes a step of heat-treating the coating film in an oxidizing atmosphere and under a reduced pressure of 10 Torr to 200 Torr. 請求項１記載の半導体装置の製造方法において、前記熱処理は８００℃乃至９００℃の温度
で行われることを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature of 800 to 900.degree. 請求項１又は２に記載の半導体装置の製造方法において、前記酸化性雰囲気が少なくとも水蒸気ガスを含むことを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidizing atmosphere includes at least a water vapor gas. 4. 請求項３記載の半導体装置の製造方法において、更に、前記改質された素子分離用絶縁物を、ＣＭＰを施すことなく、表面を半導体基板表面と同等の高さにする工程を含むことを特徴とする半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of making the surface of the modified isolation insulator have the same height as the surface of the semiconductor substrate without performing CMP. A method for manufacturing a semiconductor device. 請求項４に記載の半導体装置の製造方法において、前記表面を半導体基板表面と同等の高さにする工程は、エッチング工程であることを特徴とする半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of making the surface the same height as the surface of the semiconductor substrate is an etching step. 請求項３記載の半導体装置の製造方法において、更に、前記素子分離領域によって画成された前記半導体基板の素子形成領域にソース領域およびドレイン領域を形成する工程および前記素子形成領域上にゲート絶縁膜を介してゲート電極を形成する工程を含むことを特徴とする半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, further comprising: forming a source region and a drain region in an element forming region of the semiconductor substrate defined by the element isolation region; and a gate insulating film on the element forming region. A method for manufacturing a semiconductor device, comprising a step of forming a gate electrode through a semiconductor device. 請求項１又は２に記載の半導体装置の製造方法において、前記一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物は、ｘの範囲が０．５≦ｘ≦０．９の組成物であることを特徴とする半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ 3). The composition represented by x ≦ 1.0) is a composition in which the range of x is 0.5 ≦ x ≦ 0.9. 請求項１又は２に記載の半導体装置の製造方法において、前記一般式（（ＣＨ３）nＳｉＯ２−ｎ／２）ｘ（ＳｉＯ２）１−ｘ（但し、ｎ＝１乃至３、０≦ｘ≦１．０）で示される組成物は、ｘの範囲が０．６≦ｘ≦０．８の組成物であることを特徴とする半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the general formula ((CH 3 ) n SiO 2 -n / 2 ) x (SiO 2 ) 1-x (where n = 1 to 3, 0 ≦ 3). The composition represented by x ≦ 1.0) is a composition in which the range of x is 0.6 ≦ x ≦ 0.8. 請求項１又は２に記載の半導体装置の製造方法において、前記塗布液における前記組成物の濃度を５重量％乃至２０重量％とすることを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of the composition in the coating solution is 5% by weight to 20% by weight. 請求項１又は２に記載の半導体装置の製造方法において、前記改質する工程における減圧圧力を２０Ｔｏｒｒ乃至５０Ｔｏｒｒとすることを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the reduced pressure in the modifying step is 20 Torr to 50 Torr. 4. 請求項３に記載の半導体装置の製造方法において、前記改質する工程における前記酸化性雰囲気は、酸素ガスと水蒸気ガスとの混合ガスの流れによってつくるものであって、水蒸気ガスの割合が５容積％以上であることを特徴とする半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein the oxidizing atmosphere in the modifying step is created by a flow of a mixed gas of oxygen gas and water vapor gas, and the proportion of water vapor gas is 5 volumes. % Or more of the semiconductor device manufacturing method. 請求項４に記載の半導体装置の製造方法において、前記改質する工程の前に、前記塗布膜を大気雰囲気で減圧下２００℃以下の温度で乾燥する工程と、ついで温度を上昇させて不活性ガス雰囲気で９００℃以下の程度で減圧下加熱する工程とを含むことを特徴とする半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein, prior to the modifying step, the coating film is dried at a temperature of 200 ° C. or less under reduced pressure in an air atmosphere, and then the temperature is increased to be inactive. And a step of heating under reduced pressure at about 900 ° C. or less in a gas atmosphere.
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