JPWO2011108768A1 - Embedded gate type silicon carbide static induction transistor and manufacturing method thereof - Google Patents

Abstract

The buried gate SiC-SIT of the present invention includes a first conductivity type drift layer (3) formed on a first conductivity type high concentration SiC substrate (2), and a lateral direction substantially parallel to the drift layer. The second conductivity type high concentration gate region (5) and the first conductivity type low concentration channel region (4) arranged adjacent to each other, and the first conductivity type formed on the high concentration gate region and the low concentration channel region. A transistor structure including a conduction type layer (7) and a first conduction type high concentration source region (8) formed on the first conduction type layer is provided. The transistor structure is normally-off type, and the transistor structure has the conduction characteristics and the breakdown characteristics such that the breakdown voltage and the characteristic on-resistance are 600 V or more and 4.0 mΩcm 2 or less, respectively. By analyzing using simulation, the length, half width, and impurity concentration of the low concentration channel region are determined.

Description

  The present invention relates to a buried gate type static induction transistor using a silicon carbide (SiC) semiconductor, and more particularly to a buried gate type silicon carbide static induction transistor having normally-off characteristics.

Silicon carbide, particularly 4H-SiC, has a breakdown electric field of about 10 times, an electron saturation drift velocity of about 2 times, and a thermal conductivity of about 3 times that of silicon, so that a transistor formed on a silicon carbide substrate is used. Is attracting attention. Moreover, the energy gap of silicon carbide is 3 eV or more, which is about three times that of silicon. For this reason, the breakdown electric field is about one digit larger. Therefore, the withstand voltage can be increased by an order of magnitude or reduced by an order of magnitude compared to silicon devices. Further, operation at a higher temperature is possible. Further, as described above, since the dielectric breakdown electric field of SiC is 10 times that of silicon, when a device having the same breakdown voltage is manufactured, the depletion layer of the semiconductor device including the semiconductor substrate made of SiC is a semiconductor substrate made of Si. It is reduced to 1/10 of the width of the depletion layer of the semiconductor device using. Therefore, when a semiconductor substrate made of SiC is used, the doping concentration of the impurity added to the region where the depletion layer is formed can be increased to about 100 times that of a semiconductor substrate made of silicon. At the same time, since the energy levels of the donor and acceptor which are impurities are relatively shallow, the resistance of the drift region can be reduced by two orders of magnitude or more compared to a silicon element having the same breakdown voltage. As described above, a device with low power loss can be realized by utilizing the above-described excellent electronic properties of silicon carbide.
Thus, silicon carbide has attracted attention as a semiconductor material for power semiconductor elements because it has a wide band gap and a breakdown electric field strength of 10 times or more compared to silicon.
A buried gate type static induction transistor (SIT) is a “buried gate structure (BG)” in which a gate region is buried in an active region of an element and a gate extraction electrode is formed around the element. Is provided. Since a channel is formed in the semiconductor bulk, the buried gate structure impairs high electron mobility in silicon carbide compared to a metal-oxide-semiconductor (MOS) gate structure. It is expected that high performance devices can be developed. Further, the above-described buried gate structure does not require an alignment margin in the photolithography process when forming the surface electrode. Therefore, the buried gate structure has an advantage that the channel density can be increased and the on-resistance can be easily reduced as compared with a “surface gate structure (SG)” in which a gate electrode is provided on the surface of the semiconductor region.
Furthermore, in general, when a three-terminal power semiconductor element is used in a power conversion device such as an inverter circuit or a power supply circuit, the power semiconductor element is cut off (off state) when an unexpected failure occurs in a drive circuit or the like. However, it is desirable from the viewpoint of safety measures of the device. For this purpose, the power semiconductor element needs to have a normally-off characteristic in which the element is cut off when no voltage is applied to the input terminal.
[Patent Document 1]
As a prior art, for example, Patent Document 1 discloses a method for manufacturing SIT on a SiC substrate. However, there is no disclosure about the manufacturing method of normally-off type SIT.
[Patent Document 2]
Further, Patent Document 2 discloses a structure in which the advantages of the electrostatic induction transistor structure are combined, and a combination of the two is obtained so as to obtain the normally-off type advantage of the insulated gate field effect transistor structure. Yes. The disclosed insulated gate silicon carbide semiconductor device has a structure in which SIT and MOSFET are monolithically included in a SiC single crystal substrate. In the silicon carbide semiconductor device, an ohmic electrode is formed so as to be connected to a buried gate region, a MOSFET having a p-well region selectively formed by ion implantation is formed on the surface, and a SIT and a lateral type are formed. MOSFET is connected. However, this structure is a normally-off type in which SIT and MOSFET are arranged in series.
[Patent Document 3]
Patent Document 3 discloses a normally-off silicon carbide insulated gate semiconductor device configured by combining an electrostatic induction transistor structure and an insulated gate field effect transistor structure on a SiC substrate. This SIT structure includes a p ⁺ gate region to an n type drift layer deposited on an n ⁺ type SiC semiconductor substrate and an n ⁺ type first source region deposited on the surface of the n type drift layer above the gate region. The width of the channel region 9 of the SIT, which is the interval between the p ⁺ gate regions, is about 0.5 to 5 μm. Also in this example, an electrostatic induction transistor structure and an insulated gate field effect transistor structure are arranged in series to form a normally-off type.
[Patent Document 4]
Patent Document 4 discloses a low-concentration n-type drift layer formed by epitaxial growth on the surface of a high-concentration n-type silicon carbide substrate, and a plurality of high-concentration p-type gate regions separated from each other on the low-concentration n-type drift layer. Forming a low-concentration n-type channel region located between the high-concentration p-type gate regions adjacent to each other, epitaxially growing the low-concentration n-type region on the structure, and performing high-concentration n-type source by ion implantation A silicon carbide transistor device is disclosed in which a region is formed, a source electrode is formed on the high-concentration n-type source region, a gate electrode is formed on the high-concentration p-type layer, and a drain electrode is formed on the back surface of the high-concentration n-type silicon carbide substrate. Has been. However, this document does not disclose the realization of a normally-off type structure.
In this silicon carbide transistor device, for example, 1.0 × 10 ¹⁴ / cm ³ to 1 is formed on an n-type silicon carbide substrate having an impurity concentration of 1.0 × 10 ^{18 to} 1.0 × 10 ²⁰ / cm ³ , for example. An n-type drift layer having an impurity concentration of 0.0 × 10 ¹⁷ / cm ³ is formed. Further, the p-type gate region having an impurity concentration of, for example, 1.0 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ²⁰ / cm ³ separated from each other and immediately adjacent to each other immediately above the n-type drift layer. An n-type channel region having an impurity concentration of, for example, 1.0 × 10 ¹⁴ / cm ^{3 to} 1.0 × 10 ¹⁷ / cm ³ formed by epitaxial growth is provided between the p-type gate regions. Further, a low concentration n-type region having the same impurity concentration as that of the n-type channel region is provided immediately above the p-type gate region and the n-type channel region.
[Patent Document 5]
Patent Document 5 discloses a method for designing a channel structure of a normally-on type silicon carbide static induction transistor and a silicon carbide transistor device to which the method is applied.
[Non-Patent Document 1]
Further, Non-Patent Document 1 discloses a silicon carbide electrostatic induction transistor (hereinafter also referred to as “SiC-SIT”) having the structure shown in FIG. However, in view of the physical properties of SiC as a semiconductor material, there is room for further improvement. For example, it is well known that improvement in SIT performance can be expected by miniaturizing the channel and gate structure. However, the structure of FIG. 16 is a surface gate electrode structure in which a gate electrode is disposed immediately above the p ⁺ gate region 5. In this structure, the gate electrode and the source electrode are reliably separated from each other, and at the same time, contact holes (not shown) are reliably formed in the p ⁺ gate region 5 and the source n ⁺ region 8. It is difficult to further miniaturize the p ⁺ gate region 5.
In the structure of FIG. 16, it is preferable that the low-concentration n-type drift layer and the low-concentration n-type channel region have the same impurity concentration. The reason for this is that if they have the same concentration, the device design relating to the breakdown voltage, the blocking gain, and the ON characteristics cannot be performed independently. For example, it is possible to improve the blocking characteristics by making the impurity concentration of the low-concentration n-type channel region lower than the impurity concentration of the low-concentration n-type drift layer and to devise to realize a normally-off characteristic This is impossible in the structure of FIG. Thus, the SiC-SIT having the structure shown in FIG. 16 has a limited degree of freedom in device design.
[Non-Patent Document 2]
Moreover, the SiC-SIT structure shown in FIG. 17 has also been proposed. In the same structure, in the formation of the p ⁺ gate region, a box-shaped doping distribution with a depth of 2.5 μm is realized by multi-stage ion implantation of Al up to several MeV. However, in this structure, the low-concentration n-type drift layer and the low-concentration n-type channel region have the same impurity concentration as in the structure of FIG. 16, and this structure limits the degree of freedom in device design. Further, an SiO ₂ film is provided immediately above the metal so that the source electrode metal and the p ⁺ gate region do not come into electrical contact. When the element is turned off, a negative voltage of, for example, −15 V is applied to the gate electrode with respect to the source electrode. However, since most of the applied voltage is to be applied to the SiO ₂ film, if the quality of the SiO ₂ film is low, a problem that reliability of the device is lowered occurs.
Generally, it is known that there are a withstand voltage and an on-resistance as indices representing the performance of the power MOSFET. First, regarding the breakdown voltage, the element breakdown voltage (theoretical breakdown voltage) in an ideal case is determined by the carrier density and thickness of the n ⁻ drift layer. However, the yield phenomenon of SIT is affected by the following factors in addition to the above. First, the height of the potential barrier formed in the channel part decreases with an increase in the drain voltage, and electrons are injected from the source region through the channel to the drain side, so-called electrostatic induction effect (or punch-through phenomenon) ) Can yield. Next, the high-concentration p-type gate region locally breaks down due to an avalanche phenomenon due to local concentration of electric fields at the corners where the low-concentration n-type channel region and the low-concentration n-type drift region are in contact. Therefore, strictly adjusting the width, length, and impurity concentration of the channel region to suppress the decrease in the potential barrier height and the electric field concentration at the corners of the high concentration p-type region can increase the breakdown voltage of the element. is important.
On the other hand, regarding the on-resistance, the channel resistance can be reduced by miniaturizing the element, for example, by shortening the channel length and increasing the channel width per unit area, thereby reducing the on-resistance. However, in this case, the height of the potential barrier formed in the low-concentration n-type channel region is lowered, the above-described electrostatic induction effect is likely to occur, and the breakdown voltage is reduced. At the same time, in the depletion layer extending from the high concentration p + type gate region to the low concentration n type drift region and the low concentration n type channel region, the high concentration p + gate region is both the low concentration n type drift region and the low concentration n type channel region. There is a problem in that the curvature of the depletion layer around the corner in contact with the region increases, the electric field concentration in the high-concentration p-type region corner is promoted, and the withstand voltage decreases.
Further, when an SIT having normally-off characteristics is to be realized, when the voltage V _GS applied to the gate electrode with respect to the source electrode is 0 V, the channel region is pinched off by the depletion layer from the p ⁺ gate region, and the desired It is necessary to form a potential barrier high enough to obtain a breakdown voltage in the channel portion. For this purpose, it is necessary to reduce the concentration of impurities added to the channel part or to reduce the width of the channel part. In the case of normally-off type SIT, the width of the channel portion (hereinafter referred to as “channel width”) is required to be 2 μm or less, and in some cases, designed to be submicron. On the other hand, reducing the channel width and channel impurity concentration in this way increases the on-resistance. Therefore, in order to realize a normally-off type buried gate structure SiC-SIT, it is necessary to optimize the channel structure including the channel width and the channel impurity concentration. Furthermore, in order to reduce the variation in device characteristics after manufacturing and improve the manufacturing yield, the accuracy of the channel width on the submicron order (for example, 0.1 to 0.2 μm or less) is required. At the same time, it is necessary to accurately control the channel impurity concentration.
As described above, in order to realize the normally-off type buried gate structure SiC-SIT, 0.1 is based on the physical phenomenon of the device including the electrostatic induction effect at the time of breakdown and the electric field concentration at the corner of the gate region. There is a need for an element manufacturing method that determines a design method having an accuracy of ˜0.2 μm and accurately reproduces an element structure derived according to this design method.
However, there has been no example in which a normally-off type silicon carbide static induction transistor design method has been shown so far in consideration of complicated physical phenomena in device operation.

US Pat. No. 6,767,783 JP 2008-172007 A JP 2008-177335 A JP 2006-253292 A Table 2007/004528 specification

16th SI Device Symposium SSID-03-2, pp. 7-12, 2003 17th SI Device Symposium SSID-04-7, pp. 41-46, 2004 IEEE Trans. Electron Devices, ED-24, no. 8 pp. 1061-1069, 1977, FIG. 13, 14, 15

It is an object of the present invention to realize a normally-off type buried gate type SiC-SIT that fully draws out the advantages of the electrical characteristics of silicon carbide, has a high breakdown voltage, and a low characteristic on-resistance (R _on S). To do. That is, it is to provide a normally-off type SiC-SIT having a breakdown voltage of 600 V or more and a characteristic on-resistance of 4.0 mΩcm ² or less and a method for manufacturing the same.

In order to solve the above-described problems, a buried gate SiC-SIT according to the present invention includes a first conductivity type high-concentration SiC substrate, a first conductivity type drift layer formed on the high-concentration substrate, and the drift layer. A second conductive type high concentration gate region and a first conductive type low concentration channel region, which are arranged adjacent to each other in a substantially parallel lateral direction, and are formed on the high concentration gate region and the low concentration channel region. A first conductivity type layer; a first conductivity type high concentration source region formed on the first conductivity type layer; a source electrode formed on an uppermost surface of the source region; and a back surface of the high concentration SiC substrate. A transistor structure including a drain electrode formed on the side and a gate electrode connected to a surface exposed portion of the high-concentration gate region. The transistor structure is normally off, and the transistor structure has a conduction characteristic and a breakdown voltage and a characteristic on-resistance of 600 V or more and 4.0 mΩcm ² or less, respectively. The low-concentration channel region is formed so as to have the length, half-width and impurity concentration of the channel layer derived by analyzing the breakdown characteristics by semiconductor device simulation.
The method of manufacturing the buried gate SiC-SIT according to the present invention includes a step of forming a first conductivity type drift layer on a first conductivity type high-concentration SiC substrate, and a second conductivity type high-concentration substrate on the drift layer. A step of forming a concentration gate layer, a step of forming a groove structure on the drift layer by removing the high concentration gate layer with a predetermined width in a substantially parallel lateral direction, and a first on the groove structure. Forming a conductive low concentration channel region; forming a first conductive high concentration source layer on the high concentration gate layer and the low concentration channel region; and a source on the uppermost surface of the high concentration source layer. A step of forming an electrode, a step of forming a drain electrode on the back surface side of the high-concentration SiC substrate, and a step of providing a gate electrode conducting to the surface exposed portion of the high-concentration gate region. The structure of the transistor manufactured by the above process is normally-off type. In addition to the above process, the above-described manufacturing method of the present invention has a breakdown voltage and a characteristic on-resistance of 600 V or more and 4. A simulation step of determining the length, half width and impurity concentration of the low-concentration channel region by semiconductor device simulation so as to have a characteristic of 0 mΩcm ² or less. Then, in the manufacturing method of the present invention, in the step of forming the low-concentration channel region, the low-concentration channel region has the length, half width, and impurity concentration determined by the simulation. A low concentration channel region is formed.

  As described above, according to the present invention, it is possible to realize a normally-off switching element having a low characteristic on-resistance that surpasses a silicon power device at a desired breakdown voltage.

1A and 1B are schematic views showing a cross-sectional structure of a buried gate type SiC-SIT to which the design method of the present invention is applied. FIG. 1A is a perspective view of a quarter cut of the structure. 1B shows the unit structure of the repeating part of FIG. 1A.
FIG. 2 is a schematic diagram showing a device structure used in deriving channel structure parameters such as donor impurity concentration, channel width, and channel length by performing optimal channel design by computer simulation.
3A to 3E are diagrams showing a process for manufacturing a buried gate type SiC-SIT to which the design method of the present invention is applied.
FIG. 4A is a diagram showing the channel doping dependence of R _on S obtained by the above-described simulation using a computer when the half-channel width is changed. FIG. 4B is a diagram showing the channel doping dependence of the breakdown voltage (breakdown voltage) when the half-channel width is changed.
FIG. 5 shows a channel for realizing a normally-off n-channel buried gate SiC-SIT having R _on S of 2.0 mΩcm ² or less and a breakdown voltage of 600 to 1200 V when the channel length is 1, ² , and 3 μm. It is a figure which shows the optimal area | region of a half width and channel doping.
6, the horizontal axis the channel doping concentration N _ch, the vertical axis of the half-width b of the channel region, the upper limit of the specific on-resistance function (straight line 1) and the function related to the lower limit of the breakdown voltage (line 2) in a log-log graph FIG.
FIG. 7 is a diagram showing the relationship between the channel length X _j that is optimum in the present invention and the maximum value (b _MAX ) of the half width b of the channel region when the breakdown voltage is set to 1200V.
8A and 8B, in the case of the channel length X _{j =} 1.5 [mu] m, the breakdown voltage and specific on-resistance to channel donor impurity concentration N _ch, in FIG derived by simulation under conditions of varying half the channel width b is there.
Figure 9 shows in the case of the channel length X _{j =} 1 [mu] m, obtained by simulation, the half width b and a channel doping concentration N design range of _ch of the channel region.
10, among the data of the half-width b and _{N ch} shown in Figure 8B, the half-width b and _{N ch} characteristic ON resistance becomes 2.5Emuomegacm ² or 3Emuomegacm ² is a plot in logarithmic plane.
Figure 11 shows in the case of the channel length _X j = 2.0 .mu.m, obtained by simulation, the half width b and a channel doping concentration _N design range of _ch of the channel region.
Figure 12 is a simulation result of the simulation results and breakdown voltage characteristic ON resistance becomes 2.5Emuomegacm ² is 1200 V, in which half-width b is the vertical axis and N _ch is displayed in a log-log graph is the horizontal axis.
FIG. 13 shows a simulation result in which the characteristic on-resistance is 4.0 mΩcm ² and a simulation result in which the breakdown voltage is 1200 V in a log-log graph in which the half width b is the vertical axis and N _ch is the horizontal axis. .
FIG. 14 shows the straight lines 1 and 2 of FIG. 6 displayed in FIG.
FIG. 15 is a diagram that defines only an effective design region of the channel structure of the buried gate type SiC-SIT of the present invention that does not include a problem region.
FIG. 16 is a schematic diagram showing a cross-sectional structure of the surface gate electrode structure SiC-SIT disclosed in Non-Patent Document 1.
FIG. 17 is a schematic diagram showing a cross-sectional structure of SiC-SIT disclosed in Non-Patent Document 2.

1 ... Drain electrode 2 ... on SiC substrate (drain region)
DESCRIPTION OF SYMBOLS 3 ... Drift layer 4 ... Channel region 5 ... Gate region 6 ... Gate electrode 7 ... N-type layer 8 ... Source region 9 ... Source electrode

Embodiments of the present invention will be described below with reference to the accompanying drawings. Half width b and length X _{j of} a channel region necessary for realizing a normally-off type buried gate SiC-SIT having a breakdown voltage of 600 V or more and a characteristic on-resistance of 4.0 mΩcm ² or less. The donor impurity concentration _Nch is determined.
FIG. 1 is a schematic diagram of a cross-sectional structure of SiC-SIT to which the design method of the present invention is applied. FIG. 1A shows a quarter cut, and FIG. 1B shows a unit structure of a repeating portion. In comparison with FIG. 16 showing the structure of the conventional SIT, this structure shows that the SIT assumed by the present invention has an n-type layer on the gate region, and the gate region is completely buried. I understand.
The channel structure to be realized by the present invention is determined by two-dimensional device simulation based on the drift diffusion model. In this simulation, it is assumed that the device structure shown in FIG. Here, the symbol a represents the half gate width, and the symbol b represents the half channel width. The symbol X _j is the channel length, and the symbol N _ch represents the channel doping concentration. The device structure shown in FIG. 2 is a structure used in the simulation, and includes a drain region 2 using the drain electrode 1 as an extraction electrode, a drift layer 3 that relaxes an electric field between the drain region 2 and the channel region 4, and a channel region 3. A gate region 5 for controlling the current flowing through the gate region 6, a gate electrode 6 that is an extraction electrode from the gate region 5, an n-type layer 7 provided between the channel region 4 and the source region 8, and an extraction electrode from the source region 8. A certain source electrode 9 is provided. Here, for the sake of simulation, the gate electrode 6 is provided on the side wall of the gate region 5. Since the n-type layer 7 and the channel region 4 can be formed with the same composition, they can be formed separately or integrally.
3A to 3E are schematic views of a manufacturing process of a buried gate type SiC-SIT which is an object of the present invention. FIG. 3E shows the completed device of the present invention. The channel region 4 is formed not only in the trench between the p ⁺ gate layer 5 and the p ⁺ gate layer 5, but also between the p ⁺ gate layer 5 and the source region 8, and the above-described device structure shown in FIG. A function as the n-type layer 7 is also provided.
First, (a) the n ⁻ drift layer 3 and the p ⁺ gate layer 5 are epitaxially grown on the high-concentration n-type 4H—SiC substrate 2 (FIG. 3A).
Next, (b) dry etching, the n ^- separating the removed central portion of the p ⁺ gate layer 5 p ⁺ gate layer 5 as the surface of the drift layer 3 is exposed at a predetermined interval (Fig. 3B). By this step, a fine groove structure is formed on the n ⁻ drift layer 3. When manufacturing the SiC-SIT of FIG. 1A, the p ⁺ gate layer 5 is removed at a predetermined interval in the substantially parallel lateral direction by the step (b), and the stripe-shaped groove is the n ⁻ drift layer 3 described above. Periodically formed on top. Since the element characteristics are substantially determined by the dimensions determined in this etching process (p ⁺ gate region width x (= 2a), adjacent p ⁺ gate region interval y (= 2b), channel length X _j ), it is constant. In order to realize the device characteristics, it is important to perform this etching process with good reproducibility.
On this groove structure, (c) n ⁻ channel region 4 is formed by epitaxial growth (FIG. 3C). Normally, epitaxial growth is performed on a flat substrate. However, by optimizing the crystal orientation of the SiC substrate and the epitaxial growth conditions (temperature, gas flow rate, etc.), epitaxial growth on a fine groove structure is possible. When the SiC-SIT of FIG. 1 is manufactured, the p ⁺ gate layer 5 and the channel region 4 are periodically adjacent to each other in the substantially parallel lateral direction on the n ⁻ drift layer 3 by the step (c). Arranged.
Thereafter, (d) n ⁺ source region 8 is formed by ion implantation, and after activation heat treatment (for example, 1600 ° C.) (FIG. 3D), (e) source electrode 9 and drain electrode 1 are formed (FIG. 3E). The inventive device is completed. In the buried gate type SiC-SIT device manufactured in this way, the p ⁺ gate region 5 is completely buried, and the n ⁻ channel region is interposed between the p ⁺ gate regions 5 and 5 adjacent to each other at a predetermined interval in the horizontal direction. 4 is formed.
In the element design process by semiconductor device simulation, the mesh interval is set finely, especially in locations where electric field concentration occurs and in the channel region that is important for SIT operation, so that avalanche breakdown and electrostatic induction effects can be simulated accurately. Devised. Assuming that the crystal structure of the semiconductor material is 4-period hexagonal SiC (4H-SiC), in order to obtain accurate simulation results, the physical properties of the material such as carrier mobility, band gap and ionization coefficient are 4H-SiC experiments. A model formula fitted with data is used.
A clear design technique for the SIT channel structure has not yet been established. However, as in Non-Patent Document 3, the channel structure is often determined based on the width of the depletion layer based on the complete depletion approximation of the semiconductor pn junction. The complete depletion approximation assumes that the concentration of electrons and holes in the depletion layer is zero when deriving the electric field and potential distribution inside the depletion layer formed at the junction such as a semiconductor pn junction. The calculation is carried out assuming a fully depleted situation.
However, there is a transition region at the boundary between the depletion layer and the non-depletion layer of the actual semiconductor pn junction. Therefore, the finer the channel structure, the worse the design accuracy when using the full depletion approximation. Furthermore, the avalanche breakdown phenomenon is a phenomenon due to the process in which carriers generated in the depletion layer get energy from the electric field of the same layer and collide with electrons in the valence band, and the electrons become free electrons, so that the full depletion approximation When is used, it is difficult to accurately determine the breakdown voltage of the element.
Therefore, when designing a normally-off type buried gate SiC static induction transistor that requires sub-micron-order fine dimensional accuracy using the conventional design method using the above-mentioned complete depletion approximation, the manufacturing yield is significantly reduced. Can be easily predicted.
On the other hand, the simulation used in the present invention does not use perfect depletion approximation. That is, the half-width b of the channel region, relates length X _j and a donor impurity concentration N _ch, limit line indicating the upper and lower limits can achieve an object of the present invention, conduction characteristics and breakdown characteristics of the normally-off SiC-SIT Is derived by analyzing the semiconductor device simulation. For the semiconductor device simulation, the Poisson equation, the electron continuity equation, and the hole continuity equation, which are basic equations of the semiconductor, are discretized by the finite difference method and solved using the Newton method. Then, under the condition of half width b and the channel length X _j of the various channel region, characteristic ON-resistance and breakdown voltage for the channel donor impurity concentration N _ch using the formula of solutions obtained from these equations is simulated, These upper and lower limit lines are derived. Today, software for performing such semiconductor simulation is commercially available, and anyone who purchases it can use it. However, in order to accurately analyze a target semiconductor device and establish a more accurate design method, the following matters are required.
First, it is necessary to accurately grasp physical properties such as carrier mobility, avalanche multiplication factor, and forbidden bandwidth of semiconductor device materials (for example, Si and SiC) to be simulated, and to incorporate these physical properties into the simulator. It is. These physical property values complicatedly depend on the density of impurities added to the semiconductor, the plane orientation of the semiconductor, and the temperature. In the case of Si semiconductors, since the history of research and development is long, anyone can easily obtain reliable physical property data. On the other hand, since SiC has a short development history, many accurate physical property data on SiC have not been clarified. Therefore, the simulation is repeated by fitting the model formula based on the measured physical property data into the simulator so that the simulation results match the characteristics of the actual device. It is necessary to improve the accuracy.
Next, as a general semiconductor simulation technique, a finite difference method or a finite element method is used. At this time, there is a process of dividing the target device structure region with a mesh. According to the numerical analysis theory, if the mesh interval is set finely, the calculation error decreases, but the simulation time increases. For this reason, in a normal semiconductor simulation, a so-called non-uniform mesh is generated in which a mesh interval is finely set in a region where the carrier distribution and the electric field strength change are large in the device region, and a mesh is coarsely set in other regions. Such a mesh setting is used to prevent the total number of meshes from becoming too large in the entire analysis region.
In addition, when it has a complicated operation principle including electrostatic induction effect and electric field concentration at the gate area corner, such as normally-off type buried gate structure SiC-SIT handled in the present invention, the operation is accurately reproduced. It will be necessary to arrange the mesh so that it can. Finally, as in determining physical property values, the mesh adjustment is repeatedly performed so that the simulation result matches the actual device characteristics.
In the present invention, in order to obtain an accurate simulation result in consideration of the above, based on the experimental result, parameters in the model formulas of carrier mobility and avalanche multiplication coefficient, which are physical properties specific to SiC material, are determined and fitted. Work is performed and highly accurate physical property values are incorporated into the simulator.
Further, in mesh generation, it is necessary to accurately analyze the electric field concentration and electrostatic induction effect (punch-through phenomenon) generated at the gate corner portion at the time of breakdown, and the carrier flow in the channel and drift region at the time of ON.
Therefore, in the present invention, the lower right corner portion of the p ⁺ gate region 5 in the device structure of FIG. 2, the portion where the region 5 and the drift region 3 are in contact, the side wall portion of the p ⁺ gate region 5, the channel region 4, the drift region 3. In the substrate region 2 or the like, a mesh profile relating to the device structure of FIG. 2 is created and evaluated by the fitting operation in the same manner as in the case of adjusting the physical property values described above. By using this method, it is possible to accurately analyze the complex element operation mechanism including the electrostatic induction effect that occurs at the time of breakdown and the electric field concentration at the gate corner, so that the problem of the perfect depletion approximation is solved and the accuracy is high. The channel part can be designed.
That is, each of the half-width b of the channel region satisfying the lower limit of the upper and breakdown voltage characteristics on-resistance of interest, by two-dimensional device simulation based on drift-diffusion model using a computer, the channel length X _j and channel doping concentration N _It is determined as a function of _ch . Then, represents the upper limit of the specific on-resistance of interest, represents a graph of the half-width b of the channel region as a function of the channel length X _j and the doping concentration N _ch, the lower limit of the breakdown voltage, the channel length X _j and doping identifying a region surrounded by the graph of half-width b of the channel region as a function of the concentration N _ch. This specified region is an effective design range of the channel structure of the buried gate type SiC-SIT of the present invention.

と表される。ここでｑは素電荷（Ｃ）、ε_ｓは半導体の比誘電率、ε_０は真空の誘電率（Ｆ／ｃｍ）、Ｖ_ｂｉはゲート領域５とチャネル領域４の接合間の内蔵電位（Ｖ）、Ｖ_ａｐｐはソース端子に対してゲート端子に印加する電圧（Ｖ）である。
図５に示されたＷ_ｄｅｐ（０Ｖ）の解析値およびＷ_ｄｅｐ（２．５Ｖ）の解析値に関する直線は、上記Ｗ_ｄｅｐ（Ｖ_ａｐｐ）の解析値の式を使用して求めた従来設計手法によるものである。
すなわち、Ｗ_ｄｅｐ（０Ｖ）及びＷ_ｄｅｐ（２．５Ｖ）に関する上記関係式を満足する領域、すなわち、図５のＷ_ｄｅｐ（０Ｖ）及びＷ_ｄｅｐ（２．５Ｖ）の直線で囲まれた領域が、解析的手法に基づく従来の手法による有効な設計範囲であり、空乏層ではキャリアがゼロであると仮定する完全空乏近似に基づいて、Ｎチャネルノーマリーオフ埋め込みゲートＳｉＣ−ＳＩＴを設計できる範囲である。
これに対して、下記に説明する図５中のハッチングで示された領域は本願発明の埋込ゲート型ＳｉＣ−ＳＩＴのチャネル構造の有効な設計範囲である。この設計領域の導出は、上述した完全空乏近似に基づく従来の設計手法ではなく、上述したような半導体シミュレーションによる厳密な素子解析により導出したものである。
すなわち、上記したように、実デバイスの電気的特性データを使用しながら図２のデバイス構造についてフィッティング作業によってメッシュのプロファイルを作成し、該作成されたプロファイルを用いたシミュレーションにおいて、物性値を調整するためのフィッティング作業を繰り返した。このようにして得られた精度の高い半導体シミュレータを用いて、（ｉ）及び（ｉｉ）のように不純物ドーピングされている場合において上記の特性を有するノーマリーオフ型のＳｉＣ−ＳＩＴのチャネル構造の設計範囲を導出した。
具体的には、上記の特性を有するノーマリーオフ型のＳｉＣ−ＳＩＴのチャネル構造は、チャネルドーピングとチャネル幅の組み合わせが、チャネルドーピング（×１０^１６ｃｍ^−３）及びチャネル幅（μｍ）を両対数表示したグラフにおいて、
（ｉ） チャネル長が１μｍの場合には、
Ａ（１．４、０．２２）、Ｂ（３．０、０．２２）、Ｃ（１．８、０．３０）、Ｄ（０．７、０．３０）の各点をＡ−Ｂ−Ｃ−Ｄ−Ａと順に結ぶ領域（領域１）内であり、
（ｉｉ） チャネル長が２μｍの場合には、
Ｅ（４．０、０．２４）、Ｆ（２．０、０．２４）、Ｇ（０．６、０．４８）の各点をＥ−Ｆ−Ｇ−Ｅと順に結ぶ領域（領域ＩＩ）内であり、
（ｉｉｉ） チャネル長が３μｍの場合には、
Ｈ（０．３、０．５３）、Ｉ（０．６、０．５３）、Ｊ（１．８、０．３８）、Ｋ（２．３、０．３）、Ｌ（０．９，０．３）、Ｍ（０．５３、０．３８）の各点をＨ−Ｉ−Ｊ−Ｋ−Ｌ−Ｍ−Ｈと順に結ぶ領域（領域ＩＩＩ）内になるように設計すれば良いことが分かる。
図５において、完全空乏近似に基づく従来設計手法による有効な設計範囲内においても、本願発明の有効な設計範囲から外れる領域が顕著に存在することがわかる。このことから、チャネル構造を正確に決定するためには，従来設計手法では不十分であり、本願発明の設計手法の有効性が確認できる。
［実施例２］
降伏電圧が１２００Ｖ以上であり、かつ特性オン抵抗が４．０ｍΩｃｍ^２以下の特性を有するノーマリーオフ型のＳｉＣ−ＳＩＴを実現するのに必要なチャネル領域の半幅ｂ、チャネル長さＸ_ｊ、チャネルドーピング濃度Ｎ_ｃｈに関する設計範囲を上記シミュレーションにより求める。
このためには、チャネルドーピング濃度Ｎ_ｃｈを横軸、チャネル領域の半幅ｂを縦軸として、特性オン抵抗の上限に関する以下の式（１）及び降伏電圧の下限に関する以下の式（２）の２つの式を両対数グラフに表示して、式（１）及び式（２）で囲まれる領域内に存在するドナー不純物濃度Ｎ_ｃｈ及びチャネルの半幅ｂの組合せ（Ｎ_ｃｈ，ｂ）を決定する。
一方、上記組合せ（Ｎ_ｃｈ，ｂ）のうち、次の式（３）によって与えられるｂ_ＭＡＸ以下の半幅ｂを有するように、チャネル長さＸ_ｊを決定する必要がある。

ここで、図６において、直線１及び２は、上記の式（１）及び式（２）をそれぞれ示す。図７の曲線１は、降伏電圧が１２００Ｖに設定された場合におけるチャネル長さＸ_ｊと、半幅ｂの上限値との関係を示す上記の式（３）を示す。
図６及び図７に示される各々の限界線は、上記した半導体デバイスシミュレーションによるノーマリーオフ型のＳｉＣ−ＳＩＴの導通特性および降伏特性を解析することによって得られた。すなわち、半導体の基本方程式であるＰｏｉｓｓｏｎ式、電子の連続方程式、正孔の連続方程式を有限差分法で離散化し、ニュートン法を用いて解いた後、得られた解を用いて上記の導通特性および降伏特性をシミュレートし、シミュレート結果を解析した。また、本発明による式（３）は、特にドレイン電極とゲート電極の両電極からの静電誘導効果のチャネル領域の電位障壁への相互作用およびｐ^＋ゲート領域のコーナー部での電界集中を正確にシミュレーションすることによって得られたものである。
後述するように、式（１）乃至式（３）に基づいて上記の方法によって決定された組合せ（Ｎ_ｃｈ，ｂ）及びチャネル長さＸ_ｊは、本願発明の目的とするＳｉＣ−ＳＩＴを実現するチャネル構造の有効な設計範囲を特定する。
図６及び図７に示される各限界線を求めるためには、まず図８Ａ及び図８Ｂに示されるように、チャネルドーピング濃度Ｎ_ｃｈに対する降伏電圧および特性オン抵抗を、様々な半チャネル幅ｂおよびチャネル長Ｘ_ｊの条件の下でシミュレーションにより導出する。
図８Ａではノーマリーオフ特性を考慮して、ゲート‐ソース間電圧Ｖ_ＧＳ＝０Ｖを設定している。一方、図８Ｂの計算では上記のＶ_ＧＳは、素子をオンする為の入力信号である２．５Ｖを設定しており、ドレイン電流密度が２００Ａ／ｃｍ^２の時のドレイン‐ソース間電圧Ｖ_ＤＳによって特性オン抵抗Ｒ_ｏｎＳを計算している。ここでＶ_ＧＳを２．５Ｖに設定しているのは、Ｖ_ＧＳを十分大きくし、図２に示すチャネル領域４に広がる空乏層の幅を小さくし、可能な限りＲ_ｏｎＳを低減するように意図している。またＶ_ＧＳを３．０Ｖ以上とするとｐ^＋ゲート領域５からホールがチャネル領域４およびドリフト領域３に注入されるため、ターンオフ時間が著しく増加する恐れがある。よってＶ_ＧＳを、ｐ^＋ゲート領域５からホールが注入されない上限である２．５Ｖに設定している。尚、図８Ａ及び図８Ｂにおいて、Ｘ_ｊ＝１．５μｍとしている。他のＸ_ｊに関しても図８Ａ及び図８Ｂと同様の解析を行った。
図８Ｂの特性オン抵抗対Ｎ_ｃｈの関係図ではＮ_ｃｈの減少と共に初めは徐々に特性オン抵抗が増加することがわかる。この理由は、Ｎ_ｃｈの減少と共に、ｐ^＋ゲート領域からチャネルに広がる空乏層の幅が増加するため、チャネル中の非空乏化領域である伝導チャネルの実効幅が徐々に減少するためである。
そして、あるＮ_ｃｈでは特性オン抵抗が急激に増加していることが図８Ｂから確認できる。これはチャネルの両側のｐ^＋ゲート領域５からの空乏層によってチャネル領域が完全に空乏化しそこに電位障壁が形成されるため、電流が著しく減少するためである。
このように特性オン抵抗を急激に増加させる値のＮ_ｃｈが、ノーマリーオフ型のＳｉＣ−ＳＩＴを導通させるための下限値であり、この素子に導通機能を持たせるためには、この下限値より大きい値でＮ_ｃｈを設計することが必要となる。また下限値は半幅ｂに依存していることが図８Ｂでわかる。
図８Ｂに示された半幅ｂ及びＮ_ｃｈのデータのうち、特性オン抵抗が２．５ｍΩｃｍ^２或いは３ｍΩｃｍ^２になる半幅ｂ及びＮ_ｃｈを両対数平面にプロットすると、半幅ｂが０．４μｍ未満の範囲において同じ傾きを持った２つの実線が得られる（図１０）。
一方、図８Ａの降伏電圧対Ｎ_ｃｈの関係図では、Ｎ_ｃｈを増加させると、あるＮ_ｃｈの値で急激に降伏電圧が低下していることがわかる。これは、Ｎ_ｃｈの増加により、ｐ^＋ゲート領域５からチャネル領域４に広がる空乏層の幅が減少し、電流を遮断するための電位障壁が低下するためである。
この降伏電圧が急激に低下するときのチャネル不純物濃度が、素子が確実にオフ機能を持つためのチャネル不純物濃度の上限値である。この上限値の値は半幅ｂが増加するに従い減少していくことが図８Ａより分かる。
この結果を踏まえ、降伏電圧が１２００Ｖになる半幅ｂ及びＮ_ｃｈを両対数平面にプロットすると、図９及び図１０に示される点線に示される降伏電圧の上限（Ｌｉｍｉｔ ｏｆ Ｖ_ＢＲ（１２００Ｖ））となる。ここでＮ_ｃｈの減少にともない点線が直線から外れその勾配が緩やかになり、最終的に、半幅ｂがＮ_ｃｈに依存しなくなるのは以下の２つの理由がある。一つはＮ_ｃｈの増加に伴い半幅ｂを増加させようとした場合、ドレイン電極からの静電誘導効果が顕著に働くようになり、Ｎ_ｃｈを減少してもノーマリーオフ特性を維持するのに十分な高さの電位障壁を形成できなくなる。これはＮ_ｃｈが減少するほど空乏層端における電界強度が低くなり、電位障壁を形成しにくくなるからである。他の一つは、Ｎ_ｃｈの減少により半幅ｂを増加させようとした場合、ｐ^＋ゲート領域５のコーナーにおける電界集中が促進され、降伏電圧が減少する傾向を示すためである。
結果として、降伏電圧が１２００Ｖになる半幅ｂ及びＮ_ｃｈを両対数平面にプロットすると、図９および図１０に示されるように、Ｎ_ｃｈが低い値になる程、曲線の勾配が緩やかになり、最終的に半幅ｂの値はＮ_ｃｈに依存しなくなる。図１０において、降伏電圧Ｖ_ＢＲが１２００Ｖになる半幅ｂ及びＮ_ｃｈの曲線は、Ｎ_ｃｈの低い側において一点鎖線で示す半幅ｂ＝０．４５μｍに漸近していることが分かる。すなわち、降伏電圧Ｖ_ＢＲを所定の大きさ、例えば、１２００Ｖに設定した場合、Ｎ_ｃｈが低い範囲において、Ｎ_ｃｈの大きさに依存しない半幅ｂの上限値ｂ_ＭＡＸが存在する。尚、チャネル長さＸ_ｊ＝１．５μｍの場合、降伏電圧Ｖ_ＢＲが１２００Ｖに等しいという条件を満たす最大の半チャネル幅、すなわち、半幅ｂ_ＭＡＸは０．４５μｍになる。
このように、図８Ａから求められた、降伏電圧が１２００Ｖになる半幅ｂ及びＮ_ｃｈの両対数平面上の曲線には、ドレイン電圧による静電誘導効果とゲート領域コーナーでの電界集中が強く作用することによって決まる、Ｎ_ｃｈに依存しない半幅ｂの上限が存在することも考慮する必要がある。この効果は、従来の完全空乏近似によって導出することは困難であり、本願発明において用いた半導体デバイスシミュレーション手法によって正確に導出することが可能となる。
Ｎ_ｃｈに依存しない半幅ｂの上限値であるｂ_ＭＡＸは、上記したドリフト拡散モデルに基づく２次元デバイスシミュレーションによってチャネル構造を設計する際の一つのパラメータとして考慮される必要がある。そのため、上記の半幅ｂ_ＭＡＸを、上記のシミュレーションによって、チャネル長さＸ_ｊ及び降伏電圧の関数として決定する必要がある。
図９及び図１１はそれぞれ、チャネル長Ｘ_ｊ＝１μｍ及びチャネル長Ｘ_ｊ＝２μｍの場合において上記シミュレーションによって得られた設計範囲を示す。これらのチャネル長の場合、半幅ｂ_ＭＡＸは、それぞれ０．３５μｍ及び０．５μｍである。
次に、図１２乃至図１４に示されるように、図９乃至図１１に記載されたシミュレーション結果を用いて、目的とする特性オン抵抗の上限及び降伏電圧Ｖ_ＢＲの下限を満たすチャネル領域の半幅ｂを、チャネル長さＸ_ｊ及びＮ_ｃｈの関数として表す。尚、半幅ｂ_ＭＡＸはＮ_ｃｈに依存しないが、チャネル長さＸ_ｊの関数として扱うことができる。
本願発明において、上記チャネル構造の有効な設計範囲は、図７に示された任意のチャネル長さＸ_ｊに関し、この曲線によって与えられる半幅の上限値ｂ_ＭＡＸと、上記のシミュレーションによって得られた特性オン抵抗の曲線、降伏電圧の曲線によって囲まれる領域である。例えば、図１２によれば、Ｘ_ｊ＝１μｍにおけるＲ_ｏｎＳ曲線、降伏電圧Ｖ_ＢＲ≧１２００Ｖの曲線およびｂ＝半幅ｂ_ＭＡＸ（＝０．３５））で囲まれる領域内の（Ｎ_ｃｈ，ｂ）の組が、上記の有効な設計範囲である。同様にして、図１２のＸ_ｊ＝１．５μｍ及びＸ_ｊ＝２．０μｍにおける有効な設計範囲も、上記のＲ_ｏｎＳ曲線と、降伏電圧Ｖ_ＢＲ曲線或いはｂ＝半幅ｂ_ＭＡＸで囲まれる領域内の（Ｎ_ｃｈ，ｂ）の組として定義される。
図１３は、チャネル長さＸ_ｊ＝１μｍ、１．５μｍ及び２μｍに関し、Ｒ_ｏｎＳ≦４．０ｍΩｃｍ^２、Ｖ_ＢＲ≧１２００Ｖの条件を満たす半幅ｂ及びＮ_ｃｈのシミュレーション結果を示す。図１３に示された、チャネル長さＸ_ｊ＝１μｍ、１．５μｍ及び２μｍの各Ｒ_ｏｎＳ曲線は、ほぼ直線状であるので、これらの曲線は同一の直線、すなわち、図６の直線２によって近似することができる。一方、図１３に示された、チャネル長さＸ_ｊ＝１μｍ、１．５μｍ及び２μｍの各降伏電圧Ｖ_ＢＲ曲線は、Ｎ_ｃｈ＞２．０×１０^１６（ｃｍ^−３）の高濃度側で一つの直線に収束している。上記の降伏電圧Ｖ_ＢＲ曲線がＮ_ｃｈの高濃度側で収束する当該直線は、図６の直線１によって近似することができる。
図１４は、上記Ｒ_ｏｎＳ曲線の近似直線及び上記降伏電圧Ｖ_ＢＲ曲線の近似曲線を図１３上に、追加的に示した図である。直線１及び直線２は、チャネル長さＸ_ｊ＝２．０（μｍ）における降伏電圧Ｖ_ＢＲ曲線及びＲ_ｏｎＳ曲線を比較的に良く近似している。
しかし、チャネル長さＸ_ｊが小さくなるに従い、直線１とｂ＝半幅ｂ_ＭＡＸが交差する近傍の領域において、降伏電圧Ｖ_ＢＲ曲線は、直線１及びｂ＝半幅ｂ_ＭＡＸの直線から乖離している。このような乖離した領域、すなわち、降伏電圧Ｖ_ＢＲ曲線と、直線１及びｂ＝半幅ｂ_ＭＡＸの直線で囲まれる領域（以下、「問題領域」という。）は、本願発明の目的とするＳｉＣ−ＳＩＴを実現するチャネル構造を実現できない。
この問題領域は上述したように、ＳＩＴの降伏時におけるｐ^＋ゲート領域５のコーナーにおける電界集中およびドレイン電界による静電誘導効果に伴うチャネル領域の電位障壁の低下に起因するものであり、ＳＩＴの設計特有のものである。すなわちこの問題領域を排除した有効な設計領域を定義することが、所望の降伏電圧を有し電力損失の低いノーマリーオフ型埋め込みゲートＳｉＣ−ＳＩＴの設計において重要になる。
本願発明では、問題領域を含まない下記の様な設計領域を提案する。すなわち図１５の横軸Ｎ_ｃｈ、縦軸ｂの両対数平面において、直線１、直線２、直線３、直線４で囲まれる領域を有効な設計領域とするものである。ここで直線４は点Ｒ（β，ｂ_ＭＡＸ）および点Ｑ（α，ｂ_ＭＡＸ−０．１）を通る直線であり、下記の式で与えられる。
ｂ＝Ａ×Ｎ_ｃｈ ^ｘ ・・・（４）
ここでＡおよびｘは下記で与えられる。

図１４に示されたシミュレーションの結果に基づき、点Ｒは、図１４の降伏電圧Ｖ_ＢＲ曲線が直線ｂ＝ｂ_ＭＡＸと交わる点および、点Ｑは降伏電圧Ｖ_ＢＲ曲線が直線１から乖離する点として導出されている。直線４は、点Ｒと点Ｑの間の降伏電圧Ｖ_ＢＲ曲線を直線で近似したものである。従って、直線１と直線３と直線４で囲まれた領域が問題領域となる。式（４）においてＡおよびｘはｂ_ＭＡＸの関数として与えられるので、任意のＸ_ｊに対して式（３）によってｂ_ＭＡＸが与えられ、これによって式（４）から直線４を求めることができる。この直線４と直線１、直線２、直線３で囲まれた領域によって、問題領域を含まない有効な設計領域を定義することができる。Hereinafter, a channel structure design method in the buried gate type SiC-SIT manufacturing method according to the first and second embodiments will be described in detail.
[Example 1]
In the case where each region of the device structure of FIG. 2 is doped as shown in (i) and (ii) below, normally-off having a breakdown voltage of 600 to 1200 V and a characteristic on-resistance of ² mΩcm ² or less. A channel structure for manufacturing a type SiC-SIT is obtained by the above simulation.
(I) The dopant of the source region 8 is nitrogen or phosphorus, the doping concentration is 2.0 × 10 ²⁰ cm ⁻³ , the doping concentration of the drain 2 is 1 × 10 ¹⁹ cm ⁻³ , and the dopant of the gate region 5 is aluminum or Boron doping is 2.0 × 10 ¹⁸ cm ⁻³ .
(Ii) The thickness of the drift layer 3 is 8.5 μm, the doping concentration of the n-type layer 7 between the channel 4 and the source region 8 is 1.3 × 10 ¹⁶ cm ⁻³ , and the thickness is 1 .1 μm. The dopant of the drift layer 3 and the n-type layer 7 is nitrogen or phosphorus.
FIG. 4A shows the channel doping dependence of R _on S obtained by the above-described simulation using a computer for each of half-channel widths of 0.3, 0.375, 0.45, and 0.5 μm. . In this case, the channel length _Xj is 1.0 μm. It can be seen that R _on S increases as the half channel width b decreases and as the channel doping concentration decreases.
FIG. 4B shows the channel doping dependence of the breakdown voltage (breakdown voltage) obtained in the same manner when the half channel width is 0.2, 0.3, and 0.45 μm. Similar to the above, the channel length _Xj is 1.0 μm. It can be seen that the breakdown voltage increases with decreasing half channel width and with decreasing channel doping concentration. 4A and 4B, the channel doping concentration N _ch (cm ⁻³ ) is logarithmically expressed.
Similar simulations were performed for other channel lengths. FIG. 5 shows an example of realizing an N-channel normally-off buried gate SiC-SIT having a R _on S of 2.0 mΩcm ² or less and a breakdown voltage of 600 V to 1200 V for each of the channel lengths of 1 μm, 2 μm, and 3 μm. The channel structure, that is, the optimum region of channel width and channel doping concentration is shown. Note that the channel doping concentration (cm ⁻³ ) on the horizontal axis and the channel width (μm) on the vertical axis in FIG.
In order to realize a normally-off transistor, it is necessary that the gate voltage is 0 V and the channel is completely depleted. Therefore, when the width of the depletion layer when the gate voltage is 0 V is expressed as W _dep (0 V), The following conditions are required.
0.5 × W _dep (0V)> b
On the other hand, since a non-depletion region needs to exist in the channel during the on operation (2.5 V), the width of the depletion layer when the gate voltage is 2.5 V is expressed as W _dep (2.5 V) Conditions are required.
0.5 × W _dep (2.5V) <b
In the analysis method using the conventional complete depletion approximation, the expression of the analysis value of W _dep (V _app ) is

It is expressed. Here, q is an elementary charge (C), ε _s is a relative dielectric constant of the semiconductor, ε ₀ is a vacuum dielectric constant (F / cm), and V _bi is a built-in potential between the gate region 5 and the channel region 4 (V ), V _app is a voltage (V) applied to the gate terminal with respect to the source terminal.
The straight line relating to the analysis value of W _dep (0V) and the analysis value of W _dep (2.5V) shown in FIG. 5 is obtained by using the conventional design method of the analysis value of W _dep (V _app ). Is due to.
That _{is, W} dep (0V) and _W dep (2.5V) relates to satisfy the above relational expression region, that is, a region surrounded by a straight line _W in FIG. 5 dep (0V) and _W dep (2.5V) This is an effective design range based on the conventional method based on the analytical method, and within a range in which the N-channel normally-off buried gate SiC-SIT can be designed based on the complete depletion approximation assuming that the carrier is zero in the depletion layer. is there.
On the other hand, the area shown by hatching in FIG. 5 described below is an effective design range of the channel structure of the buried gate type SiC-SIT of the present invention. This design area is derived not by the conventional design method based on the complete depletion approximation described above, but by a strict element analysis based on the semiconductor simulation as described above.
That is, as described above, a mesh profile is created by fitting work for the device structure of FIG. 2 while using the electrical characteristic data of the actual device, and the physical property values are adjusted in the simulation using the created profile. The fitting work for was repeated. Using the semiconductor simulator with high accuracy obtained in this way, the channel structure of the normally-off type SiC-SIT having the above characteristics in the case of impurity doping as in (i) and (ii). The design range was derived.
Specifically, in the normally-off type SiC-SIT channel structure having the above characteristics, the combination of channel doping and channel width has both channel doping (× 10 ¹⁶ cm ⁻³ ) and channel width (μm). In the logarithmic graph,
(I) When the channel length is 1 μm,
Each point of A (1.4, 0.22), B (3.0, 0.22), C (1.8, 0.30), D (0.7, 0.30) is represented by AB -C-D-A in the region (region 1) in order,
(Ii) When the channel length is 2 μm,
A region (region II) in which each point of E (4.0, 0.24), F (2.0, 0.24), and G (0.6, 0.48) is connected to EFGE in order. )
(Iii) When the channel length is 3 μm,
H (0.3, 0.53), I (0.6, 0.53), J (1.8, 0.38), K (2.3, 0.3), L (0.9, 0.3) and M (0.53, 0.38) should be designed so as to be within a region (region III) connecting HI-J-K-L-M-H in order. I understand.
In FIG. 5, it can be seen that even within the effective design range by the conventional design method based on the complete depletion approximation, there is a significant region outside the effective design range of the present invention. From this, the conventional design method is insufficient to accurately determine the channel structure, and the effectiveness of the design method of the present invention can be confirmed.
[Example 2]
Half width b of channel region, channel length X _j , channel required for realizing normally-off type SiC-SIT having a breakdown voltage of 1200 V or more and a characteristic on-resistance of 4.0 mΩcm ² or less The design range regarding the doping concentration _Nch is obtained by the above simulation.
For this purpose, the channel doping concentration N _ch of the horizontal axis, the vertical axis of the half-width b of the channel region, 2 in the following expression for the lower limit of the formula (1) and the breakdown voltage of the upper limit of the specific on-resistance (2) Two equations are displayed in a log-log graph to determine the combination (N _ch , b) of the donor impurity concentration N _ch and the channel half width b existing in the region surrounded by the equations (1) and (2).
On the other hand, in the combination (N _ch , b), it is necessary to determine the channel length X _j so as to have a half width b equal to or less than b _MAX given by the following equation (3).

Here, in FIG. 6, straight lines 1 and 2 indicate the above formulas (1) and (2), respectively. Curve 1 in FIG. 7 shows the above equation (3) showing the relationship between the channel length _Xj and the upper limit value of the half width b when the breakdown voltage is set to 1200V.
Each of the limit lines shown in FIGS. 6 and 7 was obtained by analyzing the conduction characteristics and the breakdown characteristics of normally-off SiC-SIT by the semiconductor device simulation described above. That is, the Poisson equation, the electron continuity equation, and the hole continuity equation, which are basic equations of the semiconductor, are discretized by the finite difference method and solved using the Newton method. The yield characteristics were simulated and the simulation results were analyzed. Further, the expression (3) according to the present invention accurately corrects the interaction of the electrostatic induction effect from both the drain electrode and the gate electrode to the potential barrier of the channel region and the electric field concentration at the corner of the p ⁺ gate region. It was obtained by simulation.
As will be described later, the combination (N _ch , b) and the channel length X _j determined by the above method based on the equations (1) to (3) realize the SiC-SIT that is the object of the present invention. The effective design range of the channel structure is specified.
To determine the respective limit line shown in FIG. 6 and 7, first, as shown in FIGS. 8A and 8B, the breakdown voltage and specific on-resistance to channel doping concentration N _ch, various semi channel width b and Derived by simulation under the condition of channel length _Xj .
In FIG. 8A, the gate-source voltage V _GS = 0V is set in consideration of normally-off characteristics. On the other hand, in the calculation of FIG. 8B, the above-described V _GS is set to 2.5 V, which is an input signal for turning on the element, and the drain-source voltage V _DS when the drain current density is 200 A / cm ^2. Is used to calculate the characteristic on-resistance R _on S. The reason why V _GS is set to 2.5 V here is to increase V _GS sufficiently, reduce the width of the depletion layer extending in channel region 4 shown in FIG. 2, and reduce R _on S as much as possible. Is intended. If V _{GS is set} to 3.0 V or more, holes are injected from the p ⁺ gate region 5 into the channel region 4 and the drift region 3, so that the turn-off time may be significantly increased. Therefore, V _GS is set to 2.5 V, which is the upper limit at which holes are not injected from the p ⁺ gate region 5. In FIGS. 8A and 8B, X _j = 1.5 μm. For the other X _j , the same analysis as in FIGS. 8A and 8B was performed.
Beginning with decreasing N _ch in relation diagram of characteristic ON resistance versus N _ch in Figure 8B gradually understood that the characteristic ON-resistance is increased. This is because, with decreasing N _ch, the width of the depletion layer spreading from the p ⁺ gate region to the channel is increased, because the effective width of the non-depleted region in which the conduction channel in the channel is gradually reduced.
Then, it is N _ch in specific on-resistance is rapidly increased can be confirmed from FIG. 8B. This is because the channel region is completely depleted by the depletion layers from the p ⁺ gate regions 5 on both sides of the channel and a potential barrier is formed there, so that the current is significantly reduced.
The value N _ch that rapidly increases the characteristic on-resistance in this way is a lower limit value for conducting normally-off SiC-SIT, and this lower limit value is required in order for this element to have a conduction function. It is necessary to design _Nch with a larger value. It can be seen from FIG. 8B that the lower limit value depends on the half width b.
Of half-width b and _{N ch} data shown in Figure 8B, when plotting the half-width b and _{N ch} characteristic ON resistance becomes 2.5Emuomegacm ² or 3Emuomegacm ² in double logarithmic plane, half-width b is less than 0.4μm Two solid lines with the same slope in the range are obtained (FIG. 10).
On the other hand, in the relation diagram of the breakdown voltage versus N _ch in Figure 8A, increasing the N _ch, it is understood that the rapid breakdown voltage value of a N _ch is lowered. This is an increase of N _ch, the width of the depletion layer spreading from the p ⁺ gate region 5 in the channel region 4 is decreased is because the potential barrier for breaking current decreases.
The channel impurity concentration when the breakdown voltage rapidly decreases is the upper limit value of the channel impurity concentration for ensuring that the device has an off function. It can be seen from FIG. 8A that the upper limit value decreases as the half width b increases.
Based on this result, when plotting the half-width b and _{N ch} breakdown voltage is 1200V in logarithmic plane, the upper limit of the breakdown voltage shown in the dotted line shown in FIG. 9 and FIG. _{10 (Limit of V BR (1200V} )) and Become. Here becomes moderate its gradient dotted line deviates from a straight line with the reduction of N _ch, finally, the half-width b does not depend on N _ch has the following two reasons. If one were try to increase the half-width b with increasing N _ch, static induction effect from the drain electrode is to work significantly, to maintain the normally-off characteristics even reduce N _ch Therefore, it becomes impossible to form a sufficiently high potential barrier. This field strength is low at the edge of the depletion layer as a decrease in N _ch, because becomes difficult to form a potential barrier. The other is, when it is attempted to increase the half-width b by lower N _ch, electric field concentration is promoted at the corner of the p ⁺ gate region 5, the breakdown voltage is to show a tendency to decrease.
As a result, when the half width b and N _{ch at} which the breakdown voltage is 1200 V are plotted on the logarithmic plane, as shown in FIGS. 9 and 10, the slope of the curve becomes gentler as N _ch becomes lower, Finally, the value of the half width b does not depend on _Nch . In FIG. 10, it can be seen that the curves of the half width b and N _ch at which the breakdown voltage V _BR becomes 1200 V are asymptotic to the half width b = 0.45 μm indicated by the alternate long and short dash line on the lower side of N _ch . That is, when the breakdown voltage V _BR is set to a predetermined magnitude, for example, 1200 V, there is an upper limit value b _{MAX of the} half width b that does not depend on the magnitude of N _{ch in} a range where N _ch is low. When the channel length X _j = 1.5 μm, the maximum half channel width that satisfies the condition that the breakdown voltage V _BR is equal to 1200 V, that is, the half width b _MAX is 0.45 μm.
Thus, obtained from Figure 8A, the curve on the log-log plane half width b and N _ch of breakdown voltage is 1200 V, the drain voltage electric field concentration is strong action of an electrostatic induction effect and the gate region corners by determined by, it is necessary to consider the upper limit of half width b that is independent of the N _ch is present. This effect is difficult to derive by the conventional complete depletion approximation, and can be accurately derived by the semiconductor device simulation technique used in the present invention.
B _MAX is the upper limit of the half width b that is independent of the N _ch has to be considered as one of the parameters in designing a channel structure by a two-dimensional device simulation based on drift-diffusion model described above. Therefore, it is necessary to determine the half width b _MAX as a function of the channel length X _j and the breakdown voltage by the above simulation.
9 and 11 show the design ranges obtained by the above simulation when the channel length X _j = 1 μm and the channel length X _j = 2 μm, respectively. For these channel lengths, the half width b _MAX is 0.35 μm and 0.5 μm, respectively.
Next, as shown in FIGS. 12 to 14, the half-width by using the simulation results described in FIGS. 9 to 11, the channel region satisfying the lower limit of the upper and the breakdown voltage V _BR of the specific on-resistance for the purpose Let b be a function of channel length X _j and N _ch . Incidentally, the half-width _{b MAX} does not depend on _{N ch,} it can be treated as a function of the channel length _{X j.}
In the present invention, the effective design range of the channel structure is related to the arbitrary channel length X _j shown in FIG. 7 and the upper limit value b _{MAX of the} half width given by this curve, and the characteristics obtained by the above simulation. It is a region surrounded by an on-resistance curve and a breakdown voltage curve. For example, according to FIG. 12, the R _on S curve at X _j = 1 μm, the curve with breakdown voltage V _BR ≧ 1200 V, and b = (N _ch , b in the region surrounded by half width b _MAX (= 0.35)) ) Is the above-mentioned effective design range. Similarly, the effective design range at X _j = 1.5 μm and X _j = 2.0 μm in FIG. 12 is also a region surrounded by the R _on S curve and the breakdown voltage V _BR curve or b = half width b _{MAX. Are} defined as a set of (N _ch , b).
13, channel length _X j = 1 [mu] m, relates 1.5μm and 2 [mu] _m, show simulation results for satisfying half width b and _{N ch} of ^{_{R on S ≦ 4.0mΩcm 2, V}} BR ≧ 1200V. Since the R _on S curves of channel lengths X _j = 1 μm, 1.5 μm and 2 μm shown in FIG. 13 are almost linear, these curves are the same straight line, ie, straight line 2 in FIG. Can be approximated by On the other hand, the breakdown voltage V _BR curves of channel lengths X _j = 1 μm, 1.5 μm, and 2 μm shown in FIG. 13 are on the high concentration side of N _ch > 2.0 × 10 ¹⁶ (cm ⁻³ ). It converges to one straight line. The straight line breakdown voltage V _BR curve described above converge at the high concentration side of N _ch can be approximated by a straight line 1 of Figure 6.
FIG. 14 is a diagram additionally showing an approximate line of the R _on S curve and an approximate curve of the breakdown voltage V _BR curve on FIG. The straight line 1 and the straight line 2 approximate the breakdown voltage V _BR curve and R _on S curve relatively well in the channel length X _j = 2.0 (μm).
However, in accordance with the channel length _{X j} is small, in the region of the vicinity of the straight line 1 and b = half-width _{b MAX} intersect, the breakdown voltage _{V BR} curve is deviated from the straight line of the straight line 1 and b = half width _{b MAX} . Such a divergence region, that is, a region surrounded by a breakdown voltage V _BR curve and a straight line 1 and a straight line of b = half width b _MAX (hereinafter referred to as “problem region”) is SiC− which is an object of the present invention. A channel structure that realizes SIT cannot be realized.
As described above, this problem region is caused by the electric field concentration at the corner of the p ⁺ gate region 5 at the breakdown of the SIT and the lowering of the potential barrier of the channel region due to the electrostatic induction effect due to the drain electric field. Design-specific. In other words, defining an effective design area that eliminates this problem area is important in designing a normally-off buried gate SiC-SIT having a desired breakdown voltage and low power loss.
The present invention proposes the following design areas that do not include problem areas. That is, in the logarithmic planes of the horizontal axis N _ch and the vertical axis b in FIG. 15, the area surrounded by the straight line 1, the straight line 2, the straight line 3, and the straight line 4 is an effective design area. Here, the straight line 4 is a straight line passing through the point R (β, b _MAX ) and the point Q (α, b _MAX −0.1), and is given by the following equation.
b = A × N _ch ^x (4)
Where A and x are given below.

Based on the simulation results shown in FIG. 14, point R is the point where the breakdown voltage V _BR curve of FIG. 14 intersects the straight line b = b _MAX , and point Q is the point where the breakdown voltage V _BR curve deviates from the straight line 1. As derived. The straight line 4 is obtained by approximating the breakdown voltage V _BR curve between the point R and the point Q with a straight line. Therefore, the area surrounded by the straight line 1, the straight line 3 and the straight line 4 becomes a problem area. Since A and x are given as a function of b _{MAX in} the equation (4), b _MAX is given by the equation (3) for any X _j , and thus the straight line 4 can be obtained from the equation (4). . An effective design region that does not include the problem region can be defined by the region surrounded by the straight line 4, the straight line 1, the straight line 2, and the straight line 3.

  It is known that the buried gate SiC-SIT can be used in a high temperature environment or a radiation environment, and the transistor according to the present invention can also be operated in a harsh environment. The embedded gate SiC-SIT can improve the power conversion efficiency of various power conversion circuits such as an inverter circuit and a power supply circuit as compared with the case where a conventional Si power device is used. In addition, the power converter can be easily downsized. Furthermore, it is known that it can be used in a high-temperature environment or a radiation environment, and can be operated in a harsh environment.

Claims (8)

A first conductivity type high-concentration SiC substrate, a first conductivity type drift layer formed on the high-concentration substrate, and a second conductivity type arranged adjacent to each other in a substantially parallel lateral direction on the drift layer A high concentration gate region and a first conductivity type low concentration channel region, a first conductivity type layer formed on the high concentration gate region and a low concentration channel region, and a first conductivity type layer A first conductivity type high-concentration source region; a source electrode formed on the uppermost surface of the source region; a drain electrode formed on the back side of the high-concentration SiC substrate; and a surface exposed portion of the high-concentration gate region A transistor structure comprising a gate electrode connected to
It was obtained by fitting the model expression of the physical property value incorporated in the simulation to the simulator so that the result of simulation by incorporating the measured physical property data in the simulator and the measured value of the actual device characteristics match. Using a fitted simulator, the low concentration channel region is designed and
The transistor structure has a normally-off type, and the transistor structure has a breakdown voltage and a characteristic on-resistance of 600 V or more and 4.0 mΩcm 2 or less, respectively. The low-concentration channel region is formed so as to have the length, half-width, and impurity concentration of the channel layer derived by analyzing the semiconductor device simulation using the fitted simulator.
Embedded gate SiC-SIT. Of the channel region data derived by the semiconductor device simulation,
A set of channel length X _j , channel doping N _ch and half width b of the channel region, the transistor structure being configurable to have an upper limit R _on S (mΩcm ² ) and a lower limit breakdown voltage V _BR (V) only data consisting of, performs a log-log plot of channel doping N _ch the horizontal axis and the half-width b as the vertical axis,
Each common channel length X _j is manufactured in a log-log plane region surrounded by a contour formed by connecting the log-plotted channel doping N _ch and half-width b coordinate points. Item 3. The buried gate SiC-SIT according to Item 1. Of the channel region data derived by the semiconductor device simulation,
Half-channel width b data wherein the transistor structure has an upper limit characteristic on-resistance R _on S;
Half-channel width b data in which the transistor structure has a lower breakdown voltage V _BR ;
The data of the maximum half channel width b _MAX in which the transistor structure has the lower breakdown voltage V _BR ,
_{Represent as} a function of channel length X _j and N _ch respectively
Half channel width b and b _MAX above, and plotted on a logarithmic plane channel doping N _ch the horizontal axis and the half-width b as the vertical axis,
For each common channel length X _j , a line segment formed by connecting the coordinate points of the half channel width b data having R _on S,
For each common channel length X _j , a line segment formed by connecting coordinate points of the data of the half channel width b having the V _BR ,
A set (X _j , N _ch , N x, N _ch , which depends on the channel length X _j and does not depend on N _ch and exists in a region surrounded by the horizontal boundary line b = half width b _MAX in the above logarithmic plane. The buried gate SiC-SIT according to claim 1, comprising a channel region configured using the data of b). For the data of the channel region derived by the semiconductor device simulation of the horizontal channel doping concentration N _ch axis, the vertical axis of the half-width b of the channel region, when being displayed on a log-log graph, the following equation (1) to ( 4) by the channel length enclosed, semi channel width and channel doping pairs (X _{j, b,} characterized in that it comprises a channel region formed by using the data of N _ch), according to claim 1 Embedded gate SiC-SIT.
b = 4.56 × 10 ⁷ / (N _ch ) ^1/2 (1)
b = 2.74 × 10 ⁷ / (N _ch ) ^1/2 (2)
b _MAX = 0.109 + 0.290X _j -0.0455X _j ² (3)
b = A × N _ch ^x (4)
However,

Forming a first conductivity type drift layer on the first conductivity type high-concentration SiC substrate;
Forming a second conductivity type high concentration gate layer on the drift layer;
By removing the high-concentration gate layer with a predetermined width in a substantially parallel lateral direction,
Forming a groove structure on the drift layer;
Forming a first conductivity type low-concentration channel region on the groove structure;
Forming a high-concentration source layer of a first conductivity type on the high-concentration gate layer and the low-concentration channel region;
Forming a source electrode on the uppermost surface of the high concentration source layer;
Forming a drain electrode on the back side of the high-concentration SiC substrate;
Providing a drain electrode conducting to the surface exposed portion of the high-concentration gate region;
A method of manufacturing a buried gate SiC-SIT having:
Fitting the model formula of the physical property value incorporated in the simulation so that the result of simulation by incorporating the measured physical property data into the simulator and the measured value of the actual device characteristics match,
Using the simulator obtained by the above fitting process so that the transistor has a normally-off structure, and the breakdown voltage and characteristic on-resistance of the structure have characteristics of 600 V or more and 4.0 mΩcm ² or less, respectively. Including a simulation step of determining a length, a half width and an impurity concentration of the low-concentration channel region in a semiconductor device simulation,
In the step of forming the low concentration channel region, the low concentration channel region is formed under the condition that the low concentration channel region has the length, half width, and impurity concentration determined by the simulation. And
Manufacturing method of buried gate SiC-SIT. The simulation process includes
Deriving data comprising a set of channel length X _j , channel doping concentration N _ch, and half width b of the channel region that can be configured such that the static induction transistor has an upper limit R _on S and a lower breakdown voltage V _BR. And a process of
The derived data, the channel doping concentration N _ch of the horizontal axis and the half-width b as the vertical axis, and performing plotted logarithmic plane,
For each common channel length X _j, by connecting the coordinate points of the channel doping concentration is a log-log plot N _ch and half width b, and that includes a step of forming a closed area in the log-log plane Features
A method for manufacturing a buried gate type silicon carbide static induction transistor according to claim 5. The simulation process includes
Half-channel width b data in which the electrostatic induction transistor has an upper limit characteristic on-resistance R _on S, half-channel width b data in which the static induction transistor has a lower-limit breakdown voltage V _BR , and the electrostatic induction Representing the data of the maximum half-channel width b _MAX for which the transistor has a lower breakdown voltage V _BR as a function of the channel length X _j and N _ch , respectively;
Half channel width b and b _MAX above, the step of plotting on the logarithmic plane channel doping N _ch the horizontal axis and the half-width b as the vertical axis,
For each common channel length X _j , a line segment formed by connecting the coordinate points of the half channel width b data having R _on S,
For each common channel length X _j , a line segment formed by connecting coordinate points of the data of the half channel width b having the V _BR ,
Without depending on N _ch, depending on the channel length X _j, present in the region surrounded by said logarithmic plane horizontal boundary line to be b = half width b _MAX in a double logarithmic plane above, by the set ( Identifying the data of X _j , N _ch , b);
Including,
A method for manufacturing a buried gate SiC-SIT according to claim 5. The simulation process includes
The data of the channel region derived by the semiconductor device simulation, and displaying the channel doping concentration N _ch horizontal axis, the vertical axis of the half-width b of the channel region, the log-log graph,
Of the data of the channel region displayed in the log-log graph, the channel length, half channel width and channel doping group (X _j , b, N _ch ) surrounded by the following equations (1) to (4) Identifying the data;
Including,
A method for manufacturing a buried gate SiC-SIT according to claim 5.
b = 4.56 × 10 ⁷ / (N _ch ) ^1/2 (1)
b = 2.74 × 10 ⁷ / (N _ch ) ^1/2 (2)
b _MAX = 0.109 + 0.290X _j -0.0455X _j ² (3)
b = A × N _ch ^x (4)
However,

Images