JPWO2011001847A1 - Electro copper plating solution for ULSI fine copper wiring embedding - Google Patents
Electro copper plating solution for ULSI fine copper wiring embedding Download PDFInfo
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
- C25D7/0607—Wires
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
微細化が進むＵＬＳＩ微細銅配線（ダマシン銅配線）形成において、銅シード層上に電気銅めっきを実施する際の銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁のボイドの発生を抑制することのできる電気銅めっき液を提供することを目的とする。本発明は、ｐＨが１．８以上３．０以下であることを特徴とするＵＬＳＩ微細配線埋め込み用電気銅めっき液である。該めっき液は炭素数が１以上４以下の飽和カルボン酸を０．０１ｍｏｌ／Ｌ以上２．０ｍｏｌ／Ｌ以下含むことが好ましい。In the formation of finer ULSI fine copper wiring (damascene copper wiring), dissolution of the copper seed layer when performing electrolytic copper plating on the copper seed layer is suppressed, resulting in the formation of voids on the inner walls of the via trench. An object is to provide an electrolytic copper plating solution that can be suppressed. The present invention is an electrolytic copper plating solution for embedding ULSI fine wiring, wherein the pH is 1.8 or more and 3.0 or less. The plating solution preferably contains 0.01 to 2.0 mol / L of saturated carboxylic acid having 1 to 4 carbon atoms.
Description
本発明は、ＵＬＳＩ微細銅配線埋め込み用電気銅めっき液に関する。 The present invention relates to an electrolytic copper plating solution for embedding ULSI fine copper wiring.
ＵＬＳＩ微細配線埋め込み用電気銅めっきは、通常硫酸ベースの強酸性めっき液（ｐＨ１．２以下）を用いて行われている。その際のシード層としてスパッタ銅膜が使用されているが、配線の微細化によりトレンチ・ビア内のスパッタ銅膜が極薄化してきている。シード層最表面は電気めっき前の状態では大気中に曝されているため酸化が避けられないが、電気めっき液が強酸性であるため酸性めっき液浸漬時に、シード層の酸化された部分が容易に溶解し、薄いシード層に欠陥が発生し、その後電気銅めっきにより銅配線層を形成した際に所々銅めっきの抜けが生じる問題がある。特にトレンチ・ビア内側壁にボイドが発生し易く問題となっている。 Electrolytic copper plating for embedding ULSI fine wiring is usually performed using a strongly acidic plating solution (pH 1.2 or less) based on sulfuric acid. A sputtered copper film is used as a seed layer at that time, but the sputtered copper film in the trench and via has become extremely thin due to the miniaturization of the wiring. Oxidation is inevitable because the outermost surface of the seed layer is exposed to the atmosphere before electroplating, but the electroplating solution is strongly acidic, so the oxidized portion of the seed layer is easily immersed in the acidic plating solution When the copper wiring layer is formed by electrolytic copper plating, there is a problem that the copper plating is lost in some places. In particular, voids are likely to occur on the inner wall of the trench / via.
本発明はますます微細化が進むＵＬＳＩ微細銅配線（ダマシン銅配線）形成において、銅シード層上に電気銅めっきを実施する際の銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁のボイドの発生を抑制することのできる電気銅めっき液を提供することを目的とする。 The present invention suppresses dissolution of the copper seed layer when electro copper plating is performed on the copper seed layer in the formation of finer ULSI fine copper wiring (damascene copper wiring), resulting in the inner wall of the via trench. An object of the present invention is to provide an electrolytic copper plating solution capable of suppressing the generation of voids.
本発明者らは、通常の硫酸ベースの強酸性の銅めっき液に用いる硫酸の代わりにカルボン酸等を用いることでめっき液のｐＨを通常の強酸性から弱酸性気味にすることにより、めっき液浸漬時の銅シード層の溶解し易さを抑制することを試みた。その結果、硫酸ベースの強酸性めっき液使用時に発生していたトレンチ側壁のボイドが、カルボン酸ベースのめっき液を使用することにより無くなり、上記課題が解決されることを見出し本発明に至った。 By changing the pH of the plating solution from normal strong acid to weak acidity by using carboxylic acid or the like instead of sulfuric acid used in a normal sulfuric acid-based strong acid copper plating solution, the present inventors An attempt was made to suppress the ease of dissolution of the copper seed layer during immersion. As a result, the inventors found that the voids in the trench sidewalls that were generated when using the sulfuric acid-based strong acid plating solution were eliminated by using the carboxylic acid-based plating solution, thereby solving the above-mentioned problems.
即ち、本発明は以下のとおりである。
（１）ｐＨが１．８以上３．０以下であることを特徴とするＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（２）ｐＨが２．０以上２．２以下であることを特徴とする前記（１）記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（３）炭素数が１以上４以下の飽和カルボン酸を０．０１ｍｏｌ／Ｌ以上２．０ｍｏｌ／Ｌ以下含むことを特徴とする前記（１）又は（２）記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（４）前記カルボン酸が酢酸であることを特徴とする前記（３）記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（５）前記（１）〜（４）のいずれかに記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液を用いたことを特徴とするＵＬＳＩ微細配線用電気銅めっき方法。
（６）前記（５）記載のＵＬＳＩ微細配線用電気銅めっき方法によりＵＬＳＩ微細配線が形成されたことを特徴とするＵＬＳＩ微細配線基板。That is, the present invention is as follows.
(1) An electrolytic copper plating solution for embedding ULSI fine wiring, wherein the pH is 1.8 or more and 3.0 or less.
(2) The electrolytic copper plating solution for embedding ULSI fine wiring according to (1) above, wherein the pH is 2.0 or more and 2.2 or less.
(3) The electrolytic copper for embedding ULSI fine wiring according to (1) or (2) above, comprising a saturated carboxylic acid having 1 to 4 carbon atoms in an amount of 0.01 mol / L to 2.0 mol / L Plating solution.
(4) The electrolytic copper plating solution for embedding ULSI fine wiring according to (3), wherein the carboxylic acid is acetic acid.
(5) An electrolytic copper plating method for ULSI fine wiring, characterized in that the electrolytic copper plating solution for embedding ULSI fine wiring according to any one of (1) to (4) is used.
(6) A ULSI fine wiring board, wherein a ULSI fine wiring is formed by the electrolytic copper plating method for ULSI fine wiring described in (5) above.
ＵＬＳＩ微細銅配線（ダマシン銅配線）形成において、銅シード層上に本発明の電気銅めっき液用いて銅配線層を形成することにより、銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁ボイドの発生を抑制することができる。 In the formation of ULSI fine copper wiring (damascene copper wiring), the copper wiring layer is formed on the copper seed layer by using the electrolytic copper plating solution of the present invention, thereby suppressing the dissolution of the copper seed layer. Generation of wall voids can be suppressed.
本発明のＵＬＳＩ微細配線埋め込み用電気銅めっき液は、ｐＨ１．８以上３．０以下である。通常の硫酸ベースの銅めっき液では、ｐＨ１．２以下の強酸となるが、硫酸の代わりに酢酸等のカルボン酸を用いることでめっき液のｐＨを１．８以上３．０以下とすることができる。ｐＨ１．８以上３．０以下とすることにより、銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁ボイドの発生を抑制することが可能となった。ｐＨは２．０以上２．２以下がより好ましい。
ｐＨが１．８未満であると、ｐＨが低いため銅シード層が溶解し易くなり、その結果ボイドも発生し易くなる。また、ｐＨが３．０よりも大きい場合、めっき液中の銅イオンが酸化物あるいは水酸化物となって、沈殿が発生する恐れがある。The electrolytic copper plating solution for embedding ULSI fine wiring of the present invention has a pH of 1.8 to 3.0. In a normal sulfuric acid-based copper plating solution, a strong acid having a pH of 1.2 or less is obtained, but by using a carboxylic acid such as acetic acid instead of sulfuric acid, the pH of the plating solution may be adjusted to 1.8 to 3.0. it can. By adjusting the pH to 1.8 or more and 3.0 or less, dissolution of the copper seed layer can be suppressed, and as a result, generation of voids in the inner wall of the via / trench can be suppressed. The pH is more preferably 2.0 or more and 2.2 or less.
When the pH is less than 1.8, the copper seed layer is easily dissolved because the pH is low, and as a result, voids are easily generated. Moreover, when pH is larger than 3.0, there exists a possibility that the copper ion in a plating solution may turn into an oxide or a hydroxide, and precipitation may generate | occur | produce.
前記カルボン酸としては、めっき液に溶解しｐＨを上記範囲内とすることができるものであればどのようなカルボン酸でも良く、好ましくはギ酸、酢酸、プロピオン酸、酪酸、シュウ酸等の炭素数１以上４以下の飽和カルボン酸であり、特に酢酸が好ましい。
カルボン酸はめっき液中、０．０１〜２．０ｍｏｌ／Ｌ含有されることが好ましく、より好ましくは０．２〜１．０ｍｏｌ／Ｌである。めっき液中のカルボン酸の濃度は埋め込み性、及びｐＨに影響し、カルボン酸の濃度が２．０ｍｏｌ／Ｌを超えるとめっき液のｐＨが１．８未満まで下がり、ボイドが発生し易くなる。また、カルボン酸のめっき液中の濃度が０．０１ｍｏｌ／Ｌ未満であると、めっき液のｐＨが３．０を超え、上述のように沈殿が発生する恐れがある。The carboxylic acid may be any carboxylic acid as long as it can be dissolved in the plating solution and have a pH within the above range, preferably carbon number such as formic acid, acetic acid, propionic acid, butyric acid, oxalic acid, etc. 1 to 4 saturated carboxylic acid, with acetic acid being particularly preferred.
Carboxylic acid is preferably contained in the plating solution in an amount of 0.01 to 2.0 mol / L, more preferably 0.2 to 1.0 mol / L. The concentration of the carboxylic acid in the plating solution affects the embedding property and the pH. When the concentration of the carboxylic acid exceeds 2.0 mol / L, the pH of the plating solution decreases to less than 1.8 and voids are likely to occur. Moreover, when the density | concentration in the plating solution of carboxylic acid is less than 0.01 mol / L, pH of a plating solution exceeds 3.0 and there exists a possibility that precipitation may generate | occur | produce as mentioned above.
本発明の電気銅めっき液は水溶液であり、その他の成分としては、銅塩、塩素イオン、微量添加剤等が挙げられ、それぞれ公知のものでよく特に制限はない。
銅塩としては、硫酸銅、硝酸銅、塩化銅などが挙げられ、硫酸銅が好ましい。銅塩はめっき液中０．０５〜１．５ｍｏｌ／Ｌ含有されることが好ましく、より好ましくは０．２〜０．８ｍｏｌ／Ｌである。
塩素イオン濃度はめっき液中０．３〜３．０ｍｍｏｌ／Ｌ含有されることが好ましく、より好ましくは１．０〜２．０ｍｍｏｌ／Ｌである。The electrolytic copper plating solution of the present invention is an aqueous solution, and other components include copper salts, chloride ions, trace additives, etc., and each may be a known one without any particular limitation.
Examples of the copper salt include copper sulfate, copper nitrate, copper chloride and the like, and copper sulfate is preferable. The copper salt is preferably contained in the plating solution in an amount of 0.05 to 1.5 mol / L, more preferably 0.2 to 0.8 mol / L.
The chloride ion concentration is preferably 0.3 to 3.0 mmol / L in the plating solution, and more preferably 1.0 to 2.0 mmol / L.
微量添加剤としては、促進剤、抑制剤、平滑剤等が挙げられる。
促進剤としては二硫化ビス（３−スルホプロピル）二ナトリウム、３−メルカプトプロパンスルホン酸等が挙げられ、めっき液中１〜３０ｍｇ／Ｌ含有されることが好ましい。
抑制剤としては、ポリエチレングリコール、ポリプロピレングリコール、及びこれらの共重合体等が挙げられ、めっき液中１０〜５００ｍｇ／Ｌ含有されることが好ましい。
平滑剤としては、ヤヌスグリーンＢ、ポリエチレンイミン、ポリビニルピロリドン等が挙げられ、めっき液中０．１〜５０ｍｇ／Ｌ含有されることが好ましい。Examples of the trace additive include an accelerator, an inhibitor, and a smoothing agent.
Examples of the accelerator include bis (3-sulfopropyl) disodium disulfide, 3-mercaptopropanesulfonic acid, and the like, and it is preferable to contain 1 to 30 mg / L in the plating solution.
Examples of the inhibitor include polyethylene glycol, polypropylene glycol, and copolymers thereof, and it is preferably contained in the plating solution in an amount of 10 to 500 mg / L.
Examples of the smoothing agent include Janus Green B, polyethyleneimine, polyvinylpyrrolidone and the like, and it is preferably contained in the plating solution in an amount of 0.1 to 50 mg / L.
また、本発明の電気銅めっき液を用いためっきは、浴温２０〜３０℃で行うのが、浴安定性および銅の析出速度の点から好ましく、また、カソード電流密度は０．１〜５Ａ／ｄｍ２で行うことが好ましい。In addition, the plating using the electrolytic copper plating solution of the present invention is preferably performed at a bath temperature of 20 to 30 ° C. from the viewpoint of bath stability and copper deposition rate, and the cathode current density is 0.1 to 5 A. / Dm 2 is preferable.
電気銅めっきを行う被めっき材としては、半導体ウェハーなど微細配線基板となるものであり、トレンチ・ビア等のＵＬＳＩ微細配線付きのシリコン基板の表面に銅シード層を設けたものが好ましい。
銅シード層は、スパッタ法、無電解めっき法等の公知の方法で形成されたものでよい。
本発明の電気銅めっき液を用いてめっきを行うことにより、トレンチ・ビア内の銅シード層の厚さが２ｎｍ、又はそれ以下であっても、ボイドが発生することなくめっきすることができる。The material to be subjected to electrolytic copper plating is a fine wiring substrate such as a semiconductor wafer, and a silicon seed layer provided on the surface of a silicon substrate with ULSI fine wiring such as a trench and a via is preferable.
The copper seed layer may be formed by a known method such as a sputtering method or an electroless plating method.
By plating using the electrolytic copper plating solution of the present invention, plating can be performed without generating voids even if the thickness of the copper seed layer in the trench and via is 2 nm or less.
実施例１
以下に示すめっき液を用いて、ＵＬＳＩ微細配線付きシリコン基板上に電気銅めっきを行った。被めっき材であるシリコン基板には微細なトレンチパターン（線幅１８０ｎｍ、深さ５００ｎｍ）が付いていて、最表面にはスパッタ法によりＣｕシード層が形成されている。そのＣｕシード層膜厚は、トレンチ内最薄部で２ｎｍであった。
めっき液組成：
銅（硫酸銅） ０．６３ｍｏｌ／Ｌ
酢酸 ０．５ｍｏｌ／Ｌ
ＨＣｌ １．４ｍｍｏｌ／Ｌ
二硫化ビス（３−スルホプロピル）二ナトリウム １０ｍｇ／Ｌ
ポリプロピレングリコール ８０ｍｇ／Ｌ
ポリビニルピロリドン １０ｍｇ／Ｌ
ｐＨ ２．１
２５℃、１Ａ／ｄｍ２で３０秒間めっきを実施した。
断面ＳＥＭ観察の結果を図１に示す。トレンチ側壁部も含めてボイドの発生は全く無かった。Example 1
Using the plating solution shown below, electrolytic copper plating was performed on a silicon substrate with ULSI fine wiring. A silicon substrate, which is a material to be plated, has a fine trench pattern (line width 180 nm, depth 500 nm), and a Cu seed layer is formed on the outermost surface by sputtering. The Cu seed layer thickness was 2 nm at the thinnest part in the trench.
Plating solution composition:
Copper (copper sulfate) 0.63 mol / L
Acetic acid 0.5 mol / L
HCl 1.4mmol / L
Bis (3-sulfopropyl) disodium disulfide 10mg / L
Polypropylene glycol 80mg / L
Polyvinylpyrrolidone 10mg / L
pH 2.1
Plating was performed at 25 ° C. and 1 A / dm 2 for 30 seconds.
The result of cross-sectional SEM observation is shown in FIG. There was no void at all including the trench side wall.
実施例２
以下に示すめっき液を用いて、ＵＬＳＩ微細配線付きシリコン基板上に電気銅めっきを行った。被めっき材であるシリコン基板は実施例１と同様で、Ｃｕシード層膜厚は、トレンチ内最薄部で２ｎｍであった。
めっき液組成：
銅（硫酸銅） ０．６３ｍｏｌ／Ｌ
ギ酸 １．０ｍｏｌ／Ｌ
ＨＣｌ １．４ｍｍｏｌ／Ｌ
二硫化ビス（３−スルホプロピル）二ナトリウム １０ｍｇ／Ｌ
ポリプロピレングリコール ８０ｍｇ／Ｌ
ポリビニルピロリドン １０ｍｇ／Ｌ
ｐＨ １．９
２５℃、１Ａ／ｄｍ２で３０秒間めっきを実施した。
断面ＳＥＭ観察の結果、トレンチ側壁部も含めてボイドの発生は全く無かった。Example 2
Using the plating solution shown below, electrolytic copper plating was performed on a silicon substrate with ULSI fine wiring. The silicon substrate as the material to be plated was the same as in Example 1, and the Cu seed layer thickness was 2 nm at the thinnest part in the trench.
Plating solution composition:
Copper (copper sulfate) 0.63 mol / L
Formic acid 1.0 mol / L
HCl 1.4mmol / L
Bis (3-sulfopropyl) disodium disulfide 10mg / L
Polypropylene glycol 80mg / L
Polyvinylpyrrolidone 10mg / L
pH 1.9
Plating was performed at 25 ° C. and 1 A / dm 2 for 30 seconds.
As a result of cross-sectional SEM observation, no voids were generated including the trench side wall.
実施例３
以下に示すめっき液を用いて、ＵＬＳＩ微細配線付きシリコン基板上に電気銅めっきを行った。被めっき材であるシリコン基板は、Ｃｕシード層膜厚が、トレンチ内最薄部で１．８ｎｍである以外は実施例１と同様であった。
めっき液組成：
銅（硫酸銅） ０．６３ｍｏｌ／Ｌ
シュウ酸 ０．１ｍｏｌ／Ｌ
ＨＣｌ １．４ｍｍｏｌ／Ｌ
二硫化ビス（３−スルホプロピル）二ナトリウム １０ｍｇ／Ｌ
ポリプロピレングリコール ８０ｍｇ／Ｌ
ポリビニルピロリドン １０ｍｇ／Ｌ
ｐＨ ２．５
２５℃、１Ａ／ｄｍ２で３０秒間めっきを実施した。
断面ＳＥＭ観察の結果、トレンチ側壁部も含めてボイドの発生は全く無かった。Example 3
Using the plating solution shown below, electrolytic copper plating was performed on a silicon substrate with ULSI fine wiring. The silicon substrate as the material to be plated was the same as in Example 1 except that the Cu seed layer thickness was 1.8 nm at the thinnest part in the trench.
Plating solution composition:
Copper (copper sulfate) 0.63 mol / L
Oxalic acid 0.1 mol / L
HCl 1.4mmol / L
Bis (3-sulfopropyl) disodium disulfide 10mg / L
Polypropylene glycol 80mg / L
Polyvinylpyrrolidone 10mg / L
pH 2.5
Plating was performed at 25 ° C. and 1 A / dm 2 for 30 seconds.
As a result of cross-sectional SEM observation, no voids were generated including the trench side wall.
比較例１
めっき液組成を以下のように変更した以外は実施例１と同様に電気銅めっきを実施した。
めっき液組成：
銅（硫酸銅） ０．６３ｍｏｌ／Ｌ
硫酸 ０．５ｍｏｌ／Ｌ
ＨＣｌ １．４ｍｍｏｌ／Ｌ
二硫化ビス（３−スルホプロピル）二ナトリウム １０ｍｇ／Ｌ
ポリプロピレングリコール ８０ｍｇ／Ｌ
ポリビニルピロリドン １０ｍｇ／Ｌ
＜ｐＨ１．０
断面ＳＥＭ観察の結果を図２に示す。少なくとも一部のトレンチ側壁部にボイド（円内の黒い影部）の発生が観察された。Comparative Example 1
Copper electroplating was performed in the same manner as in Example 1 except that the plating solution composition was changed as follows.
Plating solution composition:
Copper (copper sulfate) 0.63 mol / L
Sulfuric acid 0.5 mol / L
HCl 1.4mmol / L
Bis (3-sulfopropyl) disodium disulfide 10mg / L
Polypropylene glycol 80mg / L
Polyvinylpyrrolidone 10mg / L
<PH 1.0
The result of cross-sectional SEM observation is shown in FIG. The generation of voids (black shadows in the circle) was observed on at least a part of the trench side wall.
【０００２】
［０００５］
即ち、本発明は以下のとおりである。
（１）飽和カルボン酸を０．０１ｍｏｌ／Ｌ以上２．０ｍｏｌ／Ｌ以下含み、ｐＨが１．８以上３．０以下であることを特徴とするＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（２）ｐＨが２．０以上２．２以下であることを特徴とする前記（１）記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（３）前記飽和カルボン酸が炭素数１以上４以下の飽和カルボン酸であることを特徴とする前記（１）又は（２）記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（４）前記カルボン酸が酢酸であることを特徴とする前記（１）〜（３）のいずれか一項に記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液。
（５）前記（１）〜（４）のいずれか一項に記載のＵＬＳＩ微細配線埋め込み用電気銅めっき液を用いたことを特徴とするＵＬＳＩ微細配線用電気銅めっき方法。
（６）前記（５）記載のＵＬＳＩ微細配線用電気銅めっき方法によりＵＬＳＩ微細配線が形成されたことを特徴とするＵＬＳＩ微細配線基板。
発明の効果
［０００６］
ＵＬＳＩ微細銅配線（ダマシン銅配線）形成において、銅シード層上に本発明の電気銅めっき液用いて銅配線層を形成することにより、銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁ボイドの発生を抑制することができる。
図面の簡単な説明
［０００７］
［図１］実施例１で得られためっき物の断面ＳＥＭ写真である。
［図２］比較例１で得られためっき物の断面ＳＥＭ写真である。
発明を実施するための形態
［０００８］
本発明のＵＬＳＩ微細配線埋め込み用電気銅めっき液は、ｐＨ１．８以上３．０以下である。通常の硫酸ベースの銅めっき液では、ｐＨ１．２以下の強酸となるが、硫酸の代わりに酢酸等のカルボン酸を用いることでめっき液のｐＨを１．８以上３．０以下とすることができる。ｐＨ１．８以上３．０[0002]
[0005]
That is, the present invention is as follows.
(1) An electrolytic copper plating solution for embedding ULSI fine wiring, characterized by comprising saturated carboxylic acid in an amount of 0.01 mol / L to 2.0 mol / L and a pH of 1.8 to 3.0.
(2) The electrolytic copper plating solution for embedding ULSI fine wiring according to (1) above, wherein the pH is 2.0 or more and 2.2 or less.
(3) The electrolytic copper plating solution for embedding ULSI fine wiring according to (1) or (2), wherein the saturated carboxylic acid is a saturated carboxylic acid having 1 to 4 carbon atoms.
(4) The electrolytic copper plating solution for embedding ULSI fine wiring according to any one of (1) to (3), wherein the carboxylic acid is acetic acid.
(5) A copper electroplating method for ULSI fine wiring, comprising using the copper electroplating solution for embedding ULSI fine wiring according to any one of (1) to (4).
(6) A ULSI fine wiring board, wherein a ULSI fine wiring is formed by the electrolytic copper plating method for ULSI fine wiring described in (5) above.
Effects of the Invention [0006]
In the formation of ULSI fine copper wiring (damascene copper wiring), the copper wiring layer is formed on the copper seed layer by using the electrolytic copper plating solution of the present invention, thereby suppressing the dissolution of the copper seed layer. Generation of wall voids can be suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS [0007]
FIG. 1 is a cross-sectional SEM photograph of a plated product obtained in Example 1.
FIG. 2 is a cross-sectional SEM photograph of the plated product obtained in Comparative Example 1.
BEST MODE FOR CARRYING OUT THE INVENTION [0008]
The electrolytic copper plating solution for embedding ULSI fine wiring of the present invention has a pH of 1.8 to 3.0. In a normal sulfuric acid-based copper plating solution, a strong acid having a pH of 1.2 or less is obtained, but by using a carboxylic acid such as acetic acid instead of sulfuric acid, the pH of the plating solution may be adjusted to 1.8 to 3.0. it can. pH 1.8 to 3.0
即ち、本発明は以下の通りである。
（１）飽和カルボン酸を０．０１ｍｏｌ／Ｌ以上２．０ｍｏｌ／Ｌ以下、硫酸銅を０．０５〜１．５ｍｏｌ／Ｌ、塩素イオンを０．３〜３．０ｍｍｏｌ／Ｌ含み、ｐＨが１．８以上３．０以下であることを特徴とする、トレンチ・ビア内の銅シード層の厚さが２ｎｍ以下のＵＬＳＩ微細ダマシン配線埋め込み用電気銅めっき水溶液。
（２）ｐＨが２．０以上２．２以下であることを特徴とする前記（１）記載のＵＬＳＩ微細ダマシン配線埋め込み用電気銅めっき水溶液。
（３）炭素数が１以上４以下の飽和カルボン酸を０．０１ｍｏｌ／Ｌ以上２．０ｍｏｌ／Ｌ以下含むことを特徴とする前記（１）又は（２）記載のＵＬＳＩ微細ダマシン配線埋め込み用電気銅めっき水溶液。
（４）前記カルボン酸が酢酸であることを特徴とする前記（３）記載のＵＬＳＩ微細ダマシン配線埋め込み用電気銅めっき水溶液。
（５）前記（１）〜（４）のいずれか一項に記載のＵＬＳＩ微細ダマシン配線埋め込み用電気銅めっき水溶液を用いることを特徴とするＵＬＳＩ微細ダマシン配線用電気銅めっき方法。
（６）前記（５）記載のＵＬＳＩ微細ダマシン配線用電気銅めっき方法により、銅シード層の厚さが２ｎｍ以下のビア・トレンチ側壁部にボイドが全く無いＵＬＳＩ微細ダマシン配線が形成されたことを特徴とするＵＬＳＩ微細ダマシン配線基板。
発明の効果
That is, the present invention is as follows.
(1) 0.01 mol / L or more and 2.0 mol / L or less of saturated carboxylic acid, 0.05 to 1.5 mol / L of copper sulfate, 0.3 to 3.0 mmol / L of chloride ion, pH 1 and wherein the at .8 to 3.0, copper electroplating aqueous solution for embedding ULSI fine damascene wiring thickness is less 2nm copper seed layer in a trench vias.
(2) wherein (1) ULSI fine damascene wiring embedding copper electroplating aqueous solution, wherein the pH is 2.0 to 2.2.
(3) Electricity for embedding ULSI fine damascene wiring according to (1) or (2) above, comprising a saturated carboxylic acid having 1 to 4 carbon atoms in an amount of 0.01 mol / L to 2.0 mol / L copper plating aqueous solution.
(4) said carboxylic acid is characterized in that the acetic acid the (3) ULSI fine damascene wiring embedding copper electroplating aqueous solution according.
(5) the (1) to (4) either copper plating method for ULSI fine Damascene wiring, wherein the benzalkonium using ULSI fine damascene wiring embedding copper electroplating aqueous solution according to one of.
(6) The ULSI fine damascene wiring for ULSI fine damascene wiring described in (5) above has formed a ULSI fine damascene wiring having no voids in the sidewalls of vias and trenches with a copper seed layer thickness of 2 nm or less. A featured ULSI fine damascene wiring board.
Effect of the invention
Claims (6)
A ULSI fine wiring board, wherein the ULSI fine wiring is formed by the electrolytic copper plating method for ULSI fine wiring according to claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011520869A JP5809055B2 (en) | 2009-07-01 | 2010-06-22 | Electrolytic copper plating solution for embedding ULSI fine damascene wiring |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2009156929 | 2009-07-01 | ||
| JP2009156929 | 2009-07-01 | ||
| PCT/JP2010/060545 WO2011001847A1 (en) | 2009-07-01 | 2010-06-22 | Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi |
| JP2011520869A JP5809055B2 (en) | 2009-07-01 | 2010-06-22 | Electrolytic copper plating solution for embedding ULSI fine damascene wiring |
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| Publication Number | Publication Date |
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| JPWO2011001847A1 true JPWO2011001847A1 (en) | 2012-12-13 |
| JP5809055B2 JP5809055B2 (en) | 2015-11-10 |
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| US (2) | US20120103820A1 (en) |
| JP (1) | JP5809055B2 (en) |
| TW (1) | TWI412631B (en) |
| WO (1) | WO2011001847A1 (en) |
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| JP2012092366A (en) * | 2010-10-25 | 2012-05-17 | Imec | Method of electrodepositing copper |
| JP5903706B2 (en) * | 2011-08-25 | 2016-04-13 | 石原ケミカル株式会社 | Copper filling method and electronic component manufacturing method using the method |
| KR20140135007A (en) * | 2013-05-15 | 2014-11-25 | 삼성전기주식회사 | Copper plating solution composition for printed circuit board and via hole filling method using the same |
| JP7157749B2 (en) | 2017-08-31 | 2022-10-20 | 株式会社Adeka | Electrolytic plating solution containing additive for electrolytic plating solution and electrolytic plating method using the electrolytic plating solution |
| TWI636245B (en) * | 2017-11-21 | 2018-09-21 | 財團法人金屬工業研究發展中心 | System and method for monitoring metal collision |
| JPWO2022172823A1 (en) | 2021-02-15 | 2022-08-18 |
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| US6197181B1 (en) * | 1998-03-20 | 2001-03-06 | Semitool, Inc. | Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece |
| US6444110B2 (en) * | 1999-05-17 | 2002-09-03 | Shipley Company, L.L.C. | Electrolytic copper plating method |
| US6355153B1 (en) * | 1999-09-17 | 2002-03-12 | Nutool, Inc. | Chip interconnect and packaging deposition methods and structures |
| JP3367655B2 (en) * | 1999-12-24 | 2003-01-14 | 島田理化工業株式会社 | Plating apparatus and plating method |
| US6491806B1 (en) * | 2000-04-27 | 2002-12-10 | Intel Corporation | Electroplating bath composition |
| JP2002004081A (en) * | 2000-06-16 | 2002-01-09 | Learonal Japan Inc | Electroplating method to silicon wafer |
| DE60123189T2 (en) * | 2000-10-13 | 2007-10-11 | Shipley Co., L.L.C., Marlborough | Germ layer repair and electroplating bath |
| EP1197586A3 (en) * | 2000-10-13 | 2002-09-25 | Shipley Company LLC | Electrolyte |
| JP4603812B2 (en) * | 2003-05-12 | 2010-12-22 | ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． | Improved tin plating method |
| US20090218233A1 (en) * | 2005-11-18 | 2009-09-03 | Mikael Fredenberg | Method of Forming a Multilayer Structure |
| JP2007197809A (en) * | 2006-01-30 | 2007-08-09 | Fujifilm Corp | Plating treatment method, electrically conductive film, and translucent electromagnetic wave shielding film |
| US7799684B1 (en) * | 2007-03-05 | 2010-09-21 | Novellus Systems, Inc. | Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers |
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| US20120103820A1 (en) | 2012-05-03 |
| WO2011001847A1 (en) | 2011-01-06 |
| TWI412631B (en) | 2013-10-21 |
| JP5809055B2 (en) | 2015-11-10 |
| TW201107537A (en) | 2011-03-01 |
| US20140158546A1 (en) | 2014-06-12 |
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