JP5809055B2 - Copper electroplating solution for Ulsi embedded fine damascene interconnect - Google Patents

Copper electroplating solution for Ulsi embedded fine damascene interconnect Download PDF

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JP5809055B2
JP5809055B2 JP2011520869A JP2011520869A JP5809055B2 JP 5809055 B2 JP5809055 B2 JP 5809055B2 JP 2011520869 A JP2011520869 A JP 2011520869A JP 2011520869 A JP2011520869 A JP 2011520869A JP 5809055 B2 JP5809055 B2 JP 5809055B2
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copper
ulsi
ulsi fine
wiring
copper electroplating
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JPWO2011001847A1 (en
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関口 淳之輔
淳之輔 関口
祐史 高橋
祐史 高橋
相場 玲宏
玲宏 相場
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Jx日鉱日石金属株式会社
Jx日鉱日石金属株式会社
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/06Wires; Strips; Foils
    • C25D7/0607Wires
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

本発明は、ULSI微細銅配線埋め込み用電気銅めっき液に関する。 The present invention relates to a copper electroplating solution for embedding ULSI fine copper wiring.

ULSI微細配線埋め込み用電気銅めっきは、通常硫酸ベースの強酸性めっき液(pH1.2以下)を用いて行われている。 Copper electroplating for embedding ULSI fine wiring is usually performed using a sulfuric acid-based acidic plating solution (pH 1.2 or less). その際のシード層としてスパッタ銅膜が使用されているが、配線の微細化によりトレンチ・ビア内のスパッタ銅膜が極薄化してきている。 Although sputtering copper film is used as a seed layer during the sputter copper film in the trench vias are becoming extremely thinned by the miniaturization of wiring. シード層最表面は電気めっき前の状態では大気中に曝されているため酸化が避けられないが、電気めっき液が強酸性であるため酸性めっき液浸漬時に、シード層の酸化された部分が容易に溶解し、薄いシード層に欠陥が発生し、その後電気銅めっきにより銅配線層を形成した際に所々銅めっきの抜けが生じる問題がある。 Although inevitable oxidation because it is exposed to the atmosphere in the seed layer outermost surface before electroplating state, when an acidic plating solution immersion for electroplating solution is strongly acidic, easily oxidized portion of the seed layer dissolved in, a thin seed layer defects occur, there is a problem that omission may occur in some places copper plating when forming the copper wiring layer by the subsequent electrolytic copper plating. 特にトレンチ・ビア内側壁にボイドが発生し易く問題となっている。 In particular, it has become a easy problem void is generated in the side wall in the trench vias.

本発明はますます微細化が進むULSI微細銅配線(ダマシン銅配線)形成において、銅シード層上に電気銅めっきを実施する際の銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁のボイドの発生を抑制することのできる電気銅めっき液を提供することを目的とする。 The present invention is in increasingly miniaturization ULSI fine copper wiring (damascene copper wiring) formed, to suppress the dissolution of the copper seed layer in the practice of copper electroplating on the copper seed layer, resulting sidewall within via hole or trench and to provide a copper electroplating solution capable of suppressing generation of voids.

本発明者らは、通常の硫酸ベースの強酸性の銅めっき液に用いる硫酸の代わりにカルボン酸等を用いることでめっき液のpHを通常の強酸性から弱酸性気味にすることにより、めっき液浸漬時の銅シード層の溶解し易さを抑制することを試みた。 The present inventors have found that by the weakly acidic slightly the pH of the plating solution by using a carboxylic acid in place of sulfuric acid used in the conventional strongly acidic copper plating solution of sulfuric acid based usually strongly acidic plating solution We attempted to suppress the dissolution ease of copper seed layer during immersion. その結果、硫酸ベースの強酸性めっき液使用時に発生していたトレンチ側壁のボイドが、カルボン酸ベースのめっき液を使用することにより無くなり、上記課題が解決されることを見出し本発明に至った。 As a result, voids of the trench sidewall that occurs during a strongly acidic plating liquid used in the sulfuric acid base, eliminated by using a carboxylic acid-based plating solution, leading to found the present invention that the above problems can be solved.

即ち、本発明は以下の通りである。 That is, the present invention is as follows.
(1)飽和カルボン酸を0.01mol/L以上2.0mol/L以下、硫酸銅を0.05〜1.5mol/L、塩素イオンを0.3〜3.0mmol/L含み、pHが1.8以上3.0以下であり、抑制剤としてはポリエチレングリコール、ポリプロピレングリコール、及びこれらの共重合体を使用することを特徴とする、トレンチ・ビア内の銅シード層の厚さが2nm以下のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 (1) a saturated carboxylic acid 0.01 mol / L or more 2.0 mol / L or less, including 0.3~3.0mmol / L 0.05~1.5mol / L, chloride ions of copper sulfate, pH is 1 and at .8 to 3.0, the polyethylene glycol as an inhibitor, polypropylene glycol, and wherein the use of these copolymers, the thickness of the copper seed layer in a trench via the following 2nm copper electroplating solution for embedding ULSI fine damascene wiring.
(2)pHが2.0以上2.2以下であることを特徴とする前記(1)記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 (2) wherein (1) ULSI fine Damascene wiring copper electroplating solution for embedding, wherein the pH is 2.0 to 2.2.
(3)炭素数が1以上4以下の飽和カルボン酸を0.01mol/L以上2.0mol/L以下含むことを特徴とする前記(1)又は(2)記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 (3) (1) or (2) ULSI fine damascene wiring embedding electric according to carbon atoms, characterized in that it contains a saturated carboxylic acid having from 1 to 4 0.01 mol / L or more 2.0 mol / L or less copper plating solution.
(4)前記カルボン酸が酢酸であることを特徴とする前記(3)記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 (4) the said (3) ULSI fine Damascene wiring copper electroplating solution for embedding, wherein the carboxylic acid is acetic acid.
(5)前記(1)〜(4)のいずれか一項に記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液を用いることを特徴とするULSI微細ダマシン配線用電気銅めっき方法。 (5) the (1) to (4) either copper plating method for ULSI fine Damascene wiring, which comprises using a ULSI fine damascene wiring embedding copper plating solution according to one of.
(6)前記(5)記載のULSI微細ダマシン配線用電気銅めっき方法により、銅シード層の厚さが2nm以下のビア・トレンチ側壁部にボイドが全く無いULSI微細ダマシン配線形成することを特徴とするULSI微細ダマシン配線基板の製造方法 (6) wherein (5) the copper electroplating method for ULSI fine damascene wiring according, characterized in that the voids formed a completely free ULSI fine damascene wiring via hole or trench side wall thickness is less 2nm copper seed layer method for manufacturing ULSI fine damascene wiring board to.

ULSI微細銅配線(ダマシン銅配線)形成において、銅シード層上に本発明の電気銅めっき液用いて銅配線層を形成することにより、銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁ボイドの発生を抑制することができる。 In ULSI fine copper wiring (damascene copper wiring) formed on the copper seed layer by electrolytic copper plating solution of the present invention by forming a copper wiring layer, to suppress the dissolution of the copper seed layer, resulting via hole or trench inner it is possible to suppress the occurrence of the wall voids.

実施例1で得られためっき物の断面SEM写真である。 It is a cross-sectional SEM photograph of the obtained plated in Example 1. 比較例1で得られためっき物の断面SEM写真である。 It is a cross-sectional SEM photograph of the obtained plated in Comparative Example 1.

本発明のULSI微細配線埋め込み用電気銅めっき液は、pH1.8以上3.0以下である。 ULSI fine wiring embedding copper plating solution of the present invention is pH1.8 to 3.0. 通常の硫酸ベースの銅めっき液では、pH1.2以下の強酸となるが、硫酸の代わりに酢酸等のカルボン酸を用いることでめっき液のpHを1.8以上3.0以下とすることができる。 In a typical sulfate-based copper plating solution, but becomes pH1.2 following strong acid, it can be the pH of the plating solution with 1.8 to 3.0 by using a carboxylic acid such as acetic acid in place of sulfuric acid it can. pH1.8以上3.0以下とすることにより、銅シード層の溶解を抑制し、その結果ビア・トレンチ内側壁ボイドの発生を抑制することが可能となった。 With pH1.8 to 3.0, to suppress the dissolution of the copper seed layer, it becomes possible to result suppress the occurrence of the via trench sidewall voids. pHは2.0以上2.2以下がより好ましい。 pH is more preferably 2.0 to 2.2.
pHが1.8未満であると、pHが低いため銅シード層が溶解し易くなり、その結果ボイドも発生し易くなる。 When the pH is less than 1.8, the pH is liable to dissolve copper seed layer due to the low, even more likely to occur as a result voids. また、pHが3.0よりも大きい場合、めっき液中の銅イオンが酸化物あるいは水酸化物となって、沈殿が発生する恐れがある。 Further, if the pH is greater than 3.0, the copper ions in the plating solution becomes an oxide or hydroxide, there is a risk that precipitation will occur.

前記カルボン酸としては、めっき液に溶解しpHを上記範囲内とすることができるものであればどのようなカルボン酸でも良く、好ましくはギ酸、酢酸、プロピオン酸、酪酸、シュウ酸等の炭素数1以上4以下の飽和カルボン酸であり、特に酢酸が好ましい。 As the carboxylic acid, the pH and dissolved in the plating solution may be any acid so long as it can be within the above range, preferably the number of carbon atoms, such as formic acid, acetic acid, propionic acid, butyric acid, oxalic acid 1 to 4 are less saturated carboxylic acids, particularly acetic acid is preferred.
カルボン酸はめっき液中、0.01〜2.0mol/L含有されることが好ましく、より好ましくは0.2〜1.0mol/Lである。 In the plating solution the carboxylic acid is preferably contained 0.01~2.0mol / L, more preferably 0.2~1.0mol / L. めっき液中のカルボン酸の濃度は埋め込み性、及びpHに影響し、カルボン酸の濃度が2.0mol/Lを超えるとめっき液のpHが1.8未満まで下がり、ボイドが発生し易くなる。 The concentration of the carboxylic acid in the plating solution embeddability, and affect the pH, down to a pH less than 1.8 of the plating solution and the concentration of carboxylic acid is more than 2.0 mol / L, easily voids are generated. また、カルボン酸のめっき液中の濃度が0.01mol/L未満であると、めっき液のpHが3.0を超え、上述のように沈殿が発生する恐れがある。 The concentration of the plating solution of the carboxylic acid is less than 0.01 mol / L, pH of the plating solution is more than 3.0, there is a risk that precipitation will occur as described above.

本発明の電気銅めっき液は水溶液であり、その他の成分としては、銅塩、塩素イオン、微量添加剤等が挙げられ、それぞれ公知のものでよく特に制限はない。 Copper electroplating solution of the present invention is an aqueous solution, as other components, copper, chloride ions, trace additives and the like, not particularly limited, respectively may be of known.
銅塩としては、硫酸銅、硝酸銅、塩化銅などが挙げられ、硫酸銅が好ましい。 The copper salt, copper sulfate, copper nitrate, copper chloride and the like, copper sulfate is preferred. 銅塩はめっき液中0.05〜1.5mol/L含有されることが好ましく、より好ましくは0.2〜0.8mol/Lである。 Copper salt is preferably contained 0.05~1.5mol / L in the plating solution, more preferably 0.2~0.8mol / L.
塩素イオン濃度はめっき液中0.3〜3.0mmol/L含有されることが好ましく、より好ましくは1.0〜2.0mmol/Lである。 Chloride ion concentration is preferably contained in the plating solution 0.3~3.0mmol / L, more preferably 1.0~2.0mmol / L.

微量添加剤としては、促進剤、抑制剤、平滑剤等が挙げられる。 Examples of the trace additive, accelerators, inhibitors, leveling agents, and the like.
促進剤としては二硫化ビス(3−スルホプロピル)二ナトリウム、3−メルカプトプロパンスルホン酸等が挙げられ、めっき液中1〜30mg/L含有されることが好ましい。 Disulfide bis (3-sulfopropyl) disodium as promoters, 3-mercapto propanesulfonic acid, and the like, the content thereof is preferably 1 to 30 mg / L in the plating solution.
抑制剤としては、ポリエチレングリコール、ポリプロピレングリコール、及びこれらの共重合体等が挙げられ、めっき液中10〜500mg/L含有されることが好ましい。 The inhibitor, polyethylene glycol, polypropylene glycol, and copolymers thereof, with the content thereof is preferably 10 to 500 mg / L in the plating solution.
平滑剤としては、ヤヌスグリーンB、ポリエチレンイミン、ポリビニルピロリドン等が挙げられ、めっき液中0.1〜50mg/L含有されることが好ましい。 The smoothing agent, Janus Green B, polyethyleneimine, polyvinyl pyrrolidone, and the like, to be contained in 0.1 to 50 mg / L the plating solution preferably.

また、本発明の電気銅めっき液を用いためっきは、浴温20〜30℃で行うのが、浴安定性および銅の析出速度の点から好ましく、また、カソード電流密度は0.1〜5A/dm で行うことが好ましい。 The plating using electrolytic copper plating solution of the present invention is carried out at a bath temperature 20 to 30 ° C., preferably in terms of bath stability and copper deposition rate, also the cathode current density 0.1~5A it is preferably carried out in / dm 2.

電気銅めっきを行う被めっき材としては、半導体ウェハーなど微細配線基板となるものであり、トレンチ・ビア等のULSI微細配線付きのシリコン基板の表面に銅シード層を設けたものが好ましい。 The material to be plated for performing electrolytic copper plating, which a fine wiring substrate such as a semiconductor wafer, it is preferable that the copper seed layer provided on the surface of a silicon substrate with a ULSI fine wiring such as trench vias.
銅シード層は、スパッタ法、無電解めっき法等の公知の方法で形成されたものでよい。 Copper seed layer, the sputtering method, may be those formed by a known method such as electroless plating.
本発明の電気銅めっき液を用いてめっきを行うことにより、トレンチ・ビア内の銅シード層の厚さが2nm、又はそれ以下であっても、ボイドが発生することなくめっきすることができる。 By performing plating by using a copper electroplating solution of the present invention, 2 nm thick copper seed layer in a trench vias, or even less than a, it can be plated without voids are generated.

実施例1 Example 1
以下に示すめっき液を用いて、ULSI微細配線付きシリコン基板上に電気銅めっきを行った。 Using a plating solution shown below was carried out copper electroplating in ULSI fine wiring with silicon substrate. 被めっき材であるシリコン基板には微細なトレンチパターン(線幅180nm、深さ500nm)が付いていて、最表面にはスパッタ法によりCuシード層が形成されている。 The material to be plated on the silicon substrate is a fine trench pattern (line width 180 nm, depth 500 nm) to have a, Cu seed layer is formed by sputtering on the outermost surface. そのCuシード層膜厚は、トレンチ内最薄部で2nmであった。 Its Cu seed layer thickness was 2nm thinnest portion in the trench.
めっき液組成: Plating solution composition:
銅(硫酸銅) 0.63mol/L Copper (copper sulfate) 0.63mol / L
酢酸 0.5mol/L Acetic acid 0.5mol / L
HCl 1.4mmol/L HCl 1.4mmol / L
二硫化ビス(3−スルホプロピル)二ナトリウム 10mg/L Disulfide bis (3-sulfopropyl) disodium 10 mg / L
ポリプロピレングリコール 80mg/L Polypropylene glycol 80mg / L
ポリビニルピロリドン 10mg/L Polyvinylpyrrolidone 10 mg / L
pH 2.1 pH 2.1
25℃、1A/dm で30秒間めっきを実施した。 25 ° C., was carried out for 30 seconds plating 1A / dm 2.
断面SEM観察の結果を図1に示す。 The results of cross-sectional SEM observation shown in FIG. トレンチ側壁部も含めてボイドの発生は全く無かった。 Generation of voids, including the trench side wall portion was absolutely not.

実施例2 Example 2
以下に示すめっき液を用いて、ULSI微細配線付きシリコン基板上に電気銅めっきを行った。 Using a plating solution shown below was carried out copper electroplating in ULSI fine wiring with silicon substrate. 被めっき材であるシリコン基板は実施例1と同様で、Cuシード層膜厚は、トレンチ内最薄部で2nmであった。 Silicon substrate as an object to be plated is the same as in Example 1, Cu seed layer thickness was 2nm thinnest portion in the trench.
めっき液組成: Plating solution composition:
銅(硫酸銅) 0.63mol/L Copper (copper sulfate) 0.63mol / L
ギ酸 1.0mol/L Formic acid 1.0mol / L
HCl 1.4mmol/L HCl 1.4mmol / L
二硫化ビス(3−スルホプロピル)二ナトリウム 10mg/L Disulfide bis (3-sulfopropyl) disodium 10 mg / L
ポリプロピレングリコール 80mg/L Polypropylene glycol 80mg / L
ポリビニルピロリドン 10mg/L Polyvinylpyrrolidone 10 mg / L
pH 1.9 pH 1.9
25℃、1A/dm で30秒間めっきを実施した。 25 ° C., was carried out for 30 seconds plating 1A / dm 2.
断面SEM観察の結果、トレンチ側壁部も含めてボイドの発生は全く無かった。 Cross-sectional SEM observation of the occurrence of voids, including the trench side wall was completely no.

実施例3 Example 3
以下に示すめっき液を用いて、ULSI微細配線付きシリコン基板上に電気銅めっきを行った。 Using a plating solution shown below was carried out copper electroplating in ULSI fine wiring with silicon substrate. 被めっき材であるシリコン基板は、Cuシード層膜厚が、トレンチ内最薄部で1.8nmである以外は実施例1と同様であった。 Silicon substrate is a material to be plated is, Cu seed layer thickness, than a 1.8nm thinnest portion within the trench were the same as in Example 1.
めっき液組成: Plating solution composition:
銅(硫酸銅) 0.63mol/L Copper (copper sulfate) 0.63mol / L
シュウ酸 0.1mol/L Oxalic acid 0.1mol / L
HCl 1.4mmol/L HCl 1.4mmol / L
二硫化ビス(3−スルホプロピル)二ナトリウム 10mg/L Disulfide bis (3-sulfopropyl) disodium 10 mg / L
ポリプロピレングリコール 80mg/L Polypropylene glycol 80mg / L
ポリビニルピロリドン 10mg/L Polyvinylpyrrolidone 10 mg / L
pH 2.5 pH 2.5
25℃、1A/dm で30秒間めっきを実施した。 25 ° C., was carried out for 30 seconds plating 1A / dm 2.
断面SEM観察の結果、トレンチ側壁部も含めてボイドの発生は全く無かった。 Cross-sectional SEM observation of the occurrence of voids, including the trench side wall was completely no.

比較例1 Comparative Example 1
めっき液組成を以下のように変更した以外は実施例1と同様に電気銅めっきを実施した。 Except for changing the plating solution composition as follows was carried out copper electroplating in the same manner as in Example 1.
めっき液組成: Plating solution composition:
銅(硫酸銅) 0.63mol/L Copper (copper sulfate) 0.63mol / L
硫酸 0.5mol/L Sulfuric acid 0.5mol / L
HCl 1.4mmol/L HCl 1.4mmol / L
二硫化ビス(3−スルホプロピル)二ナトリウム 10mg/L Disulfide bis (3-sulfopropyl) disodium 10 mg / L
ポリプロピレングリコール 80mg/L Polypropylene glycol 80mg / L
ポリビニルピロリドン 10mg/L Polyvinylpyrrolidone 10 mg / L
<pH1.0 <PH1.0
断面SEM観察の結果を図2に示す。 The results of cross-sectional SEM observation shown in FIG. 少なくとも一部のトレンチ側壁部にボイド(円内の黒い影部)の発生が観察された。 Voids (dark shadow within circles) was observed on at least a portion of the trench sidewall portion.

Claims (6)

  1. 飽和カルボン酸を0.01mol/L以上2.0mol/L以下、硫酸銅を0.05〜1.5mol/L、塩素イオンを0.3〜3.0mmol/L含み、pHが1.8以上3.0以下であり、抑制剤としてはポリエチレングリコール、ポリプロピレングリコール、及びこれらの共重合体を使用することを特徴とする、トレンチ・ビア内の銅シード層の厚さが2nm以下のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 Saturated carboxylic acid 0.01 mol / L or more 2.0 mol / L or less, 0.05~1.5Mol copper sulfate / L, chloride ions include 0.3~3.0mmol / L, pH 1.8 or 3.0 or less, the polyethylene glycol as an inhibitor, polypropylene glycol, and wherein the use of these copolymers, ULSI fine damascene thickness of the copper seed layer is less 2nm in the trench vias wiring copper electroplating solution for embedded.
  2. pHが2.0以上2.2以下であることを特徴とする請求項1記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 ULSI fine Damascene wiring copper electroplating solution for embedding according to claim 1, wherein the pH is 2.0 to 2.2.
  3. 炭素数が1以上4以下の飽和カルボン酸を0.01mol/L以上2.0mol/L以下含むことを特徴とする請求項1又は2記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 ULSI fine Damascene wiring copper electroplating solution for embedding claim 1 or 2, wherein the carbon atoms including saturated carboxylic acids of 1 to 4 0.01 mol / L or more 2.0 mol / L or less.
  4. 前記カルボン酸が酢酸であることを特徴とする請求項3記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液。 ULSI fine Damascene wiring copper electroplating solution for embedding claim 3 wherein said carboxylic acid is acetic acid.
  5. 請求項1〜4のいずれか一項に記載のULSI微細ダマシン配線埋め込み用電気銅めっき水溶液を用いることを特徴とするULSI微細ダマシン配線用電気銅めっき方法。 Copper electroplating method for ULSI fine Damascene wiring, which comprises using a ULSI fine damascene wiring embedding copper plating solution according to any one of claims 1-4.
  6. 請求項5記載のULSI微細ダマシン配線用電気銅めっき方法により、銅シード層の厚さが2nm以下のビア・トレンチ側壁部にボイドが全く無いULSI微細ダマシン配線形成することを特徴とするULSI微細ダマシン配線基板の製造方法 The claim 5 electrolytic copper plating method for ULSI fine damascene wiring according, ULSI fine that the thickness of the copper seed layer and forming a ULSI fine damascene wiring void without any below the via trench sidewall portion 2nm method of manufacturing a damascene wiring board.
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