JPWO2009090893A1 - Capacitor element, semiconductor device including the same, and method of manufacturing capacitor element - Google Patents

Abstract

In a capacitive element having a structure in which a lower electrode material is in direct contact with a Cu wiring, a structure for improving reliability is provided. The capacitive element (30) is provided on the first lower electrode (32) made of the Cu wiring layer and the first lower electrode (32), and has a size including the first lower electrode (32). A capacitive element interlayer film (40) having an opening (44), and a second lower electrode on the first lower electrode (32) and the capacitive element interlayer film (40) so as to enclose the opening (44). (61), a capacitive insulating film (62), and a laminated body (65) provided in this order on the upper electrode (63).

Description

  The present invention relates to a capacitive element, a semiconductor device including the capacitive element, and a method for manufacturing the capacitive element.

  In ultra-large scale integrated circuits (ULSI) formed on Si semiconductor substrates, design dimensions are constantly being miniaturized in order to pursue cost reduction, performance improvement, and power consumption reduction. . The function is improved by increasing the number of integrated elements by miniaturization, and the cost is reduced by reducing the chip size. Alternatively, it is possible to mount a plurality of circuit blocks having different functions due to the improvement in the degree of integration, and it is possible to reduce the cost of a device incorporating a ULSI chip by reducing the number of parts. Such mixed mounting of circuit blocks having different functions can realize not only cost reduction but also additional performance improvement by combining them such as improvement of communication speed. Further, since the operating voltage can be reduced by miniaturization, power consumption of circuit blocks having the same function can be suppressed.

  However, new problems have become apparent due to the rapid miniaturization of active devices. Below, this problem is classified and classified into power supply noise, RF (Radio Frequency) / analog, and power consumption.

  First, the problem about power supply noise is described. As the miniaturization progresses, the voltage reduction is promoted, but the number of elements to be integrated increases rapidly, so that the amount of current consumed increases rapidly. In addition, the operating frequency continues to increase with the miniaturization of elements, and the switching time is shortened. That is, since the amount of current at the time of switching increases and the switching time is shortened, di / dt that is the time change of the current increases rapidly. L · di / dt obtained by multiplying the time variation of the current by the inductance L of the circuit is an inductive voltage fluctuation and is called simultaneous switching noise. Simultaneous switching noise fluctuates the power supply potential, and in some cases, the logic state may be reversed. As described above, as the miniaturization progresses, the power supply voltage decreases, and the fluctuation voltage due to noise increases, so the noise margin decreases at an accelerated rate.

  Such inductive noise can be reduced by reducing the impedance of the circuit. For example, power supply fluctuations can be suppressed by adding capacitance to the circuit. Such a capacity is called a decoupling capacity. In the conventional ULSI, a MOS (Metal Oxide Silicon) capacitor obtained when forming a transistor is used as a decoupling capacitor. However, with the progress of miniaturization, the insulating film thickness of the MOS capacitor is reduced, which causes a problem that the leakage current of the insulating film increases rapidly. In addition, since the noise margin is drastically reduced, the absolute capacitance value is also insufficient, and the chip area tends to increase due to the decoupling capacitance inserted to stabilize the power supply potential.

  In order to avoid the above problems, it is necessary to prepare a decoupling capacitor using an insulating film having a dielectric constant higher than that of the MOS capacitor in the wiring layer. By incorporating a capacitor in the wiring layer, the capacitor can be placed over the transistor on a plane, so that the installation area can be larger than the MOS capacitor. Since the capacitance value in the same area can be increased by increasing the dielectric constant, a large capacitance can be installed in a limited area.

  As countermeasures against noise during high-speed operation, it is necessary to consider not only a capacity problem but also a response problem. Power supply noise in high-speed operation contains a lot of high-frequency components. The capacitive element has a parasitic resistance component of the electrode, and the parasitic resistance component deteriorates the response to noise. When the operating speed reaches the gigahertz region, the influence of the parasitic resistance of the electrode becomes obvious, and it becomes difficult to sufficiently exhibit the performance of the decoupling capacitance. Therefore, it is necessary to reduce the electrode resistance as much as possible.

  Improvement of the operation speed by miniaturization of the MOS active element promotes the use of a high frequency (RF) signal processing circuit as a MOS device. If the RF device can be constructed with a MOS device, improvement in function and cost reduction can be realized by mixing with a digital baseband circuit. The same merit can be enjoyed by mixing analog circuits and digital circuits. In RF devices and analog devices, passive elements such as resistance elements, capacitance elements, and inductors are effectively used. For this reason, it is extremely important to integrate passive elements in addition to the active elements used in the MOS logic. The miniaturization of MOS logic is progressed with generations, but such passive elements are not miniaturized even when generations progress because characteristics are determined only by physical properties. For this reason, the relative area of the passive elements in the ULSI chip is increased, which is an impediment to a reduction in chip cost.

  Next, the problem seen from the aspect of power consumption is described. Advances in miniaturization technology not only increase the current handled by each device in the chip by increasing the driving power of the transistors, but also increase the current consumption consumed by the entire chip by improving the degree of integration. Will do. The power consumption is converted into heat by a resistance component in the circuit, causing a rise in chip temperature. In order to avoid this, a temperature sensor is mounted in a chip, and a mechanism for controlling power consumption to be reduced when a temperature rise occurs is mounted. In order to reduce the chip cost, it is necessary to reduce the size of the temperature sensor itself.

  In the case of a capacitive element, the formation of parasitic capacitance between the electrode and the silicon substrate is also a problem in terms of operating characteristics. Since the miniaturization of ULSI is three-dimensionally reduced due to the structure, the distance between the wiring layer and the silicon substrate becomes closer. At the same time, the parasitic capacitance formed between the electrode and the substrate is increased by increasing the electrode area of the capacitive element relative to the peripheral circuit. In order to solve the above problems, it is desirable to install a capacitive element having a high dielectric constant away from the substrate. That is, it is necessary to provide a capacitive element in the upper wiring layer. Further, the parasitic resistance of the electrode plate cannot be ignored due to the increase in the size relative to the active element. In high frequency operation, if the parasitic resistance of the electrode increases, the response of the capacitive element deteriorates and the desired operation is not exhibited. Therefore, the parasitic resistance in the capacitive element needs to be reduced as much as possible.

  As described above, many problems are solved by adding a capacitive element in the wiring layer. However, there is a new problem to add such a capacitive element in the wiring. In a state-of-the-art wiring structure in which a wiring material mainly composed of copper is formed in a low dielectric constant interlayer insulating film, there is a problem of heat resistance of the insulating film, so there is an upper limit of process temperature of 350 to 400 ° C. . For this reason, the temperature at which the capacitive element is formed must be set so that the upper limit is about 350 ° C. Further, since copper easily diffuses in the insulating film, it is necessary to insert a barrier film that suppresses copper diffusion between the interlayer insulating film or the capacitor insulating film and the copper wiring. From the above viewpoint, it is necessary to carefully consider the manufacturing process and structure of the passive element formed in the copper wiring.

  Examples disclosed for structures and manufacturing methods considered for the purpose of forming capacitive elements in the wiring layer are shown below.

(First related technology)
Patent Document 1 discloses a structure in which an insulating film other than silicon nitride or silicon carbide can be used as a capacitor dielectric film. This related technology relates to a capacitor structure formed on a multilayer wiring structure having copper wiring. Silicon nitride or silicon carbide is always formed as an anti-oxidation insulating film on the copper wiring. For this reason, in order to form a capacitor on the copper wiring, it is necessary to use these films as a capacitor insulating film. This related technique is a technique for avoiding this restriction. This related technology is characterized in that a metal film is used as an antioxidant film instead of an insulating film. A barrier metal is inserted between the exposed surface of the copper wiring and the metal film. The metal film is formed so as to remain on the copper wiring, and a capacitive insulating film is formed on the metal film. At this time, the portion other than the metal film exposed as the lower electrode on the copper wiring is only exposed to the interlayer insulating film, and the lower electrode has higher oxidation resistance than the copper wiring, so that it is highly oxidizable. A metal oxide dielectric film or the like can be used as a capacitive insulating film.

(Second related technology)
Patent Document 2 discloses a structure that uses Cu wiring as a lower electrode. However, since Cu has a large diffusion coefficient in the insulating film, a means for preventing the diffusion of Cu by an appropriate barrier material is necessary. In this related technology, the Cu wiring structure is connected to the lower surface of the lower electrode made of a material that prevents Cu diffusion, so that electric charges are supplied to the lower electrode through the Cu wiring, and oxidation of the interlayer insulating film or the like is performed. A structure capable of preventing Cu diffusion into the film is provided.

JP 2004-014761 A JP 2003-264235 A

  However, the first and second related technologies have the following problems.

  In the first related technology, the lower electrode and the barrier metal are inserted between the upper and lower wirings in the portion where no capacitance is formed. The lower electrode material and barrier metal having strong oxidation resistance generally have high electric resistance, and increase resistance between the upper and lower wirings. In addition, after processing the lower electrode and the barrier metal, the capacitor insulating film and the upper electrode are formed. However, in the portion where the pitch of the lower electrode is narrow, the insulating film or the like is not uniformly formed between the electrodes, and the characteristics are improved. Defects occur. In order to improve the coverage to the lower electrode, film formation using the CVD (Chemical Vapor Deposition) method is desired. However, in order to thermally decompose the raw material, it is necessary to heat at least 400 ° C. or more in the CVD method. is there. Such high temperature processes are not applicable to copper / low dielectric constant interconnects.

  In the second related technology, the laminated film constituting the capacitive element is patterned inside the opening provided in the insulating film on the lower layer wiring. In other words, there is a space between the laminated film and the end of the opening (see FIG. 10), and it is necessary to remove this part of the laminated film when the capacitive element is processed by etching. However, it is difficult to etch the laminated film attached to the side wall portion of the opening. Further, when the space between the end portion of the laminated film and the side wall of the opening is narrow, it is difficult to bury an interlayer insulating film formed thereon. If an attempt is made to secure the space in this portion, the area of the capacitive element must be reduced, resulting in an area loss.

  Here, in the capacitive element having the feature that the parasitic resistance can be reduced by the lower electrode material being in direct contact with the Cu wiring, a structure in which a space exists between the laminated film and the opening end in the second related technology. When used, the space portion becomes a copper wiring, and thus copper diffuses into the laminated film, thereby reducing the reliability of the capacitive element.

  Therefore, an object of the present invention is to provide a structure that improves the reliability of a capacitor element having a structure in which the lower electrode material is in direct contact with the Cu wiring.

  A capacitive element according to the present invention includes an interlayer insulating film having a first lower electrode made of a Cu wiring layer and an opening having a size provided on the first lower electrode and enclosing the first lower electrode. And a laminate provided in order of the second lower electrode, the capacitive insulating film and the upper electrode on the first lower electrode and the interlayer insulating film so as to contain the opening. Features.

  According to the present invention, the opening of the interlayer insulating film in which the capacitor element stack is provided is sized so as to include the first lower electrode, so that the Cu component of the first lower electrode is opened when the opening is formed. Since the second lower electrode is in direct contact with the first lower electrode made of the Cu wiring layer, the reliability can be greatly improved in the structure in which the parasitic resistance can be reduced.

  FIG. 1 is a cross-sectional view showing a capacitive element and a semiconductor device according to the first embodiment of the present invention. Hereinafter, description will be given based on this drawing.

  The semiconductor device 10 according to this embodiment includes a CMOS transistor layer 11 and a Cu multilayer wiring layer 12 composed of two or more layers formed above the CMOS transistor layer 11. Here, an arbitrary Cu wiring layer is defined as a first Cu wiring layer 23. The first Cu wiring layer 23 is connected to the second Cu wiring layer 31 existing on one layer via the first via plug 24 thereon. Similarly, the first Cu wiring layer 23 is connected to the first lower electrode 32 made of Cu of the capacitive element 30 via the via plug 25. On the surface of the second Cu wiring layer 31, there are a wiring cap insulating film 41 for preventing Cu wiring oxidation and Cu element diffusion, and a hard mask insulating film 42 for opening the wiring cap insulating film 41. A capacitive element interlayer insulating film 40 composed of layers is formed. The capacitor element interlayer insulating film corresponds to an “interlayer insulating film” in claims, and is hereinafter abbreviated as “capacitor element interlayer film”. In the portion where the capacitive element 30 is formed, the capacitive element interlayer 40 is opened, and at least a part of the second lower electrode 61 is in direct contact with the first lower electrode 32. The first lower electrode 32 is completely contained in the opening 44 and does not straddle the side wall (circumferential end) of the opening 44. The capacitive element 30 is formed with a laminated body 65 composed of the second lower electrode 61, the capacitive insulating film 62, the upper electrode 63, and the etching stopper layer 51 in a shape extending to the opening 44 and the outside thereof. Each wiring layer is insulated by an insulating film (reference numeral omitted).

  The capacitive element 30 of the present embodiment includes a first lower electrode 32 made of a Cu wiring layer, and an opening 44 that is provided on the first lower electrode 32 and has a size that encloses the first lower electrode 32. A second lower electrode 61, a capacitive insulating film 62, and an upper electrode 63 are provided in this order on the first lower electrode 32 and the capacitive element interlayer film 40 so as to enclose the capacitive element interlayer film 40 and the opening 44. A laminated body 65 is provided. The second lower electrode 61 and the upper electrode 63 have the same planar shape. The opening 44 has a tapered shape with the upper side greatly opening. The stacked body 65 also has an etching stop layer 51 provided on the upper electrode 63.

  The semiconductor device 10 of this embodiment includes a first Cu wiring layer 23, a second Cu wiring layer 31 connected to the first Cu wiring layer 23 via a first via plug 24, and a capacitive element. 30. The first lower electrode 32 is a Cu wiring layer formed in the same layer as the second Cu wiring layer 31, and is connected to the first Cu wiring layer 23 via the via plug 25. Further, the semiconductor device 10 includes a third Cu wiring layer 75 connected to the second Cu wiring layer 31 via a second via plug 71 at the upper side. The upper electrode 63 is connected to the third Cu wiring layer 76 through a contact plug 72 formed in the same layer as the second via plug 71.

The capacitor element interlayer film 40 is composed of a wiring cap insulating film 41 having a property of preventing oxidation of the Cu wiring layer and diffusion of Cu element, and a material different from the wiring cap insulating film 41 provided on the wiring cap insulating film 41. It has two layers with the hard mask insulating film 42. For example, the wiring cap insulating film 41 is made of SiCN or SiC, and the hard mask insulating film 42 is made of SiO ₂ or SiCOH. The capacitor insulating film 62 is made of, for example, SiN having a thickness of 5 nm or more, or made of tantalum oxide formed by a plasma oxidation method.

  In other words, the capacitive element 30 covers the surface of the first lower electrode 32 formed at the same time as the optional second Cu wiring layer 31 and the second Cu wiring layer 31 and the first lower electrode 32. A capacitive element interlayer film 40 having an enclosing opening 44, a second lower electrode 61, a capacitive insulating film 62, and an upper part formed so as to enclose the opening 44 and extend on the capacitive element interlayer film 40. A stacked body 65 including an electrode 63 and an etching stopper layer 51 is provided. For connection with an external circuit, the first lower electrode 32 is connected to the lower first wiring layer 23 via the via plug 25, and the upper electrode 63 is connected to the upper third electrode via the contact plug 72. Are connected to the wiring layer 76.

  Next, the operation of the capacitive element 30 and the semiconductor device 10 of this embodiment will be described. A capacitor element interlayer film 40 is formed on the second Cu wiring layer 31 and the first lower electrode 32, and an opening 44 is provided in the capacitor element interlayer film 40 so as to enclose the first lower electrode 32 in a plane. Further, the capacitive element 30 is formed so as to include the opening 44 in a plane. Thus, the first lower electrode 32 made of the Cu wiring layer is completely covered with either the second lower electrode 61 or the capacitor element interlayer film 40 that prevents diffusion of Cu. Further, since the second lower electrode 61 is in direct contact with the first lower electrode 32 made of the Cu wiring layer, it is possible to reduce the parasitic resistance. Substantially, since the Cu wiring layer is used as the first lower electrode 32, it is possible to reduce the thickness of the entire capacitive element 30, and to ensure scaling in a semiconductor process in which miniaturization proceeds. Although having the above-described characteristics, since the side wall of the opening 44 is not located on the first lower electrode 32 made of the Cu wiring layer, the reliability of the capacitor 30 is improved as will be described later. In the lithography process for opening the capacitor element interlayer film 44, alignment using a mark formed by a lower Cu wiring through the optically transparent capacitor element interlayer film 44 is possible. Therefore, by simultaneously forming the mark for alignment when patterning the capacitive element 30 in this opening process, the capacitive element 30 can be mounted on the semiconductor device 10 by adding lithography twice in total.

  FIG. 2 is a graph for explaining the effects of the semiconductor device and the capacitive element in the present embodiment. Hereinafter, a description will be given based on FIG. 1 and FIG.

  In the present embodiment, as described above, the side wall of the opening 44 is not located on the first lower electrode 32 made of the Cu wiring layer, that is, the opening 44 is sized to include the first lower electrode 32. It is characterized by that. This is because it has been confirmed that the reliability deteriorates when the side wall of the opening 44 is positioned on the first lower electrode 32. This will be described in detail below.

  FIG. 2 shows the result of investigating the relationship between the total length of the side wall of the opening 44 and the leakage current of the capacitive element 30 in the structure in which the side wall of the opening 44 exists on the first lower electrode 32 made of the Cu wiring layer. Indicates. Here, the size of each capacitive element 30 is the same for the stacked body 65 and the first lower electrode 32, and only the size of the opening 44 is different. As is apparent from FIG. 2, the leakage current tends to increase as the total length of the side wall of the opening 44 increases. This is considered to be because Cu exposed at the bottom of the opening 44 is scattered by being exposed to plasma and adheres to the side wall of the opening 44 when the opening 44 is etched. Since the etching product of Cu has low volatility, chemical etching hardly occurs. Therefore, the physically scattered Cu scattered material reattaches to the side wall of the opening 44. Cu attached to the bottom surface of the opening 44 is removed by etching, but Cu attached to the side wall of the opening 44 tends to remain. Cu adhering to the side wall of the opening 44 diffuses and reaches the capacitive insulating film 62 and the like, thereby increasing the leakage current of the capacitive element 30.

  Therefore, in the present embodiment, the opening 44 is sized to enclose the first lower electrode 32, so that the side wall of the opening 44 is moved away from the first lower electrode 32, and etched Cu scattered objects are opened. Since it is difficult to adhere to the side wall of the portion 44, the reliability is improved.

  3 to 9 are cross-sectional views of each step showing a method for manufacturing a capacitor and a semiconductor device according to the second embodiment of the present invention. Hereinafter, description will be given based on these drawings.

  The present embodiment is a method of manufacturing the capacitive element 30 and the semiconductor device 10 of FIG. In FIG. 3 to FIG. 9, for the sake of brevity, the uppermost layer of the two or more Cu wiring layers in FIG. 1 is the Cu wiring layer 13, and the lower layers are omitted. In addition, a film omitted in FIG. 1 is also referred to.

  First, as shown in FIG. 3, after forming the Cu wiring layer 13, a wiring cap insulating film 14 for preventing oxidation and diffusion of the Cu wiring is formed. Then, a via layer interlayer insulating film 15 is formed, and a first Cu wiring layer 23 and a via plug 16 for connecting to the same are formed by a damascene method. A wiring cap insulating film 26 is formed on the Cu wiring layer 23. Hereinafter, the “via interlayer insulating film” is abbreviated as “via interlayer film”.

Subsequently, as shown in FIG. 4, after the via interlayer film 33 is formed, the second Cu wiring layer 31 and the first via plug 24 are formed by the damascene method. At this time, the first lower electrode 32 is also formed at the same time, and the via plug 25 that connects the capacitive element and the external circuit is formed in the same manner as the first via plug 24. Then, a SiN or SiCN film is formed as the wiring cap insulating film 41 for the purpose of preventing Cu oxidation and Cu diffusion, and subsequently, SiO ₂ or SiOCH is formed as the hard mask insulating film 42. The two layers of the wiring cap insulating film 41 and the hard mask insulating film 42 become the capacitive element interlayer film 40.

  Subsequently, as shown in FIG. 5, an opening 43 is formed in the hard mask insulating film 42 through a photolithography process and an etching process. At this time, it is important to stop the etching on the wiring cap insulating film 41 using the selective characteristics of dry etching. Further, as shown in the drawing, it is preferable that the end of the opening 43 has a taper shape in order to improve the coverage of a laminate to be formed later. After the opening 43 of the hard mask insulating film 42 is formed, the photoresist is removed by ashing. At this time, since the Cu surface of the first lower electrode 32 is not exposed, the oxidation of Cu by oxygen plasma can be suppressed.

  Next, as shown in FIG. 6, the opening 43 reaching the Cu surface of the first lower electrode 32 is formed by etching the wiring cap insulating film 42 using the opening 43 of the hard mask insulating film 42 as a mask. Also at this time, it is preferable that the end of the opening 44 has a tapered shape in order to improve the coverage of a laminate to be formed later. Further, in the present embodiment, the opening 44 is sized to enclose the first lower electrode 32, so that the side wall 44 a of the opening 44 is moved away from the first lower electrode 32, and etched Cu scattered matter Since it is difficult to adhere to the side wall 44a, the reliability is improved.

  Subsequently, as shown in FIG. 7, a second lower electrode 61, a capacitor insulating film 62, an upper electrode 63, and a film that becomes the etching stop layer 51 are sequentially formed. As the second lower electrode 61, a refractory metal film such as Ti, Ta, or W, an alloy film containing these metal elements, or a nitride film thereof is used. It is also effective to use a laminated film composed of a plurality of films as any of these films. Also, as the second lower electrode 61, it is an important property to suppress the diffusion of Cu element. The film thickness of the second lower electrode 61 is 5 nm to 30 nm in order to realize the thinning of the capacitive element and suppress the diffusion of Cu element. As the capacitor insulating film 62, a silicon nitride film having a thickness of 5 nm or more is formed by a plasma CVD method. When the film thickness of the silicon nitride film is thinner than 5 nm, the insulation property is drastically lowered, so that sufficient reliability cannot be obtained. As the upper electrode 63, a refractory metal film such as Ti, Ta, or W, an alloy film containing these metal elements, or a nitride film thereof is used. Since the upper electrode 63 is exposed to an etching atmosphere during etching of the upper electrode contact, the film thickness is set to a relatively large value of 20 nm or more for the purpose of preventing penetration. The etching stop layer 51 is made of a material such as SiCN or SiN, like the wiring cap insulating film 41.

Subsequently, as shown in FIG. 8, the etching stopper layer 51, the upper electrode 63, the capacitor insulating film 62, and the second lower electrode 61 are patterned in this order in a single lithography process so as to include the opening 44 in a plane. The laminated body 65 is formed. The patterning of the stacked body 65 may be performed by etching the etching stop layer 51 using a photoresist as a mask, and etching the stacked film below the upper electrode 63 using the etching stop layer 51 as a mask after ashing. Alternatively, the etching stop layer 51 to the lower metal layer may be collectively etched using a hard mask such as a SiO ₂ film. In this case, the apparent wiring cap insulating film 41 remains in the device as a laminated structure with the hard mask insulating film 42.

  Finally, as shown in FIG. 9, after forming the via interlayer film 73, the uppermost third Cu wiring layers 75 and 76 and the upper electrode 63 of the capacitive element 30 are formed by the single damascene method or the dual damascene method. The contact plug 72 and the second via plug 71 for connecting the Cu wiring layers are formed. Then, a wiring cap insulating film 77 is formed on the surface including the surfaces of the third Cu wiring layers 75 and 76. The via interlayer film, that is, the wiring interlayer insulating film itself may have a multi-layer structure due to process requirements. Therefore, the via interlayer film 73 is usually composed of a multilayer insulating film. Further, the contact plug 72 to the upper electrode 63 of the capacitive element 30 is shallower than the second via plug 71 between the Cu wiring layers. However, since both the contact plug 72 and the second via plug 71 have the wiring cap insulating films 41 and 51 functioning as an etch stopper at the bottom thereof, the openings with different depths can be formed without any problem. it can.

  As described above, in the method of manufacturing the capacitive element according to this embodiment, the process of forming the capacitive element interlayer film 40 on the surface including the first lower electrode 32 (FIG. 4) and the etching of the capacitive element interlayer film 40 are performed. Thus, the step of forming the opening 44 (FIGS. 5 and 6) and the first lower electrode 61 on the capacitor element interlayer film 40 and the first lower electrode 32 in the opening 44 are formed. Step of sequentially forming a layer, a second layer that becomes the capacitive insulating film 62, and a third layer that becomes the upper electrode 63 (FIG. 7), and the first layer, the second layer, and the third layer are collectively etched. And a step of forming the stacked body 65 (FIG. 8).

  According to the manufacturing method of the present embodiment, since the opening 44 is processed to a size that encloses the first lower electrode 32, the Cu component of the first lower electrode 33 is formed on the side wall of the opening 44 when the opening 44 is formed. Since the second lower electrode 61 is in direct contact with the first lower electrode 32 made of the Cu wiring layer, the reliability can be greatly improved in the structure in which the parasitic resistance can be reduced.

  FIG. 10 shows a semiconductor device according to a third embodiment of the present invention, FIG. 10 [1] is a circuit diagram of the semiconductor device, and FIG. 10 [2] is a plan view of a capacitive element included in the semiconductor device. Hereinafter, description will be given based on this drawing.

A semiconductor device 100 in FIG. 10A is a successive approximation AD (Analog to Digital) conversion circuit, and includes a comparator 101, a capacitor array 102, a switch unit 103, and the like. In order to convert an analog value into a digital value using this circuit, the capacitance element having a capacitance value C is increased by a factor of 2, such as 1, 2, 4, 8,... Each capacitive element is required. When converting to an N-bit digital value, a maximum capacity of 2 ^N-1 C is required, and a total capacity of 2 ^N C is required. In configuring this circuit, it is common to use a capacitor array 102 in which unit capacitor elements having C capacitance are arranged in a ^2N array. For example, it is necessary to arrange 2 ¹⁰ = 1024 capacitors to realize a ¹⁰ -bit AD converter circuit, and 2 ¹² = 4096 capacitors to realize a 12-bit AD converter circuit. Since the successive approximation AD converter circuit itself is well known, detailed description of its operation is omitted.

  FIG. 10 [2] shows a plan configuration diagram of the capacitor array 102. Each capacitive element 30 of the capacitive array 102 has the same configuration as the capacitive element 30 shown in FIG. One capacitive element 30 includes a first lower electrode 32 formed simultaneously with the second Cu wiring layer, a capacitive element interlayer film having an opening 44 in a shape including the first lower electrode 32 therein, and a laminate. 65. In FIG. 10 [2], the layer above the stacked body 65 is removed and shown.

  The stacked body 65 includes a second lower electrode made of TaN having a thickness of 5 nm to 30 nm, a capacitive insulating film made of SiN having a thickness of 5 nm to 15 nm, an upper electrode made of TiN having a thickness of 20 nm to 100 nm, and etching. Consists of stop layers. In the case of this embodiment, since it is necessary to arrange a very large number of capacitive elements 30, it is important to increase the capacitance per unit area and reduce the capacitance area. For this purpose, it is effective to use TaO having a dielectric constant higher than that of SiN as the capacitor insulating film. TaO used as a capacitor insulating film is formed by forming metal Ta with a thickness of 3 to 7 nm by sputtering and oxidizing the film in an oxidizing plasma atmosphere at 350 ° C. In addition, the film may be formed by reactive sputtering in which oxygen is introduced into the sputtering atmosphere, or a vapor phase growth method such as a CVD method may be used.

  According to the semiconductor device 100, since the capacitive element 30 having low parasitic resistance and high reliability is used, the reliability can be improved.

  11 and 12 show a semiconductor device according to a fourth embodiment of the present invention, FIG. 11 [1] is a signal flow diagram, and FIG. 11 [2] is a configuration diagram of a conversion unit in the semiconductor device. 12 [1] is a circuit diagram of the operational amplifier circuit in the conversion unit, and FIG. 12 [2] is a plan view of the capacitive element in the operational amplifier circuit. Hereinafter, description will be given based on these drawings.

  A semiconductor device 200 shown in FIG. 11 [1] is a pipelined AD converter circuit, which converts a plurality of conversion units 201 for each bit, and a digital signal of a predetermined code from a 1-bit signal output from each conversion unit 201. An output code conversion circuit 202 and the like are provided. In the semiconductor device 200, the input analog value is output as a digital signal by one bit from the most significant bit at each stage. N-1 conversion units 201 are required for N-bit conversion. In each stage, when processing of one signal is completed, processing of the next signal can be performed in the next cycle. Therefore, the semiconductor device 200 has a feature that the next signal processing is started without waiting for the output of all bits. Since the pipeline type AD conversion circuit itself is well known, detailed description of its operation is omitted.

  FIG. 11 [2] shows the configuration of the conversion unit 201 at each stage. The conversion unit 201 includes an operational amplifier circuit 210, a sample hold circuit 221, an ADC (Analog-Digital Converter) 222, a DAC (Digital-Analog Converter) 223, and the like. A detailed configuration of the operational amplifier circuit 210 is shown in FIG.

  The operational amplifier circuit 210 in FIG. 12 [1] uses a switched capacitor including an operational amplifier 211, a capacitor circuit 212, and the like. In this configuration, the relative accuracy of the capacitors C1 and C2 is an extremely important factor. The relative accuracy depends on the size of the capacitive element, and the accuracy increases as the size increases.

  FIG. 12 [2] shows a layout of a capacitor applied to the operational amplifier circuit 210. Capacitors C1 and C2 have the same configuration as the capacitive element 30 of FIG. 1, as shown. Capacitors C1 and C2 are adjacent to each other. Since one capacitive element 30 has a relatively large area, the area of the first lower electrode 32 is increased. However, it is difficult to form a continuous large-area pattern for Cu wiring because of its manufacturing problems. Usually, the Cu wiring is formed by removing an excess portion of Cu embedded in the groove portion by polishing by CMP (Chemical Mechanical Polishing). At this time, if a large area of Cu is used, the polishing rate increases at the center, resulting in a concave shape. In order to suppress this, it is effective to form the first lower electrode 32 in a lattice shape as illustrated. Even in this case, the layout is made so that all the parts of the first lower electrode 32 exist only inside the opening 44. The stacked body 65 is formed in a shape that includes the opening 44. In FIG. 12 [2], the layer above the stacked body 65 is removed and shown.

  According to the semiconductor device 200, since the capacitive element 30 having low parasitic resistance and high reliability is used, the reliability can be improved.

  FIG. 13 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention. Hereinafter, description will be given based on this drawing.

  The semiconductor device 300 according to this embodiment includes an AD conversion circuit 301, a wireless input circuit 302, a PLL circuit 303, a wired input / output circuit 304, a digital circuit 305, and a storage circuit 306 mounted on one chip. The AD conversion circuit 301 includes a capacitive element 30a, the wireless input circuit 302 includes a capacitive element 30b, the PLL circuit 303 includes a capacitive element 30c, and the digital circuit 305 includes a capacitive element 30d. The capacitive elements 30a to 30d have the same configuration as the capacitive element 30 in FIG.

  The AD conversion circuit 301 has been described in the third embodiment or the fourth embodiment, and a DA conversion circuit can also be mounted in the same manner. The wireless input circuit 302 uses the capacitive element 30b as a pass capacitor for passing a wireless signal from the outside. At this time, since the high frequency response is important, the characteristic of the low parasitic resistance of the capacitive element 30b is extremely effective. In addition, in the analog signal processing in the wireless input circuit 302, a circuit that passes only a specific frequency is also mounted, and the capacitive element 30b is also used in that circuit. The PLL circuit 303 is for generating a specific frequency, and uses the capacitive element 30c as a loop filter for feeding back a frequency shift. Also in the digital circuit 305, the capacitive element 30d works effectively in order to reduce simultaneous switching noise generated when a large number of elements are switched simultaneously. Thus, although the capacitive element is used in various circuits, the capacitive elements 30a to 30d according to the present invention can be used for all applications, and are extremely effective in the semiconductor device 300 having a plurality of functions. It becomes an element.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-009654 for which it applied on January 18, 2008, and takes in those the indications of all here.

  The present invention relates to a capacitive element incorporated in, for example, an LSI (Large Scale Integrated circuit), and more specifically, to a capacitive element composed of a conductive upper electrode film, a capacitive insulating film, and a conductive lower electrode in an LSI having multilayer wiring. Used.

It is sectional drawing which shows the capacitive element and semiconductor device in 1st embodiment of this invention. It is a graph for demonstrating the effect of the capacitive element and semiconductor device of this invention. It is sectional drawing of the process (the 1) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 2) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 3) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 4) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 5) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 6) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. It is sectional drawing of the process (the 7) which shows the manufacturing method of the capacitive element and semiconductor device in 2nd embodiment of this invention. The semiconductor device in 3rd embodiment of this invention is shown, FIG. 10 [1] is a circuit diagram of a semiconductor device, FIG. 10 [2] is a top view of the capacitive element contained in a semiconductor device. The semiconductor device in 4th embodiment of this invention is shown, FIG. 11 [1] is a signal flow figure, FIG. 11 [2] is a block diagram of the conversion part in a semiconductor device. The semiconductor device in 4th embodiment of this invention is shown, FIG. 12 [1] is a circuit diagram of the operational amplifier circuit in a conversion part, FIG. 12 [2] is a top view of the capacitive element in an operational amplifier circuit. . It is a top view which shows the semiconductor device in 5th embodiment of this invention.

Explanation of symbols

10, 100, 200, 300 Semiconductor device 11 CMOS transistor layer 12 Cu multilayer wiring layer 13 Cu wiring layer 14 wiring cap insulating film 15 via interlayer film 16 via plug 23 first Cu wiring layer 24 first via plug 25 via plug 26 wiring cap Insulating films 30, 30a, 30b, 30c, 30d Capacitor element 31 Second Cu wiring layer 32 First lower electrode 33 Via interlayer film 40 Capacitor element interlayer film (interlayer insulating film)
41 Wiring cap insulating film 42 Hard mask insulating film 43 Hard mask insulating film opening 44 Capacitor element interlayer opening 51 Etching stop layer 61 Second lower electrode 62 Capacitor insulating film 63 Upper electrode 71 Second via plug 72 Contact Plugs 75 and 76 Third Cu wiring layer 101 Comparator 102 Capacitance array 210 Operational amplifier circuit 211 Operational amplifier 301 AD conversion circuit 302 Wireless input circuit 303 PLL circuit 304 Wired input / output circuit 305 Digital circuit 306 Memory circuit

Claims (10)

A first lower electrode made of a Cu wiring layer; an interlayer insulating film provided on the first lower electrode and having an opening sized to enclose the first lower electrode; and the opening. A stacked body in which a second lower electrode, a capacitor insulating film and an upper electrode are sequentially provided on the first lower electrode and the interlayer insulating film,
A capacitive element comprising: A first Cu wiring layer; a second Cu wiring layer connected to the first Cu wiring layer via a via plug; and a capacitive element according to claim 1;
The first lower electrode is a Cu wiring layer that is connected to the first Cu wiring layer through a via plug and formed in the same layer as the second Cu wiring layer.
A semiconductor device. A third Cu wiring layer connected to the second Cu wiring layer via a via plug above;
The upper electrode is connected to the third Cu wiring layer through a contact plug formed in the same layer as the via plug,
The semiconductor device according to claim 2. The second lower electrode and the upper electrode have the same planar shape,
The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. The interlayer insulating film includes a wiring cap insulating film having a property of preventing oxidation of Cu wiring layer and diffusion of Cu element, and a hard mask made of a material different from the wiring cap insulating film provided on the wiring cap insulating film Having two layers with insulating film,
The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. The wiring cap insulating film is made of SiCN or SiC, and the hard mask insulating film is made of SiO ₂ or SiCOH.
The semiconductor device according to claim 5. The opening has a tapered shape with a large opening on the upper side,
The semiconductor device according to claim 2, wherein: The capacitive insulating film is made of SiN having a thickness of 5 nm or more.
The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. The capacitive insulating film is made of tantalum oxide formed by a plasma oxidation method.
The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. A first lower electrode made of a Cu wiring layer; an interlayer insulating film provided on the first lower electrode and having an opening sized to enclose the first lower electrode; and the opening. In the method of manufacturing a capacitive element including the second lower electrode, the capacitive insulating film, and the laminated body provided in this order on the first lower electrode and the interlayer insulating film,
Forming the interlayer insulating film on a surface including the first lower electrode;
Forming the opening by etching the interlayer insulating film;
A first layer to be the second lower electrode, a second layer to be the capacitive insulating film, and a third layer to be the upper electrode are formed on the interlayer insulating film and the first lower electrode in the opening. A step of sequentially forming a film;
Forming the laminate by etching the first layer, the second layer, and the third layer together;
The manufacturing method of the capacitive element characterized by including

Images