JP5432662B2 - Power supply wiring structure design method, semiconductor device manufacturing method, and semiconductor device - Google Patents

Description

  The present invention relates to a method for designing a power supply wiring structure, a method for manufacturing a semiconductor device, and a semiconductor device. More specifically, the present invention relates to a method for designing a power supply wiring structure for supplying a stable power supply voltage, a method for manufacturing a semiconductor device using this design method, and a semiconductor device provided with this power supply wiring structure.

  In ultra-high integrated circuits (ULSI) formed on a Si semiconductor substrate, design dimensions are being reduced in order to pursue cost reduction, performance improvement, and power consumption reduction. The function is improved by miniaturization and the number of integrated elements is increased, and the cost is reduced by reducing the chip size. Further, by improving the degree of integration, it becomes possible to mount a plurality of circuit blocks having different functions, and by reducing the number of components, it is possible to reduce the cost of a device incorporating a ULSI chip. Such mixed mounting of circuit blocks having different functions can realize not only cost reduction but also additional performance improvement such as improvement of communication speed. Furthermore, since the operating voltage can be reduced by miniaturization, the power consumption of circuit blocks having the same function can be suppressed.

  However, as ULSI integration progresses, power supply noise as described below becomes a serious problem. As the miniaturization advances, the voltage reduction is promoted. However, the number of elements integrated at the same time increases rapidly, so that the amount of current consumed increases. Since the performance of each active element is improved, the current driving capability of a single element is also improved, so that the total current consumed increases rapidly. In addition, with the miniaturization of elements, the operating frequency continues to increase and the switching time is shortened. That is, since the amount of current at the time of switching increases and the switching time is shortened, di / dt that is the time change of the current increases rapidly. L · di / dt obtained by multiplying the time variation of the current by the inductance L of the circuit is an inductive voltage fluctuation and is called simultaneous switching noise. Simultaneous switching noise fluctuates the power supply potential, and in some cases, the logic state may be reversed.

  As described above, as the miniaturization progresses, the power supply voltage decreases, and the fluctuation voltage due to noise increases, so that the noise margin decreases at an accelerated rate. Such inductive noise can be reduced by lowering the impedance of the circuit, and power supply fluctuations can be suppressed by adding capacitance to the circuit. Such a capacity is called a decoupling capacity. In a conventional ULSI, a MOS capacitor obtained when a transistor is formed is used as a decoupling capacitor. However, with the progress of miniaturization, there is a problem that the insulating film thickness of the MOS capacitor becomes thinner and the leakage current of the insulating film increases rapidly. In addition, since the noise margin is drastically reduced, the absolute capacitance value is also insufficient, and the chip area tends to increase due to the decoupling capacitance inserted to stabilize the power supply potential.

  In order to avoid the above problems, it is necessary to prepare a decoupling capacitor using an insulating film having a dielectric constant higher than that of the MOS capacitor in the wiring layer. If a capacitor can be incorporated in the wiring layer, it can be placed over the transistor on a plane, so that the installation area can be made larger than the MOS capacitor. Further, by increasing the dielectric constant, the capacitance value in the same area can be increased, and a large capacitance can be installed in a limited area.

  In addition, regarding noise countermeasures during high-speed operation, it is necessary to consider not only a capacity problem but also a response problem. The power supply noise in high-speed operation contains a lot of high-frequency components. The capacitive element has a parasitic resistance component of the electrode, and has an effect of deteriorating responsiveness to noise. When the operating speed reaches the gigahertz region, the influence of the parasitic resistance of the electrode becomes obvious, and it becomes difficult to sufficiently exhibit the performance of the decoupling capacitance. Therefore, it is necessary to reduce the electrode resistance as much as possible.

  The dynamic voltage fluctuation of the power supply voltage has been described above. However, it is necessary to consider the influence of a static voltage drop due to the resistance component when supplying power. That is, there may be a problem that the supply voltage is not constant in each part of the ULSI chip due to the resistance component of the power supply line itself.

  In order to avoid this problem, a mesh power supply wiring method using multilayer wiring is often used. Specifically, the multi-layer mesh power supply wiring method is provided with a plurality of power supply wiring layers above and below a logic element. GND lines) are wired in different arrangement directions (wiring directions) in different layers, and GND lines and VDD lines are connected to each other by vias or the like between layers.

  Here, Patent Document 1 and Patent Document 2 describe a method for supplying a power supply that is spatially and temporally stable over the entire ULSI chip. Patent Document 3 describes a layout structure of a capacitor element formed of a wiring layer.

JP 2002-270771 A JP 2007-134468 A JP 2007-220716 A

  The causes that impair the stabilization of the power supply are intricately intertwined, and it is often difficult to specify the capacity required for the stabilization of the power supply at the circuit design stage. In such a case, the capacity required for stabilizing the power supply is specified after looking at the actual circuit operation. However, if the required capacity is identified by looking at the circuit operation, and then the design is changed to add the required capacity to the circuit, the work efficiency is poor.

  Therefore, a technique is desired in which a predetermined capacity is designed in advance so as to be added to the circuit, and the capacity actually added to the circuit can be changed only by a simple design change.

  In addition, when no capacity is required to stabilize the power supply, the manufactured semiconductor can be manufactured by removing the process of forming a predetermined capacity that has been designed in advance without changing other processes. A technique that does not cause problems in the apparatus is desired. According to this technique, there is no work to change the mask design, and the number of steps can be deleted, and it is expected to effectively reduce the manufacturing cost.

  According to the present invention, there is provided a design method for a power supply wiring structure provided in a layer above a circuit formed on a substrate, wherein a first wiring and a second wiring for supplying different potentials are provided above the circuit. One or more MIM capacitor elements arranged in one layer and having a lower electrode, a capacitor insulating film, and an upper electrode laminated in this order are arranged in a second layer above the first layer, and the same as the first wiring. A third wiring having a potential and a fourth wiring having the same potential as the second wiring are arranged in a third layer above the second layer, and the first wiring and the third wiring overlap in a plan view. When the region is a first region and the region where the second wiring and the fourth wiring overlap in plan view is the second region, the first lower electrode of the first MIM capacitor element includes at least one first region and The first M is disposed so as to overlap with at least one second region in plan view. The first upper electrode of the M capacitive element does not overlap at least one region where the first region and the first lower electrode overlap in a plan view, and the second region and the first lower electrode in a plan view. The first via for connecting the first upper electrode and the fourth wiring is disposed so as to overlap the second region in plan view, and is arranged so as to overlap with the second region. A method of designing a power supply wiring structure is provided in which a second via for connecting one lower electrode and the third wiring is arranged to overlap the first region in plan view.

  According to the present invention, the first wiring and the second wiring for supplying different potentials in the first layer above the circuit formed on the substrate, and the second layer above the first layer are provided. One or more MIM capacitive elements in which a lower electrode, a capacitive insulating film, and an upper electrode are stacked in this order, and a third wiring having the same potential as the first wiring, provided in a third layer above the second layer And a fourth wiring having the same potential as that of the second wiring, a first via connecting the upper electrode and the fourth wiring, and a second via connecting the lower electrode and the third wiring. Then, if a region where the first wiring and the third wiring overlap in a plan view is a first region, and a region where the second wiring and the fourth wiring overlap in a plan view is a second region, the first MIM The first lower electrode of the capacitor element includes at least one first region and at least one first electrode. The first upper electrode of the first MIM capacitor element does not overlap with at least one region in which the first region and the first lower electrode overlap in plan view, And, when viewed in plan, the second region and at least one region where the first lower electrode overlaps are disposed so as to overlap, and the first via is disposed so as to overlap with the second region in plan view, A semiconductor device having a power supply wiring structure in which the second via is disposed so as to overlap the first region in plan view is provided.

  In the present invention, the MIM capacitance element is disposed between the layer in which the first wiring and the second wiring are disposed and the layer in which the third wiring and the fourth wiring are disposed, and the third wiring has the same potential as the first wiring. In addition, the fourth wiring has the same potential as the second wiring. The upper electrode and lower electrode of the MIM capacitor element are connected to the third wiring or the fourth wiring. A via connecting the third wiring and the MIM capacitive element is provided in a region where the first wiring and the third wiring overlap in a plan view, and a via connecting the fourth wiring and the MIM capacitive element is a second wiring in the plan view. The fourth wiring is provided in the overlapping region.

  In the present invention, since the MIM capacitor element and the wiring disposed above and below the MIM capacitor element can be formed independently, the capacitance insulating film of the MIM capacitor element is thinned to increase the capacity, and the distance between the upper and lower wires is sufficiently increased. Can be separated. Therefore, it is possible to achieve both an increase in the stabilization capacitance and a reduction in parasitic capacitance between the wirings.

  In the present invention, the MIM capacitance element connected to the circuit can be changed only by changing the layout of the via connecting the MIM capacitance element and the third wiring and the fourth wiring. That is, for example, the MIM capacitor connected to the circuit can be changed only by a simple process of changing the via lithography mask pattern.

  Further, in the present invention, when the step of arranging the MIM capacitor element is omitted without changing the contents of other manufacturing steps, the vias connecting the third wiring and the MIM capacitor element have the third wiring and the first wiring. A via that connects the fourth wiring and the MIM capacitor element is a via that connects the fourth wiring and the second wiring. Even in such a state, in the present invention, the third wiring is at the same potential as the first wiring, and the fourth wiring is at the same potential as the second wiring. There is nothing. That is, according to the present invention, the step of arranging the MIM capacitor element can be eliminated without changing the contents of other manufacturing steps.

  According to the present invention, a semiconductor device that supplies a stable power supply voltage is provided. In addition, a power supply wiring structure design method and a semiconductor device manufacturing method for supplying a stable power supply voltage are provided.

1 is a cross-sectional structure diagram schematically illustrating an example of a semiconductor device of Embodiment 1. FIG. FIG. 3 is a plan transparent view schematically showing an example of the power supply wiring structure of the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a power supply wiring structure according to the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a power supply wiring structure according to the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a power supply wiring structure according to the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a power supply wiring structure according to the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a power supply wiring structure according to the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a method for manufacturing the power supply wiring structure of the first embodiment. FIG. 3 is a cross-sectional structure diagram schematically illustrating an example of a method for manufacturing the power supply wiring structure of the first embodiment. 3 is a top transparent view schematically showing an example of a power supply wiring structure of Embodiment 1. FIG. 3 is a top transparent view schematically showing an example of a power supply wiring structure of Embodiment 1. FIG. FIG. 6 is a cross-sectional structure diagram schematically showing an example of a method for manufacturing a power supply wiring structure of Embodiment 2. FIG. 6 is a cross-sectional structure diagram schematically showing an example of a method for manufacturing a power supply wiring structure of Embodiment 2.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
<Embodiment 1>

  FIG. 1 is a cross-sectional structure diagram schematically showing an example of the semiconductor device of the present embodiment. This semiconductor device has two or more multilayer wirings formed on a substrate, 11 is a transistor layer composed of CMOS, and 12 is a contact via for connecting the transistor and the lowermost wiring layer. Above these, there is a multilayer wiring layer 13 composed of an arbitrary number of layers, and a power supply wiring structure (above 21) connected via vias (not shown) arranged at appropriate positions thereon. Layer). In the semiconductor device of the present embodiment, the configuration of the layer below the power supply wiring structure (layer above 21) is not particularly limited.

  Next, an example of the power supply wiring structure of this embodiment will be described.

  As shown in FIG. 1, the power supply wiring structure of the present embodiment has a first potential for supplying different potentials in the first layer above the circuit (eg, layers 11, 12, 13) formed on the substrate. The wiring 21 and the second wiring 22 (not shown) are included. Further, in the second layer above the first layer, one or more MIM capacitor elements in which the lower electrode 34, the capacitor insulating film 33, and the upper electrode 32 are stacked in this order are provided. Further, a third wiring 51 having the same potential as the first wiring 21 and a fourth wiring 52 having the same potential as the second wiring 22 (not shown) are provided in the third layer above the second layer. Furthermore, it has the 2nd via | veer 41b for connecting the lower electrode 34 and the 3rd wiring 51, and the 1st via | veer 42b (not shown) for connecting the upper electrode 32 and the 4th wiring 52. The third via 41a for connecting the upper electrode 32 and the third wiring 51 and the fourth via 42a (not shown) for connecting the lower electrode 34 and the fourth wiring 52 may be provided. Good. Further, the thickness of the capacitor insulating film 33 of the MIM capacitor element may be a silicon nitride film of 8 nm or more and 25 nm or less.

  FIG. 2 is a plan transparent view of the power supply wiring structure of FIG. 1 as viewed from the top to the bottom in the drawing. 3 is a sectional view taken along the line AA ′ in FIG. 2, FIG. 4 is a sectional view taken along the line BB ′ in FIG. 2, and FIG. 5 is a sectional view taken along the line CC ′ in FIG.

  As shown in FIG. 2, the first wiring 21 and the second wiring 22 may be formed in a straight line, and may be arranged in parallel with each other and alternately. The third wiring 51 and the fourth wiring 52 may be formed in a straight line, and may be alternately arranged in parallel with each other. Then, the first wiring 21 and the second wiring 22, and the third wiring 51 and the fourth wiring 52 may be arranged so as to be orthogonal to each other in plan view. In addition, although the thickness of the 1st wiring 21, the 2nd wiring 22, the 3rd wiring 51, and the 4th wiring 52 is arbitrary design matters, the 1st wiring 21 and the 2nd wiring 22 have the same thickness, Further, it is desirable that the third wiring 51 and the fourth wiring 52 have the same thickness. The first wiring 21, the second wiring 22, the third wiring 51, and the fourth wiring 52 may all have the same thickness. The spacing between the first wiring 21 and the second wiring 22 and the spacing between the third wiring 51 and the fourth wiring 52 are also optional design matters.

  When the first wiring 21 and the third wiring 51 are wirings for supplying a power supply potential, the second wiring 22 and the fourth wiring 52 are wirings for supplying a ground potential. Conversely, when the first wiring 21 and the third wiring 51 are wirings that supply a ground potential, the second wiring 22 and the fourth wiring 52 are wirings that supply a power supply potential. The first wiring 21 and the second wiring 22 may be made of a metal containing 95% or more of Cu. The third wiring 51 and the fourth wiring 52 may be made of a metal containing 95% or more of Cu or a metal containing 95% or more of Al.

  Here, a region where the first wiring 21 and the third wiring 51 overlap in plan view is defined as a first region 81, and a region where the second wiring 22 and fourth wiring 52 overlap in plan view is defined as a second region 82. The first wiring 21 and the third wiring 51 are arranged so as to form one or more first regions 81. The second wiring 22 and the fourth wiring 52 are arranged so as to form one or more second regions 82.

  As shown in FIG. 2, the first lower electrode 34b (square electrode in the figure) of the first MIM capacitor element (upper left and lower right MIM capacitor elements in the figure) has at least one first region 81 and It arrange | positions so that it may overlap with at least 1 2nd area | region 82 by planar view. The first upper electrode 32b (L-shaped electrode in the drawing) of the first MIM capacitor element does not overlap at least one region where the first region 81 and the first lower electrode 34b overlap in plan view. And it arrange | positions so that the 2nd area | region 82 and the 1st lower electrode 34b may overlap with at least 1 area | region in planar view. The first via 42b is disposed so as to overlap the second region 82 in a plan view, and the second via 41b is disposed so as to overlap the first region 81 in a plan view. That is, the first via 42b is disposed in a region where the first upper electrode 32b, the first lower electrode 34b, and the second region 82 overlap in plan view. Further, the second via 41b is disposed in a region where the first lower electrode 34b and the first region 81 overlap in a plan view and does not overlap the first upper electrode 32b.

  In addition, as shown in FIG. 2, the power supply wiring structure of the present embodiment can also include a second MIM capacitor (upper right and lower left MIM capacitors in the figure). The second lower electrode 34a (square electrode in the drawing) of the second MIM capacitor element is disposed so as to overlap with at least one first region 81 and at least one second region 82 in plan view. The second upper electrode 32a (L-shaped electrode in the drawing) of the second MIM capacitor element does not overlap at least one region where the second region 82 and the second lower electrode 34a overlap in plan view. In addition, the first region 81 and at least one region where the second lower electrode 34a overlaps are disposed so as to overlap in plan view. The third via 41a is disposed so as to overlap the first region 81 in a plan view, and the fourth via 42a is disposed so as to overlap the second region 82 in a plan view. That is, the third via 41a is arranged in a region where the second upper electrode 32a, the second lower electrode 34a, and the first region 81 overlap in plan view. The fourth via 42a is disposed in a region where the second lower electrode 34a and the second region 82 overlap in a plan view and does not overlap the second upper electrode 32a. The second MIM capacitor element may be disposed adjacent to the first MIM capacitor element.

  Here, the first MIM capacitive element “connects the upper electrode and the fourth wiring, and connects the lower electrode and the third wiring”, whereas the second MIM capacitive element “connects the upper electrode and the third wiring. The first MIM capacitive element and the second MIM capacitive element are different in that they are connected and the lower electrode and the fourth wiring are connected. That is, the upper electrode 32b of the first MIM capacitive element and the lower electrode 34a of the second MIM capacitive element have the same potential, and the lower electrode 34b of the first MIM capacitive element and the upper electrode 32a of the second MIM capacitive element. And have the same potential. Thus, the polarity of the voltage applied to the upper and lower electrodes is reversed between the first MIM capacitive element and the second MIM capacitive element.

  In the MIM capacitor element, asymmetry occurs at the interface between the electrode and the capacitor insulating film, the capacitance characteristics become asymmetric, the parasitic resistance becomes asymmetric due to the difference between the upper and lower electrode shapes, and the contact resistances of the upper and lower electrodes are mutually different. It can happen that the parasitic resistance becomes asymmetric due to the difference. As described above, when the parasitic resistance and the capacitance characteristic become asymmetric, the asymmetry occurs in the responsiveness to the power supply fluctuation, resulting in malfunction. For this reason, the stability of the circuit can be ensured by appropriately disposing the MIM capacitor element in which the potentials applied to the upper electrode and the lower electrode are reversed to each other in the power supply wiring structure. Desirably, the number of first MIM capacitive elements and the number of second MIM capacitive elements should be approximately the same. In order to secure local symmetry, the first MIM capacitor and the second MIM capacitor may be arranged adjacent to each other.

  In the power supply wiring structure of the present embodiment, the first wiring 21 and the third wiring 51 may be connected by vias 43 arranged at appropriate positions, as shown in FIGS. Further, the second wiring 22 and the fourth wiring 52 may be connected by a via 44 disposed at an appropriate position.

  Here, in the case of the power supply wiring structure of the present embodiment as shown in FIG. 2, the first via 42b connected to the first lower electrode 34b of the first MIM capacitive element and the first upper electrode of the same MIM capacitive element The second via 41 b connected to 32 b is not arranged on the same straight line parallel to the first wiring 21 and the second wiring 22. Further, the first via 42 b and the second via 41 b are not arranged on the same straight line parallel to the third wiring 51 and the fourth wiring 52. This relationship also holds in the second MIM capacitor element.

  That is, in one MIM capacitor element, a via connected to one electrode (upper electrode or lower electrode) and a via connected to the other electrode (lower electrode or upper electrode) are connected to the first wiring 21 and the second wiring. 22 on the same straight line parallel to 22 or on the same straight line parallel to the third wiring 51 and the fourth wiring 52. Further, even when a plurality of connection vias are provided in each of the upper and lower electrodes of one MIM capacitor element, any one of all the vias connected to the upper electrode and all the vias connected to the lower electrode Any one of them is not arranged on the same straight line parallel to the first wiring 21 and the second wiring 22 or on the same straight line parallel to the third wiring 51 and the fourth wiring 52. This configuration is a characteristic point of the present invention.

  The above relationship is that the first wiring 21 and the second wiring 22 are arranged in parallel with each other, and the third wiring 51 and the fourth wiring 52 are arranged in parallel with each other, and the first wiring 21 and the second wiring 22 are If the third wiring 51 and the fourth wiring 52 are arranged so as to be orthogonal to each other in plan view, the positional relationship between the first wiring 21 and the second wiring 22, the third wiring 51 and the fourth wiring 52, and so on. This is true regardless of the positional relationship. For example, the first wiring 21 and the second wiring 22 are not arranged alternately, and the third wiring 51 and the fourth wiring 52 are not arranged alternately.

  In the power supply wiring structure of the present embodiment, the MIM capacitor element and the wiring disposed above and below the MIM capacitor element are formed independently. Therefore, the capacitor insulating film of the MIM capacitor element is thinned to increase the capacity, and It is possible to sufficiently separate the distance. Therefore, it is possible to achieve both an increase in the stabilization capacitance and a reduction in parasitic capacitance between the wirings.

  The power supply wiring structure as described above can be realized by the following power supply wiring structure design method. That is, a method for designing a power supply wiring structure provided in a layer above a circuit formed on a substrate, wherein a first wiring and a second wiring for supplying different potentials are placed in a first layer above the circuit. One or more MIM capacitor elements arranged in this order and having a lower electrode, a capacitor insulating film, and an upper electrode laminated in this order are disposed in a second layer above the first layer, and a third potential having the same potential as that of the first wiring is disposed. A wiring and a fourth wiring having the same potential as the second wiring are arranged in the third layer above the second layer, and a region where the first wiring and the third wiring overlap in the plan view is first. If the second region is a region where the second wiring and the fourth wiring overlap in plan view, the first lower electrode of the first MIM capacitor element includes at least one first region and at least one first region. The first MIM container is disposed so as to overlap with the two regions in plan view. The first upper electrode of the element does not overlap at least one region where the first region and the first lower electrode overlap in a plan view, and the second region and the first lower electrode overlap in a plan view. The first via that connects the first upper electrode and the fourth wiring is disposed so as to overlap with at least one region, and is disposed so as to overlap with the second region in plan view, The second via for connecting the third wiring can be realized by a method for designing a power supply wiring structure arranged so as to overlap the first region in plan view.

  Further, the second MIM capacitor element is disposed adjacent to the first MIM capacitor element, and the second lower electrode of the second MIM capacitor element includes at least one first region and at least one one region. The second upper electrode of the second MIM capacitor element is arranged so as to overlap with the second region in plan view, and the second upper electrode of the second MIM capacitor element overlaps with at least one region where the second region and the second lower electrode overlap in plan view. And the third via that is arranged so as to overlap at least one region where the first region and the second lower electrode overlap in a plan view and connects the second upper electrode and the third wiring is a plan view. The fourth via that is disposed so as to overlap the first region and connects the second lower electrode and the fourth wiring may overlap the second region in plan view.

  Next, an example of a method for manufacturing a semiconductor device using the design method for the power supply wiring structure will be described. In the method of manufacturing a semiconductor device according to the present embodiment, a Si substrate, a CMOS transistor formed on the Si substrate, a contact plug, and a multi-layer wiring having an arbitrary number of layers positioned below or above the two-layer wiring After forming the layers and the like, a power supply wiring structure is formed thereon. The configuration other than the power supply wiring structure can be realized in accordance with the prior art, and thus the description thereof is omitted here. Hereinafter, an example of the method for manufacturing the power supply wiring structure of the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 8A, the first wiring 21 and the second wiring 22 (not shown) for supplying the power supply potential VDD or the ground potential GND are formed in the same layer. If the first wiring 21 is a VDD wiring, the second wiring 22 is a GND wiring, and if the first wiring 21 is a GND wiring, the second wiring 22 is a VDD wiring. The first wiring 21 and the second wiring 22 are formed to be parallel to each other in a planar layout.

  The first wiring 21 and the second wiring 22 are grooves in which a desired wiring pattern is transferred in a first insulating film containing at least two elements of Si, O, C, H, and N. After the metal film is embedded in the groove, the excess metal film is removed by polishing. Here, the metal film may be made of a conductive adhesion film that secures adhesion to the first insulating film, a conductive barrier film that suppresses mutual diffusion of elements, and a main wiring metal. The conductive adhesion film and the conductive barrier film are selected from refractory metals such as Ta and Ti, or nitrides thereof, and are formed by a technique such as PVD or CVD. Note that the conductive adhesion film and the conductive barrier film are collectively described as one layer in the drawing. The main wiring metal is formed by a method such as a PVD method, a CVD method, or a plating method using copper or an alloy material containing 95% or more of copper. After forming the first wiring 21 and the second wiring 22, an insulating barrier layer is formed over the entire surface (not shown) that prevents oxidation of the wiring material and suppresses diffusion of elements constituting the wiring material. The surface may be protected. As this insulating barrier layer, a film containing Si and an element selected from one or more of O, C, H, and N, preferably a film containing Si and N, is used.

  Next, as shown in FIG. 8B, the MIM lower insulating film 35, the conductive film 34A that becomes the lower electrode 34 of the MIM capacitor, the insulating film 33A that becomes the capacitor insulating film 33 of the MIM capacitor, and the MIM capacitor A conductive film 32A serving as the upper electrode 32 and an etch stopper layer 31 functioning as an etching stop layer during via etching are sequentially stacked. Here, as the MIM lower insulating film 35, a film containing at least two elements of Si, O, C, H, and N is used.

  The conductive film 34A to be the lower electrode 34 may be a refractory metal such as Ti or Ta, a nitride of these metals, or a stacked structure of a plurality of conductive films, and is formed by a method such as PVD or CVD. The minute unevenness of the lower electrode 34 affects the reliability of the capacitive element. For this reason, it is very important to control the surface of the conductive film 34 </ b> A that becomes the lower electrode 34. For example, when Ti or TiN is used, unevenness reflecting the crystal grain structure is observed on the surface, though it is inexpensive. Here, when Ta or TaN is formed into a film by the PVD method, the surface unevenness is greatly improved. This is because Ta, which is a heavy element, has excellent straightness during PVD film formation, and the film formation proceeds so as to fill the concave and convex portions. In addition, the fact that Ta or TaN does not have a columnar crystal grain structure is effective in reducing surface irregularities.

  The material and film thickness of the capacitive insulating film 33 are important factors that determine the characteristics of the capacitance. In order to realize a high capacity, it is preferable to use a SiN film having a film thickness of 8 to 25 nm. Alternatively, when a metal oxide that is an oxide such as Ta, Ti, Zr, Hf, or La is used, high reliability can be ensured by increasing the physical film thickness by taking advantage of its high dielectric constant. I can do it. The insulating film 33A to be the capacitor insulating film 33 is formed by a CVD method or is obtained by oxidizing a metal film formed by a PVD method. Examples of the oxidation treatment include a method of performing heat treatment in an oxygen-containing atmosphere at a temperature range of 250 to 350 ° C., and a method of generating plasma in a similar atmosphere to promote oxidation.

  The conductive film 32A to be the upper electrode 32 may be a refractory metal such as Ti or Ta, a nitride of these metals, or a stacked structure of a plurality of conductive films, and is formed by a method such as a PVD method or a CVD method. The etch stopper layer 31 is a film containing Si and an element selected from one or more of O, C, H, and N, preferably a film containing Si and N.

  Subsequently, as shown in FIG. 8C, the conductive film 32A to be the upper electrode 32 is patterned by a lithography process dedicated to MIM. At this time, a mark pattern may be formed in the MIM lower insulating film 35 in order to facilitate alignment between the upper electrode 32 and the lower layer wiring 21 or 22. In that case, a lithography process for forming a mark pattern is also required. For patterning the conductive film 32A to be the upper electrode 32, the etch stopper layer 31 and the conductive film 32A are simultaneously etched by a dry etching method. At this time, the etching is stopped on the insulating film 33A to be the capacitive insulating film 33 by utilizing the etching selectivity of the conductive film 32A and the insulating film 33A to be the capacitive insulating film 33.

  Next, as shown in FIG. 9D, the MIM upper insulating film 36 is formed after the conductive film 34A to be the lower electrode 34 is patterned by another lithography process dedicated to the MIM. In the patterning of the conductive film 34A to be the lower electrode 34, the insulating film 33A to be the capacitive insulating film 33 and the conductive film 34A are simultaneously etched by a dry etching method. At this time, the etching is stopped on the lower MIM insulating film 35 using the etching selectivity between the conductive film 34A and the lower MIM insulating film 35.

  Next, the MIM upper insulating film 36 has unevenness due to the MIM pattern formed on the surface thereof. Therefore, the unevenness is flattened by polishing by the CMP method. Thereafter, an interlayer insulating film for forming the upper layer wiring (the third wiring 51 and the fourth wiring 52) is formed. As shown in FIG. 9E, the upper portion of the MIM capacitor element is formed by a normal dual damascene process. A via hole reaching the electrode 32, the lower electrode 34, the lower wiring (the first wiring 21 or the second wiring 22), and a groove for forming the upper third wiring 51 and the fourth wiring 52 are formed. Thereafter, vias 43 and 44 (not shown), a third wiring 51 and a fourth wiring 52 as shown in FIG. A method for forming the vias 43 and 44 (not shown) and the third wiring 51 and the fourth wiring 52 can be realized in accordance with the method for forming the first wiring 21 and the second wiring 22. Therefore, detailed description here is omitted.

  Here, in the design method of the power supply wiring structure of the present embodiment, the number of MIM capacitive elements necessary for power supply stabilization is calculated based on the actual operation of the circuit, and at least the calculated number of MIM capacitive elements are connected to the circuit. As described above, the layout of the first and second vias and / or the third and fourth vias can be changed. In other words, the number (capacitance) of MIM capacitors connected to the circuit can be changed simply by changing the layout of the first and second vias and / or the third and fourth vias. . For example, in the case of the semiconductor device manufacturing method as described above, the number (capacitance) of MIM capacitor elements connected to the circuit can be changed only by changing the lithography mask pattern of the via.

  In such a case, in the initial design stage, the first via and the second via and / or the third via and the fourth via are designed to be connected to all the predetermined number of designed MIM capacitors. When the number of MIM capacitors required to stabilize the power supply is calculated based on the actual operation of the circuit, it is given to the circuit only by changing the via layout so that at least the calculated number of MIM capacitors are connected to the circuit. Capacity can be changed. In such a case, there may be an MIM capacitor element that is not connected to the circuit in some cases. A feature of the configuration of the present embodiment is that an MIM capacitor element that is not connected to such a circuit can exist in the power supply wiring structure.

  In the design method of the power supply wiring structure of the present embodiment, when the number of MIM capacitance elements necessary for power supply stability determined based on the actual operation of the circuit is 0 (zero), the contents of other steps The step of arranging the MIM capacitor element without changing can be eliminated. Even if it does in this way, in the design method of the power supply wiring structure of this embodiment, a malfunction will not arise in the semiconductor device manufactured. Hereinafter, the reason will be described.

  FIG. 6 is a cross-sectional view taken along the line AA ′ in a state where all the MIM capacitor elements are removed in the power supply wiring structure shown in FIG. Further, FIG. 7 shows a cross-sectional view of BB ′ in a state where all the MIM capacitor elements are removed from the power supply wiring structure shown in FIG. The power supply wiring structure shown in these drawings corresponds to the power supply wiring structure of the semiconductor device manufactured by removing the process of arranging the MIM capacitor element without changing the contents of other processes in the manufacturing method of the semiconductor device. To do.

  According to the manufacturing method of the semiconductor device excluding the step of arranging the MIM capacitor element, the power supply wiring structure has the first wiring 21 and the second wiring 22 (not shown) formed as shown in FIG. Thereafter, the process proceeds to, for example, the step shown in FIG. That is, an insulating film (MIM upper insulating film 36) is formed on the first wiring 21 and the second wiring 22 (not shown). At this time, the MIM capacitor shown in FIG. 9D is not formed. Thereafter, the process proceeds to the step shown in FIG. That is, a via hole and grooves for forming the upper third wiring 51 and the fourth wiring 52 are formed by a normal dual damascene process. As shown in FIG. 9E, the via hole formed in this process has an upper electrode 32, a lower electrode 34, and a lower layer wiring (first wiring 21 or second wiring) of the MIM capacitive element, as shown in FIG. The via hole reaches the wiring 22). However, when there is no MIM capacitor, the via hole reaches the lower layer wiring (the first wiring 21 or the second wiring 22). That is, when the MIM capacitive element is present, the via hole formed so as to reach the upper electrode 32 and the lower electrode 34 of the MIM capacitive element has a lower wiring (first wiring 21) when the MIM capacitive element is not present. Alternatively, the via hole reaches the second wiring 22). As described above, except for the step of arranging the MIM capacitor element, the first via 42b, the second via 41b, which connected the third wiring 51 or the fourth wiring 52 and the upper electrode 32 or the lower electrode 34, The third via 41 a and the fourth via 42 a are vias that connect the third wiring 51 or the fourth wiring 52 and the first wiring 21 or the second wiring 22. In such a case, depending on the connection relationship, a disadvantage in performance may occur in the manufactured semiconductor device.

  However, all of the first via 42b, the second via 41b, the third via 41a, and the fourth via 42a of the present embodiment are all in the first region 81 (the region where the first wiring 21 and the third wiring 51 overlap in plan view) or It arrange | positions so that it may overlap with the 2nd area | region 82 (area | region where the 2nd wiring 22 and the 4th wiring 52 overlap in planar view) planarly. Therefore, the first via 42b, the second via 41b, the third via 41a, and the fourth via 42a are all vias that connect the first wiring 21 and the third wiring 51 when the MIM capacitance element is not present, or The vias connect the second wiring 22 and the fourth wiring 52. In the present embodiment, the first wiring 21 and the third wiring 51 are designed to have the same potential, and the second wiring 22 and the fourth wiring 52 are designed to have the same potential. Therefore, the first via 42b, the second via 41b, the third via 41a, and the fourth via 42a connect the first wiring 21 and the third wiring 51 or the second wiring 22 and the fourth wiring 52. Even if the via is made, there is no inconvenience in performance in the manufactured semiconductor device. As described above, according to the design method of the power supply wiring structure of the present embodiment, the manufactured semiconductor device has inconvenience in performance even if the step of arranging the MIM capacitor element is omitted without changing the contents of other steps. It does not occur. In this way, if the MIM capacitive element forming process incorporated in advance in the design stage can be skipped, the total number of processes can be reduced and the chip manufacturing cost can be reduced.

  Further, according to the method of manufacturing a semiconductor device using the design method of the power supply wiring structure of the present embodiment, the additional lithography process for forming the MIM capacitor element includes “patterning of the upper electrode 32” and “of the lower electrode 34”. "Pattern", and if necessary, "Mark pattern is formed in the MIM lower insulating film 35 to facilitate alignment between the upper electrode 32 and the lower layer wiring 21 or 22". Capacitance can be formed. Note that, in the design method of the power supply wiring structure of the present embodiment, the third wiring is formed using the via connecting the first wiring 21 and the third wiring 51 and the via connecting the second wiring 22 and the fourth wiring 52. 51 and the fourth wiring 52 and the MIM capacitor element are connected, it is not necessary to newly provide a step of forming a via for connecting the wiring and the MIM capacitor element.

  On the other hand, in the case of the technique described in Patent Document 1, for example, in this structure, the upper two wirings are dedicated to the power source, and in order to generate these, (1) the lower circuit and (n-1) layer 4 of the via connecting the second wiring layer, (2) the (n-1) th wiring layer, (3) the via connecting the lower layer circuit and the nth wiring, and (4) the nth wiring layer. It is necessary to perform the photolithography process once.

  Thus, according to the manufacturing method of the semiconductor device using the design method of the power supply wiring structure of the present embodiment, it is possible to improve the manufacturing efficiency and to suppress the manufacturing cost.

  Here, the shapes of the upper electrodes 32a and 32b and the lower electrodes 34a and 34b of the MIM capacitor element shown in FIG. 2 are merely examples, and other shapes may be employed.

  For example, a shape as shown in FIG. In the case of this configuration, the lower MIM capacitive element in the figure corresponds to the first MIM capacitive element, and the upper MIM capacitive element in the figure corresponds to the second MIM capacitive element.

  That is, the lower first MIM capacitive element in the figure is arranged such that the first lower electrode 34b overlaps at least one first region 81 and at least one second region 82 in plan view, The electrode 32b does not overlap with at least one region where the first region 81 and the first lower electrode 34b overlap in a plan view, and at least one region where the second region 82 and the first lower electrode 34b overlap in a plan view. Are arranged so as to overlap.

  The second MIM capacitive element on the upper side in the drawing is arranged such that the second lower electrode 34a overlaps at least one first region 81 and at least one second region 82 in plan view, and the second upper electrode 32a does not overlap at least one region where the second region 82 and the second lower electrode 34a overlap in plan view, and at least one region where the first region 81 and the second lower electrode 34a overlap in plan view Are arranged to overlap.

  In addition, for example, a shape as shown in FIG. In the case of this configuration, the lower MIM capacitive element in the figure corresponds to the first MIM capacitive element, and the upper MIM capacitive element in the figure corresponds to the second MIM capacitive element.

  In addition, regarding the shapes and arrangement methods of the first wiring 21, the second wiring 22, the third wiring 51, and the fourth wiring 52, a first region 81 that is a region where the first wiring 21 and the third wiring 51 overlap in plan view. As long as it forms the second region 82 where the second wiring 22 and the fourth wiring 52 overlap in a plan view, there is no particular limitation, and the present invention is not limited to that shown in FIG. For example, the first wiring 21 and the second wiring 22 do not have to be arranged alternately. Further, the third wiring 51 and the fourth wiring 52 may not be alternately arranged.

However, as shown in FIG. 2, “the first wiring 21 and the second wiring 22 are formed in a straight line, and are arranged in parallel and alternately with each other. The third wiring 51 and the fourth wiring 52 are formed in a straight line. The first wiring 21 and the second wiring 22, and the third wiring 51 and the fourth wiring 52 are arranged so as to be orthogonal to each other in plan view. This is desirable because the first region 81 and the second region 82 can be formed efficiently.
<Embodiment 2>

  Next, another example of a semiconductor device manufacturing method using the power supply wiring structure design method described in the first embodiment will be described. In the method of manufacturing a semiconductor device according to the present embodiment, a Si substrate, a CMOS transistor formed on the Si substrate, a contact plug, and a multi-layer wiring having an arbitrary number of layers positioned below or above the two-layer wiring After forming the layers and the like, a power supply wiring structure is formed thereon. The configuration other than the power supply wiring structure can be realized in accordance with the prior art, and thus the description thereof is omitted here. Hereinafter, an example of a method for manufacturing the power supply wiring structure of the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 12A, the first wiring 21 and the second wiring 22 (not shown) for supplying the power supply potential VDD or the ground potential GND are formed in the same layer. If the first wiring 21 is a VDD wiring, the second wiring 22 is a GND wiring, and if the first wiring 21 is a GND wiring, the second wiring 22 is a VDD wiring. The first wiring 21 and the second wiring 22 are formed to be parallel to each other in a planar layout.

  The first wiring 21 and the second wiring 22 are grooves in which a desired wiring pattern is transferred in a first insulating film containing at least two elements of Si, O, C, H, and N. After the metal film is embedded, the excess metal film is removed by polishing. Here, the metal film may be made of a conductive adhesion film that secures adhesion to the first insulating film, a conductive barrier film that suppresses mutual diffusion of elements, and a main wiring metal. The conductive adhesion film and the conductive barrier film are selected from refractory metals such as Ta and Ti, or nitrides thereof, and are formed by a technique such as PVD or CVD. The main wiring metal is formed by a method such as a PVD method, a CVD method, or a plating method using copper or an alloy material containing 95% or more of copper. After the first wiring 21 and the second wiring 22 are formed, an insulating barrier layer that prevents the wiring material from being oxidized and suppresses the diffusion of elements constituting the wiring material is formed over the entire surface (not shown). ), Protect the surface. As this insulating barrier layer, a film containing Si and an element selected from one or more of O, C, H, and N, preferably a film containing Si and N, is used.

  Next, as shown in FIG. 12B, the MIM lower insulating film 35, the conductive film 34A that becomes the lower electrode 34 of the MIM capacitor, the insulating film 33A that becomes the capacitor insulating film 33 of the MIM capacitor, and the MIM capacitor A conductive film 32A serving as the upper electrode 32 and an etch stopper layer 31 functioning as an etching stop layer during via etching are sequentially stacked.

  Here, as the MIM lower insulating film 35, a film containing at least two elements of Si, O, C, H, and N is used. The conductive film 34A to be the lower electrode 34 may be a refractory metal such as Ti or Ta, a nitride of these metals, or a stacked structure of a plurality of conductive films, and is formed by a method such as PVD or CVD.

  The material and film thickness of the capacitive insulating film 33 are important factors that determine the characteristics of the capacitance. In order to realize a high capacity, it is preferable to use a SiN film having a film thickness of 8 to 25 nm. Alternatively, when a metal oxide such as Ta, Ti, Zr, Hf, or La is used, high reliability can be secured by increasing the physical film thickness by utilizing the high dielectric constant. The insulating film 33A to be the capacitor insulating film 33 is obtained by a CVD method or by oxidizing a metal film formed by the PVD method. Examples of the oxidation treatment include a method of performing heat treatment in an oxygen-containing atmosphere at a temperature range of 250 to 350 ° C., and a method of generating plasma in a similar atmosphere to promote oxidation. The conductive film 32A to be the upper electrode 32 may be a refractory metal such as Ti or Ta, a nitride of these metals, or a laminated structure of a plurality of conductive films, and is formed by a technique such as PVD or CVD. . For the etch stopper layer 31, a film containing Si and an element selected from one or more of O, C, H, and N, preferably a film containing Si and N, is used.

  Subsequently, as shown in FIG. 12C, the conductive film 32A to be the upper electrode 32 is patterned by a lithography process dedicated to MIM. At this time, a mark pattern may be formed in the MIM lower insulating film 35 in order to facilitate alignment between the upper electrode 32 and the lower layer wiring 21 or 22. In that case, a lithography process for forming a mark pattern is also required. For patterning the conductive film 32A to be the upper electrode 32, the etch stopper layer 31 and the conductive film 32A are simultaneously etched by a dry etching method. At this time, the etching is stopped on the insulating film 33A to be the capacitive insulating film 33 by utilizing the etching selectivity of the conductive film 32A and the insulating film 33A to be the capacitive insulating film 33.

  Next, as shown in FIG. 12D, the conductive film 34A to be the lower electrode 34 is patterned by another lithography process dedicated to MIM. In the patterning of the conductive film 34A to be the lower electrode 34, the insulating film 33A to be the capacitive insulating film 33 and the conductive film 34A are simultaneously etched by a dry etching method. At this time, the etching is stopped on the lower MIM insulating film 35 using the etching selectivity between the conductive film 34A and the lower MIM insulating film 35.

  Subsequently, as shown in FIG. 13E, an MIM upper insulating film 37 is formed. The MIM upper insulating film 37 has unevenness caused on the surface due to the MIM capacitor element. The unevenness may be transferred to the next step as it is, or may be transferred to the next step after being flattened by polishing by the CMP method.

  Next, as shown in FIG. 13F, via holes reaching the upper electrode 32, the lower electrode 34, and the lower wiring layer 21 or 22 are formed by a photolithography process and a dry etching process. Subsequently, as shown in FIG. 13G, a conductive film 70 to be the upper wiring layer 71 or 72 is formed using a PVD method, a CVD method, or the like. The conductive film 70 is composed of a stack of refractory metals such as Ti and Ta, a metal film containing 95% or more of nitrides of these refractory metals and Al. Here, the portion connected to the upper electrode 32 or the lower electrode 34 in the lower layer of the via hole becomes the electrode via 61, and the portion connected to the lower wiring (the first wiring 21 or the second wiring 22) becomes the wiring via 63. . Finally, as shown in FIG. 13H, an upper wiring pattern is formed by a photolithography process and a dry etching process. That is, the third wiring 71 having the same potential as the first wiring 21 and the fourth wiring 72 having the same potential as the second wiring 22 are formed. It should be noted that the first wiring 21 having the same potential is always located immediately below the via connected to the third wiring 71. In addition, the second wiring 22 having the same potential is always located immediately below the via connected to the fourth wiring 72.

  Also in the manufacturing method of the semiconductor device of the present embodiment, the same excellent effect as that of the manufacturing method of the semiconductor device described in the first embodiment can be realized. In addition, at present, in LSI chips, it is common to form bonding pads or the like with wiring mainly composed of Al as the uppermost layer, but by providing power wiring on the pad layer, efficient power wiring is provided. It becomes possible. Furthermore, since the thickness of this aluminum pad is generally formed sufficiently thicker than the thickness of the underlying copper wiring, the semiconductor device manufactured by the semiconductor device manufacturing method of this embodiment has a low resistance. Therefore, according to such a semiconductor device, static power supply fluctuation can be effectively suppressed.

11 transistor layer 12 via 13 multilayer wiring layer 21 first wiring 22 second wiring 31 etch stopper layer 32 upper electrode 32A conductive film 32a second upper electrode 32b first upper electrode 33 capacitive insulating film 33A insulating film 34 lower electrode 34A conductive film 34a Second lower electrode 34b First lower electrode 35 MIM lower insulating film 36 MIM upper insulating film 37 MIM upper insulating film 41a 3rd via 41b 2nd via 42a 4th via 42b 1st via 43 via 44 44 via 51 3rd wiring 52 Fourth wiring 61 Electrode via 63 Wiring via 70 Conductive film 71 Third wiring 72 Fourth wiring 81 First region 82 Second region

Claims (17)

A method for designing a power supply wiring structure provided in a layer above a circuit formed on a substrate,
A first wiring and a second wiring for supplying different potentials are disposed in the first layer above the circuit;
One or more MIM capacitive elements in which a lower electrode, a capacitive insulating film, and an upper electrode are laminated in this order are disposed in a second layer above the first layer,
A third wiring having the same potential as the first wiring and a fourth wiring having the same potential as the second wiring are arranged in a third layer above the second layer;
A region where the first wiring and the third wiring overlap in a plan view is a first region, and a region where the second wiring and the fourth wiring overlap in a plan view is a second region,
The first lower electrode of the first MIM capacitor element is disposed so as to overlap with at least one first region and at least one second region in plan view,
The first upper electrode of the first MIM capacitor element does not overlap at least one region where the first region and the first lower electrode overlap in a plan view, and the second region and the first region in a plan view The first lower electrode is disposed so as to overlap with at least one region overlapping,
A first via for connecting the first upper electrode and the fourth wiring is disposed to overlap the second region in plan view;
A method of designing a power supply wiring structure in which a second via for connecting the first lower electrode and the third wiring is arranged to overlap the first region in plan view. In the design method of the power supply wiring structure according to claim 1,
The number of the MIM capacitor elements required for power supply stabilization is calculated based on the actual operation of the circuit, and the first via and the at least one of the calculated number of the MIM capacitor elements are connected to the circuit. A method for designing a power supply wiring structure for changing the layout of the second via. In the design method of the power supply wiring structure according to claim 1,
When the number of the MIM capacitor elements required for power supply stability determined based on the actual operation of the circuit is 0, the process of arranging the MIM capacitor elements without changing the contents of other processes is excluded. Design method for power supply wiring structure. A first wiring and a second wiring for supplying different potentials in the first layer above the circuit formed on the substrate;
One or more MIM capacitive elements in which a lower electrode, a capacitive insulating film, and an upper electrode are stacked in this order, provided in one or more second layers above the first layer;
A third wiring having the same potential as the first wiring, and a fourth wiring having the same potential as the second wiring, provided in a third layer above the second layer;
A first via connecting the upper electrode and the fourth wiring; and a second via connecting the lower electrode and the third wiring;
Have
A region where the first wiring and the third wiring overlap in a plan view is a first region, and a region where the second wiring and the fourth wiring overlap in a plan view is a second region,
The first lower electrode of the first MIM capacitor element is disposed so as to overlap with at least one first region and at least one second region in plan view,
The first upper electrode of the first MIM capacitor element does not overlap at least one region where the first region and the first lower electrode overlap in a plan view, and the second region and the first region in a plan view The first lower electrode is disposed so as to overlap with at least one region overlapping,
The first via is arranged to overlap the second region in plan view,
The semiconductor device having a power supply wiring structure in which the second via is disposed so as to overlap the first region in plan view. 5. The semiconductor device according to claim 4, further comprising:
A third via that connects the upper electrode and the third wiring; and a fourth via that connects the lower electrode and the fourth wiring;
The second lower electrode of the second MIM capacitor element is disposed so as to overlap with at least one first region and at least one second region in plan view,
The second upper electrode of the second MIM capacitor element does not overlap at least one region where the second region and the second lower electrode overlap in plan view, and the first region and the second region in plan view. The second lower electrode is disposed so as to overlap with at least one region overlapping,
The third via is disposed so as to overlap the first region in plan view,
The semiconductor device is arranged such that the fourth via overlaps with the second region in plan view. The semiconductor device according to claim 5,
The semiconductor device in which the first MIM capacitive element and the second MIM capacitive element are disposed adjacent to each other. In the semiconductor device according to any one of claims 4 to 6,
The semiconductor device in which the first wiring and the second wiring are arranged in parallel to each other. The semiconductor device according to any one of claims 4 to 7,
The semiconductor device in which the third wiring and the fourth wiring are arranged in parallel to each other. The semiconductor device according to any one of claims 4 to 8,
The first wiring and the second wiring are arranged in parallel to each other,
The third wiring and the fourth wiring are arranged in parallel to each other, and the first wiring and the second wiring, and the third wiring and the fourth wiring are arranged to be orthogonal to each other in plan view. Semiconductor device. The semiconductor device according to any one of claims 4 to 9,
The semiconductor device, wherein the first wiring and the third wiring are wirings for supplying a power supply potential, and the second wiring and the fourth wiring are wirings for supplying a ground potential. The semiconductor device according to any one of claims 4 to 9,
The semiconductor device, wherein the first wiring and the third wiring are wirings for supplying a ground potential, and the second wiring and the fourth wiring are wirings for supplying a power supply potential. The semiconductor device according to any one of claims 4 to 11,
The first wiring and the second wiring are semiconductor devices made of a metal containing 95% or more of Cu. The semiconductor device according to claim 12,
The third wiring and the fourth wiring are semiconductor devices made of a metal containing 95% or more of Cu. The semiconductor device according to claim 12,
The third wiring and the fourth wiring are semiconductor devices composed of a metal containing 95% or more of Al. The semiconductor device according to any one of claims 4 to 14,
The semiconductor device, wherein the capacitive insulating film of the MIM capacitive element is a silicon nitride film having a thickness of 8 nm to 25 nm. The semiconductor device according to any one of claims 4 to 15,
A semiconductor device in which one or more of the MIM capacitance elements that are not connected to the third wiring and the fourth wiring exist.   A method for manufacturing a semiconductor device using the method for designing a power supply wiring structure according to claim 1.

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