JPWO2009069175A1 - Plasma display device - Google Patents

Abstract

The plasma display device includes a plasma display panel (PDP) having a first substrate and a second substrate facing each other through a discharge space, and a drive unit that drives the PDP. On the first substrate, there are provided three electrodes which are a pair of first and second electrodes and an address electrode. The address electrode is located in a region facing the discharge space through each cell, and extends in a direction crossing the direction in which the first electrode extends. The driving unit applies a waveform voltage that rises from the first voltage to the second voltage with the lapse of time in the reset period, and applies a third voltage equal to or lower than the first voltage to the address electrode. And a drive circuit that applies a fourth voltage lower than the second voltage and higher than the third voltage to the first electrode. As a result, the luminance at the time of reproducing black can be lowered, and the image quality can be improved.

Description

  The present invention relates to a plasma display device.

  A plasma display panel (PDP) is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

  The PDP having a three-electrode structure displays an image by generating a sustain discharge between the X electrode and the Y electrode during the sustain period. A cell that generates a sustain discharge (cell to be lit) is selected by, for example, selectively generating an address discharge between the Y electrode and the address electrode in the address period. Further, before the address period, there is a reset period for accumulating wall charges for generating an address discharge.

In a general PDP, an X electrode and a Y electrode are arranged on a front glass substrate, and an address electrode is arranged on a rear glass substrate. In recent years, a PDP in which three electrodes, that is, an X electrode, a Y electrode, and an address electrode are arranged on a front glass substrate has been proposed (see, for example, Patent Document 1).
JP-A-2005-116508

  In a general PDP, a weak discharge is generated between the X electrode and the Y electrode during the above-described reset period, and wall charges are accumulated. Due to this weak discharge, visible light is generated during the reset period, and the luminance (black luminance) at the time of reproducing black increases, and the quality of the image decreases. In addition, as the black luminance is lower, the tightened black can be reproduced, and the quality of the image is improved.

  An object of the present invention is to reduce the luminance (black luminance) when reproducing black in a PDP device having a PDP in which three electrodes are provided on a front glass substrate, thereby improving the image quality.

  The plasma display device includes a plasma display panel (PDP) and a drive unit that drives the PDP. The PDP has a first substrate and a second substrate that face each other through a discharge space. A first substrate and a second electrode, a first dielectric layer, a plurality of address electrodes, and a protective layer, which are paired with each other, are sequentially stacked on the first substrate. For example, the first electrode includes a first bus electrode extending in the first direction and a first display electrode connected to the first bus electrode, and the second electrode extends in the first direction. 2 bus electrodes and a first display electrode connected to the second bus electrode. On the second substrate, a plurality of partition walls extending in a second direction intersecting with the first direction and arranged at intervals are provided. A cell is formed in a region surrounded by the first and second bus electrodes and the partition. The address electrode extends in the second direction through each cell and is disposed along the partition wall. The drive unit includes a first drive circuit, a second drive circuit, and a third drive circuit. For example, the second drive circuit applies a waveform voltage that rises from the first voltage to the second voltage with the passage of time to the second electrode during the reset period. The third drive circuit applies a third voltage equal to or lower than the first voltage to the address electrode when the waveform voltage is applied to the second electrode. The first drive circuit applies a fourth voltage lower than the second voltage and higher than the third voltage to the first electrode when the waveform voltage is applied to the second electrode.

  In the present invention, in a PDP device having a PDP in which three electrodes are provided on a front glass substrate, the luminance (black luminance) when reproducing black can be lowered, and the quality of an image can be improved.

It is a figure which shows the PDP apparatus in one Embodiment. It is a figure which shows the principal part of PDP shown in FIG. It is a figure which shows the outline | summary of PDP shown in FIG. It is a figure which shows the cross section which follows the A-A 'line | wire of PDP shown in FIG. It is a figure which shows the structural example of the field for displaying the image of 1 screen. It is a figure which shows an example of the discharge operation | movement of the subfield shown in FIG. It is a figure which shows the outline | summary of the circuit part shown in FIG. It is a figure which shows the modification of PDP shown in FIG. It is a figure which shows the modification of the electrode structure shown in FIG. It is a figure which shows the modification of the discharge operation | movement shown in FIG. It is a figure which shows another modification of the discharge operation | movement shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. A plasma display device (hereinafter also referred to as a PDP device) includes a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, A front housing 30 disposed on the image display surface 16 side of the PDP 10, a rear housing 40 and a base chassis 50 disposed on the back surface 18 side of the PDP 10, and attached to the rear housing 40 side of the base chassis 50 to drive the PDP 10. A double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure.

  The PDP 10 includes a front substrate portion 12 that constitutes the image display surface 16 and a rear substrate portion 14 that faces the front substrate portion 12. A discharge space (cell) (not shown) is formed between the front substrate portion 12 and the rear substrate portion 14. The front substrate unit 12 and the back substrate unit 14 are formed of, for example, a glass substrate. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

  FIG. 2 shows details of a main part of the PDP 10 shown in FIG. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. As described above, the discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, the concave portion of the rear substrate portion 14).

  The front substrate portion 12 is formed in parallel along the first direction D1 on the glass substrate FS (first substrate) (lower side in the figure), and is alternately formed along the second direction D2. Xb (first bus electrode) and Y bus electrode Yb (second bus electrode) are provided. An X transparent electrode Xt (first display electrode) extending in the second direction D2 from the X bus electrode Xb to the Y bus electrode Yb is connected to the X bus electrode Xb. A Y transparent electrode Yt (second display electrode) extending in the second direction D2 from the Y bus electrode Yb to the X bus electrode Xb is connected to the Y bus electrode Yb. In the illustrated example, the X transparent electrode Xt and the Y transparent electrode Yt face each other along the second direction D2.

  Here, the X bus electrode Xb and the Y bus electrode Yb are opaque electrodes formed of a metal material or the like, and the X transparent electrode Xt and the Y transparent electrode Yt transmit visible light formed of an ITO film or the like. It is a transparent electrode. The X electrode XE (first electrode, sustain electrode) is composed of the X bus electrode Xb and the X transparent electrode Xt, and the Y electrode YE (second electrode, scan electrode) is the Y bus electrode Yb and the Y transparent electrode Yt. And is paired with the X electrode XE. A discharge (sustain discharge) is repeatedly generated at the electrode pair (more specifically, between the X transparent electrode Xt and the Y transparent electrode Yt) constituted by the X electrode XE and the Y electrode YE.

  Further, the transparent electrodes Xt and Yt may be disposed on the entire surface between the bus electrodes Xb and Yb to which the transparent electrodes Xt and Yt are connected and the glass substrate FS. It should be noted that electrodes (for example, first and second display electrodes) integral with the bus electrodes Xb and Yb may be formed instead of the transparent electrodes Xt and Yt with the same material (metal material or the like) as the bus electrodes Xb and Yb. Good.

  The electrodes Xb, Xt, Yb, Yt are covered with a dielectric layer DL1 (first dielectric layer). For example, the dielectric layer DL1 is an insulating film such as a silicon dioxide film formed by a CVD method. A plurality of address electrodes AE extending in a direction orthogonal to the bus electrodes Xb and Yb (second direction D2) are provided on the dielectric layer DL1 (lower side in the drawing). The address electrode AE is an opaque electrode formed of a metal material or the like, and is formed of, for example, a three-layer film in which chromium, copper, and chromium are stacked in this order, and is blackened. The address electrode AE may be formed of a metal material containing aluminum or silver. Thus, the PDP of this embodiment has three electrodes (electrodes XE, YE, AE) on the front substrate portion 12.

  The address electrode AE and the dielectric layer DL1 are covered with the protective layer PL, and the protective layer PL is exposed to the discharge space DS. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collisions in order to facilitate discharge.

  The back substrate portion 14 facing the front substrate portion 12 through the discharge space DS has partition walls (barrier ribs) BR formed in parallel to each other on the glass substrate RS (second substrate). For example, the barrier ribs BR extend in a direction (second direction D2) orthogonal to the bus electrodes Xb and Yb, and are arranged along the address electrodes AE. In other words, the address electrode AE extends in the second direction D2 and is disposed along the partition wall BR. A partition wall BR constitutes a side wall of the cell. Further, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall BR and the glass substrate RS between the adjacent partition walls BR by being excited by ultraviolet rays. Phosphors PHr, PHg, and PHb are respectively applied.

  One pixel of the PDP 10 includes three cells that generate red, green, and blue light. Here, one cell (one color pixel) is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR1 as shown in FIG. 3 described later. As described above, the PDP 10 is configured by arranging cells in a matrix to display an image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes Xb and Yb.

  The PDP 10 is configured by bonding the front substrate portion 12 and the rear substrate portion 14 so that the protective layer PL and the partition wall BR are in contact with each other, and enclosing a discharge gas such as Ne or Xe in the discharge space DS.

  FIG. 3 shows an outline of the PDP 10 shown in FIG. FIG. 3 shows the state of the electrodes Xb, Xt, Yb, Yt, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 2). The meanings of the arrows in the figure are the same as those in FIG. As described above, the cell C1 is formed in a region (region surrounded by a broken line in the drawing) surrounded by the bus electrodes Xb and Yb that make a pair with each other and the pair of adjacent barrier ribs BR. That is, when viewed from the image display surface side, the discharge space DS of each cell C1 is formed between the adjacent barrier ribs BR. Further, the display line DSL is configured by the cells C1 formed along the bus electrodes Xb and Yb.

  Each address electrode AE extends in the second direction D2 through the cell C1 corresponding to the address electrode AE, and is formed on one of the barrier ribs BR (left side in the drawing) forming the discharge space DS of the cell C1. Are arranged along. Note that the address electrode AE may be provided at a position where a part of the address electrode AE overlaps the partition wall BR when viewed from the image display surface side. In this case, when the front substrate portion 12 and the rear substrate portion 14 are bonded together, it is not necessary to make the alignment highly accurate, and therefore the bonding of the front substrate portion 12 and the rear substrate portion 14 can be simplified.

  The transparent electrode Xt is disposed in each cell C1 and protrudes from the bus electrode Xb toward the bus electrode Yb. The transparent electrode Yt is disposed in each cell C1, protrudes from the bus electrode Yb toward the bus electrode Xb, and the tip is located on the bus electrode Xb side from the tip of the transparent electrode Xt. In other words, in this embodiment, the transparent electrode Yt has a portion facing the transparent electrode Xt along the second direction D2. Thereby, in the sustain period SUS of FIG. 6 to be described later, a sustain discharge can be generated in the discharge space DS of the cell C1 of interest by applying a voltage between the transparent electrode Xt and the transparent electrode Yt.

  Further, when viewed from the image display surface side, the address electrode AE and the transparent electrodes Yt and Xt corresponding to the cell C1 are arranged in order from the left side along the first direction D1, and the address electrode AE includes the transparent electrode Yt. Are provided along the second direction D2. Accordingly, address discharge can be generated in the discharge space DS of the cell C1 of interest by applying a voltage between the address electrode AE and the transparent electrode Yt in the address period ADR of FIG. 6 described later. The transparent electrode Yt may be provided at a position where part of the transparent electrode Yt overlaps the address electrode AE when viewed from the image display surface side.

  Further, in two adjacent cells C1 arranged in the first direction D1, the distance between the address electrode AE of one cell C1 and the transparent electrode Yt of the other cell C1 is the same as the address electrode AE of one cell C1. It is longer than the distance from the transparent electrode Yt of one cell C1. Therefore, when an address discharge is generated between the address electrode AE and the transparent electrode Yt of one cell C1 (address period), an erroneous discharge is generated between the address electrode AE of one cell C1 and the transparent electrode Yt of the other cell C1. Can be prevented.

  FIG. 4 shows a cross section of the PDP 10 along the line A-A ′ of FIG. 3. The meanings of the arrows in the figure are the same as those in FIG. As described above, the address electrode AE and the transparent electrode Yt are disposed adjacent to each other in the cell C1 (on the discharge space DS of the cell C1). Therefore, an electric field E1 between the address electrode AE and the scan electrode YE is generated in the discharge space DS by applying a voltage between the address electrode AE and the scan electrode YE (transparent electrode Yt and bus electrode Yb).

  In the example of the figure, an electric field E1 generated when a voltage at which the address electrode AE becomes a cathode with respect to the transparent electrode Yt is applied between the address electrode AE and the transparent electrode Yt is shown. For example, an electric field E1 is generated between the address electrode AE and the transparent electrode Yt in a period T1 of a reset period RST in FIG. In this case, the address electrode AE serves as a cathode, the transparent electrode Yt serves as an anode, and a weak discharge (reset discharge) occurs between the address electrode AE and the transparent electrode Yt. Visible light VL is generated by this weak discharge. For example, ultraviolet light and visible light VL are generated from the discharge gas by weak discharge, and further excited by the ultraviolet light, and visible light of red (R), green (G), and blue (B) from the phosphors PHr, PHg, and PHb. Each VL occurs. Note that the visible light VL generated in the reset period RST is visible light that is unnecessary for displaying an image (originally unnecessary visible light).

  Since secondary electrons are emitted from the cathode-side protective layer PL (protective layer PL on the address electrode AE (lower side in the figure)) on which the positive ions collide, strong discharge occurs on the cathode side (address electrode AE side). To do. Therefore, the visible light VL generated by the discharge becomes stronger on the cathode side (address electrode AE side). In this embodiment, as described above, since the address electrode AE is made of a metal material that is opaque to visible light, most of the visible light VL from the discharge space DS toward the glass substrate FS side is addressed. Light is shielded by the electrode AE.

  Thereby, in this embodiment, for example, in the period T1 of the reset period RST in FIG. 6 to be described later, the luminance of the originally unnecessary visible light VL reaching from the discharge space DS to the glass substrate FS side can be reduced, and black is reproduced. The luminance (black luminance) at the time of performing can be lowered. As a result, the image quality can be improved. In particular, when the address electrode AE is blackened, since the visible light transmittance is low, the luminance of the originally unnecessary visible light VL that reaches the glass substrate FS side from the discharge space DS is lowered during the reset period RST. it can.

  FIG. 5 shows a configuration example of the field FLD for displaying an image of one screen. The length of one field FLD is 1/60 second (about 16.7 ms), and is composed of, for example, eight subfields SF (SF1-SF8). Each subfield SF includes a reset period RST, an address period ADR, a sustain period SUS, and an erase period ERS. Note that the erase period ERS is defined as being included in the sustain period SUS because it is a period for generating a discharge for reducing the wall charge of only the lit cells. Here, the wall charges are, for example, plus charges and minus charges accumulated on the surface of the protective layer PL such as MgO shown in FIG. 2 in each cell.

  For example, in the reset period RST, the amounts of wall charges accumulated in the electrodes XE, YE, and AE are adjusted in order to match the discharge start voltages (voltages at which address discharge in the address period ADR starts to occur) of all cells. It is a period. The address period ADR is a period for selecting a cell to be lit during the sustain period SUS. A cell to be lit in the sustain period SUS is selected by, for example, selectively generating an address discharge between the scan electrode YE and the address electrode AE in the address period as shown in FIG. The sustain period SUS is a period in which discharge is generated in the cell selected in the address period ADR.

  The length of the sustain period SUS depends on the subfield SF and depends on the number of discharges (luminance) of the cell. For this reason, it becomes possible to display an image with multiple gradations by changing the combination of the subfields SF to be lit. In this example, the number of sustain discharges preset in the subfield SF1-8 is 4, 8, 16, 32, 64, 128, 256, and 512, respectively. As shown in FIG. 6 to be described later, the cell is discharged twice during one discharge cycle CYC (star in the figure).

  FIG. 6 shows an example of the discharge operation of the subfield SF shown in FIG. The star in the figure indicates the occurrence of discharge. Further, a waveform indicated by a thick broken line in the address period ADR in the figure indicates a voltage superimposed by wall charges. Note that the voltage superimposed by the wall charges is not shown in the period other than the address period ADR.

  First, in the reset period RST, the positive voltage Vrx (fourth voltage) is applied to the sustain electrode XE (the bus electrode Xb and the transparent electrode Xt), and the voltage Vry1 (first voltage) higher than the voltage Vrx is applied to the scan electrode YE. Applied to (bus electrode Yb and transparent electrode Yt) (FIG. 6A). At this time, a voltage Vra (third voltage) lower than the voltage Vry1 and lower than the voltage Vrx, for example, the voltage (0 V) of the ground line GND is applied to the address electrode AE (FIG. 6A).

  Then, a write waveform voltage (write blunt wave) that gradually increases from the voltage Vry1 to the voltage Vry2 (second voltage) with the passage of time is applied to the scan electrode YE (FIG. 6B). Further, in the period T1 in which the write waveform voltage (write blunt wave) is applied to the scan electrode YE, the sustain electrode XE is maintained at the positive voltage Vrx, and the address electrode AE is maintained at the voltage Vra (FIG. 6). (B)). That is, in this embodiment, the voltage Vra (third voltage) equal to or lower than the voltage Vry1 (first voltage) is applied to the address electrode AE in the period T1, is lower than the voltage Vry1 (first voltage), and is equal to the voltage Vra ( A voltage Vrx (fourth voltage) higher than the third voltage) is applied to the sustain electrode XE.

  As a result, a weak discharge (reset discharge) is generated between the scan electrode YE and the address electrode AE, and negative and positive wall charges are accumulated in the scan electrode YE and the address electrode AE, respectively. Since voltage Vrx higher than voltage Vra is applied to sustain electrode XE, no discharge occurs between sustain electrode XE and scan electrode YE. That is, the voltage Vrx is lower than the lowest voltage (discharge start voltage) at which the voltage between the scan electrode YE and the sustain electrode XE (difference between the voltage Vry2 and the voltage Vrx) causes discharge between the scan electrode YE and the sustain electrode XE. Is set as follows. Further, since voltage Vrx lower than voltage Vry2 (and voltage Vry1) is applied to sustain electrode XE, sustain electrode XE becomes a cathode with respect to scan electrode YE, and positive wall charges are accumulated in sustain electrode XE. Note that the amount of wall charges accumulated in the address electrodes AE is different from the voltage applied to the sustain electrodes XE and the address electrodes AE (the voltage Vrx and the voltage Vra) compared to the amount of wall charges accumulated in the sustain electrodes XE. The difference is equivalent to

  For example, the voltage values of the voltages Vrx, Vry1, Vry2, and Vs / 2 are 50V, 70V, 300V, and 70V, respectively. Since the voltage difference between the sustain electrode XE and the scan electrode YE (difference between the voltage Vry2 and the voltage Vrx) is larger than the voltage Vs, the amount of accumulated wall charges is relatively large. As a result, the amount of wall charge accumulated in all the cells during the period T1 is equal to the amount of wall charge necessary for address discharge, regardless of the amount of wall charge remaining in the lit and unlit cells. More than the amount. That is, the period T1 is a period in which wall charges are excessively accumulated in order to reduce the influence of the wall charges remaining in the lit cells and the cells that are not lit. For example, by reducing this excessively accumulated wall charge during the reset period RST (for example, after the period T1), the wall charges of all cells can be made equal to the amount of wall charge required for address discharge.

  Here, for example, in the period T1 of the conventional control method, when a write waveform voltage (positive voltage) is applied to the scan electrode YE, a negative write voltage is applied to the sustain electrode XE and the ground line GND is applied. A voltage (0 V) is applied to the address electrode AE. As a result, a discharge (reset discharge) is generated between sustain electrode XE and scan electrode YE, and positive and negative wall charges are accumulated in sustain electrode XE and scan electrode YE, respectively. In this case, as described above with reference to FIG. 4, a strong reset discharge is generated on the cathode side (sustain electrode XE side, more specifically, transparent electrode Xt). That is, when viewed from the image display surface side (upper side of FIG. 4) (for example, FIG. 3 described above), most of the reset discharge occurs on the back side of the transparent electrode Xt.

  For this reason, the visible light generated by the reset discharge has a stronger intensity on the cathode side (transparent electrode Xt side). That is, most of the visible light generated by the reset discharge reaches the transparent electrode Xt from the discharge space DS and does not reach the address electrode AE. Further, as described with reference to FIG. 2 described above, the transparent electrode Xt on the discharge space DS is formed of an ITO film or the like that transmits visible light. Accordingly, most of the originally unnecessary visible light generated by the discharge between the sustain electrode XE and the scan electrode YE is not shielded by the address electrode AE, and passes through the transparent electrode Xt and reaches the glass substrate FS. As a result, in the conventional control method in which the reset discharge is generated between the sustain electrode XE and the scan electrode YE in the reset period RST, the luminance (black luminance) at the time of reproducing black increases, and the image quality decreases.

  In contrast, in the period T1 of this embodiment, in order to store wall charges in the electrodes XE, YE, and AE, respectively, the scanning electrode YE and the address electrode AE are used with the address electrode AE as a cathode with respect to the scanning electrode YE. A reset discharge is generated between them. That is, in this embodiment, when viewed from the image display surface side (upper side of FIG. 4) (for example, FIG. 3 described above), most of the reset discharge can be generated on the back side of the address electrode AE. Further, in this embodiment, the address electrode AE is made of an opaque metal material and is disposed on the discharge space DS of each cell C1. For this reason, as described with reference to FIG. 4 described above, most of the originally unnecessary visible light VL generated by the reset discharge between the scan electrode YE and the address electrode AE is on the way from the discharge space DS to the glass substrate FS. It is shielded by the address electrode AE and does not reach the glass substrate FS. Therefore, in this embodiment, the luminance (black luminance) at the time of reproducing black can be lowered, and the tightened black can be reproduced, so that the quality of the image can be improved.

  After the period T1, a positive adjustment voltage is applied to the sustain electrode XE (in the example of the figure, the sustain electrode XE is maintained at the voltage Vrx), and the negative adjustment in which the voltage value decreases with time. A voltage (adjusted blunt wave) is applied to the scan electrode YE (FIG. 6C). Further, the address electrode AE is maintained in a state of being grounded to the ground line GND (FIG. 6C). As a result, the amount of wall charges accumulated in the sustain electrode XE, the scan electrode YE, and the address electrode AE is reduced, and the wall charges of all the cells are equalized. For example, the positive adjustment voltage is a voltage lower than Vs / 2, and the minimum value of the negative adjustment voltage is a voltage higher than −Vs / 2.

  In the address period ADR, an X bias voltage Vax that serves as an anode during address discharge is applied to the sustain electrode XE, a scan pulse (voltage −Vsc) that serves as a cathode during address discharge is applied to the scan electrode YE, and serves as an anode during address discharge. An address pulse (voltage Vsa) is applied to the address electrode AE corresponding to the lighted cell (FIG. 6 (d)). In this case, the voltages of the sustain electrode XE, the scan electrode YE, and the address electrode AE are the voltages Vcx, −Vcy generated by the wall charges accumulated in the reset period RST to the above-described applied voltages (voltages Vax, −Vsc, Vsa). , Vca (waveforms indicated by broken lines in the figure) are superimposed on each other.

  For example, the voltage values of the voltages Vrx, Vax, −Vsc, and Vsa are 50V, 40V, −100V, and 30V, respectively. At this time, the voltage Vsa applied to the address electrode AE is such that the voltage of the address electrode AE (addition of the voltage Vsa and the voltage Vca) is higher than the voltage of the sustain electrode XE (addition of the voltage Vax and the voltage Vcx). Is set. By setting the voltage Vsa in this way, the voltage between the scan electrode YE and the address electrode AE becomes equal to or higher than the lowest voltage (discharge start voltage) that causes discharge, and the voltage between the sustain electrode XE and the scan electrode YE is It becomes lower than the discharge start voltage. Accordingly, when address discharge is generated between the address electrode AE and the scan electrode YE of the cell selected by the scan pulse and the address pulse in the target display line, the sustain electrode XE and the scan electrode YE of the unselected cell. It is possible to prevent erroneous discharge from occurring. That is, it is possible to prevent the wall charges for the sustain discharge from being accumulated in the sustain electrodes XE and the scan electrodes YE of the cells not selected by the address pulse.

  For example, the cell selected by the scan pulse and the address pulse is temporarily discharged between the scan electrode YE and the address electrode AE, and is temporarily discharged between the sustain electrode XE and the scan electrode YE using this discharge as a trigger. . At this time, discharge other than the cell selected by the scan pulse and the address pulse does not generate the above-described trigger discharge, so that no discharge (erroneous discharge) occurs between the sustain electrode XE and the scan electrode YE. Accordingly, the wall charges for the sustain discharge are accumulated in the sustain electrode XE and the scan electrode YE of the cell selected by the scan pulse and the address pulse, and the sustain electrode XE and the scan of the cell not selected by the scan pulse and the address pulse. It is not accumulated in the electrode YE. The second address pulse shown in the waveform of the address electrode AE is applied to select cells of other display lines (FIG. 6 (e)).

  In this embodiment, more wall charges than the wall charges accumulated in the sustain electrode XE are accumulated in the address electrode AE in the reset period RST, so that the voltage Vsa applied to the address electrode AE can be lowered. Thereby, in this embodiment, an erroneous discharge can be prevented while suppressing an increase in power consumption of a drive circuit (for example, a driver ADRV shown in FIG. 7 described later) that drives the address electrode AE.

  In the sustain period SUS, negative and positive sustain pulses are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 6 (f, g)). As a result, a discharge (sustain discharge) is generated between the sustain electrode XE and the scan electrode YE of the cell selected in the address period ADR (cell to be lit), and the discharge state of the lit cell is maintained. Sustain pulses having different polarities are repeatedly applied to the sustain electrode XE and the scan electrode YE, so that the lighted cells are repeatedly discharged in the sustain period SUS.

  As described with reference to FIG. 5 described above, the discharge is performed twice during one discharge cycle CYC. For example, the subfield SF4 includes 32 discharge cycles CYC, and 64 discharges are performed. In the cells that are not lit, as described above, since the wall charges for the sustain discharge are not accumulated in the sustain electrodes XE and the scan electrodes YE, even if the sustain pulse is applied, the discharge (erroneous discharge) is Does not occur.

  In the erase period ERS, a negative pre-erase pulse and a positive high-voltage pre-erase pulse are applied to the sustain electrode XE and the scan electrode YE, respectively, and discharge is generated (FIG. 6 (h)). As a result, wall charges are accumulated in sustain electrode XE and scan electrode YE. At this time, since a voltage higher than the voltage Vs / 2 is applied to the scanning electrode YE, the amount of accumulated wall charges is relatively large. Next, a positive erase pulse and a negative erase pulse are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 6 (i)). As a result, a discharge occurs between the sustain electrode XE and the scan electrode YE. However, since the difference in voltage value applied between the two electrodes is lower than the difference in voltage value in the sustain period SUS, the amount of wall charges is reduced in the sustain period. Reduced compared to SUS.

  Note that drivers XDRV and YDRV shown in FIG. 7 to be described later apply predetermined voltages (for example, a positive adjustment voltage, a negative adjustment voltage, etc.) to the sustain electrode XE and the scan in the reset period RST, the address period ADR, and the erase period ERS. Description of a circuit for applying to the electrode Y is omitted.

  FIG. 7 shows an outline of the circuit unit 60 shown in FIG. The circuit unit 60 includes a power supply unit PWR, an X driver XDRV (first drive circuit), a Y driver YDRV (second drive circuit), an address driver ADRV (third drive circuit), and a control unit CNT. The power supply unit PWR generates power supply voltages Vry1, Vry2, -Vsc, Vs / 2, -Vs / 2, Vrx, Vax, Vsa and the like to be supplied to the drivers YDRV, XDRV, and ADRV. The drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10. For example, as shown in FIG. 6, the drivers XDRV, YDRV, and ADRV use the voltages (voltage Vrx, waveform voltage rising from the voltage Vry1 to voltage Vry2, voltage Vra, etc.) as bus electrodes Xb, Yb, address electrodes. Each is applied to AE.

  The control unit CNT selects a subfield to be used based on the image data R0-7, G0-7, B0-7, and outputs control signals YCNT, XCNT, and ACNT to the drivers YDRV, XDRV, and ADRV. A multi-tone image is displayed by selecting a subfield to be used for each cell C1 constituting the pixel. The image data R0-7, G0-7, and B0-7 are 8-bit data for displaying red, green, and blue, respectively, and sequentially from a tuner unit or an external input (not shown) to the control unit CNT. Entered.

  As described above, in this embodiment, in the reset period RST, the address electrode AE is made the cathode with respect to the scan electrode YE, and the reset discharge is generated between the address electrode AE and the scan electrode YE. For example, in this embodiment, a waveform voltage that rises from the voltage Vry1 to the voltage Vry2 is applied to the scan electrode YE in the reset period RST. At this time, a voltage Vra (voltage of the ground line GND) lower than the voltage Vry1 is applied to the address electrode AE, and a voltage Vrx lower than the voltage Vry1 and higher than the voltage Vra is applied to the sustain electrode XE. Furthermore, in this embodiment, the address electrode AE is made of a metal material that is opaque to visible light, and is disposed on the discharge space DS of each cell C1. Thereby, most of the visible light VL generated by the reset discharge is shielded by the address electrode AE on the way from the discharge space DS to the glass substrate FS and does not reach the glass substrate FS. As a result, in this embodiment, the luminance (black luminance) at the time of reproducing black can be lowered, and the tightened black can be reproduced, so that the quality of the image can be improved.

  In the above-described embodiment, an example in which one pixel is configured by three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), Cells that generate colors other than blue (B) may be included.

  In the above-described embodiment, the example in which the address electrode AE is directly covered with the protective layer PL has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 8, in the PDP 10, a second dielectric layer DL2 may be provided between the first dielectric layer DL1 and the address electrode AE and the protective layer PL. FIG. 8 shows a main part of the PDP 10 in a modification of the above-described embodiment. This PDP device has a PDP 10 configured by adding a second dielectric layer DL2 to the configuration shown in FIG. 2 described above. Other configurations are the same as those in FIGS. The same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 6 except for the voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 6). The second dielectric layer DL2 is provided on the dielectric layer DL1 and the address electrode AE (lower side in the drawing) before the protective layer PL is formed. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the transparent electrodes Xt and Yt are arranged at positions facing each other along the second direction D2 has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 9, the tip portions SD1 and SD2 of the transparent electrodes Xt2 and Yt2 may be arranged at positions facing each other along the first direction D1. FIG. 9 shows the state of the electrodes Xb, Xt2, Yb, Yt2, AE and the partition wall BR as viewed from the image display surface side. In the example of FIG. 9, the transparent electrodes Xt2 and Yt2 are different from the configuration shown in FIG. Other configurations are the same as those in FIGS. The same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The tip SD1 of the transparent electrode Xt2 connected to the bus electrode Xb faces the tip SD2 of the transparent electrode Yt2 connected to the bus electrode Yb. Further, the transparent electrodes Xt2 and Yt2 are disposed adjacent to the address electrode AE. The transparent electrodes Xt2 and Yt2 may be provided at a position where part of the transparent electrodes Xt2 and Yt2 overlaps the address electrode AE when viewed from the image display surface side. Thus, in this PDP device, the reset discharge can be generated between the address electrode AE and the scan electrode YE by using the address electrode AE as a cathode with respect to the scan electrode YE in the reset period RST. Also in this PDP device, most of the originally unnecessary visible light generated by the reset discharge can be shielded by the address electrode AE on the way from the discharge space DS to the glass substrate FS. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the reset period RST includes the period (FIG. 6A) in which the scan electrode YE is maintained at the voltage Vry1 before the period T1 has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 10, the scan electrode YE has a voltage waveform that rises from the voltage Vry1 to the voltage Vry2 in the reset period RST without the scan electrode YE being maintained at the voltage Vry1 before the period T1. It may be applied to YE.

  In the operation waveform shown in FIG. 10, the period in which the scan electrode YE is maintained at the voltage Vry1 before the period T1 is omitted from the operation waveform of FIG. Other operation waveforms are the same as those in FIG. At the beginning of the reset period RST, a positive voltage Vrx is applied to the sustain electrode XE, a voltage waveform rising from the voltage Vry1 to the voltage Vry2 is applied to the scan electrode YE, and the voltage Vra (in the example of FIG. 10, the ground line GND Voltage) is applied to the address electrode AE. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the period T1 in which the voltage Vry1 increases from the voltage Vry2 is set to the same length as the period in which wall charges are excessively accumulated has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 11, the voltage applied to the scan electrode YE to accumulate wall charges excessively rises from the voltage Vry1 to the voltage Vry2, and then reaches the voltage Vry2 only for the time T2 (period T2). May be maintained. In this case, a period in which the period T1 and the period T2 are combined is a period in which wall charges are excessively accumulated.

  The operation waveforms shown in FIG. 11 are the same as those in FIG. 6 described above except for the period T2. In the period T2, the scan electrode YE is maintained at the voltage Vry2, the sustain electrode XE is maintained at the positive voltage Vrx, and the address electrode AE is maintained at the voltage Vra (in the example of FIG. 11, the voltage of the ground line GND). Is done. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the voltage Vrx (fourth voltage) lower than the voltage Vry1 (first voltage) is applied to the sustain electrode XE in the period T1 has been described. The present invention is not limited to such an embodiment. For example, the voltage Vrx (fourth voltage) may be lower than the voltage Vry2 (second voltage) and higher than the voltage Vry1 (first voltage). Also in this case, since the voltage Vrx lower than the voltage Vry2 is applied to the sustain electrode XE, the sustain electrode XE becomes a cathode with respect to the scan electrode YE, and positive wall charges are accumulated in the sustain electrode XE. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the voltage Vrx that does not generate the discharge between the sustain electrode XE and the scan electrode YE is applied to the sustain electrode XE in the period T1 has been described. The present invention is not limited to such an embodiment. For example, the PDP 10 may include a cell in which a discharge is generated between the sustain electrode XE and the scan electrode YE in the period T1. For example, the voltage Vrx may be set to be slightly lower than the average of the discharge start voltages of the cells when the discharge start voltages between the sustain electrodes XE and the scan electrodes YE are different from one another.

  In this case, in the cell in which the voltage between the sustain electrode XE and the scan electrode YE is equal to or higher than the discharge start voltage in the period T1, discharge occurs between the sustain electrode XE and the scan electrode YE in the reset period RST. Even in this case, since the voltage Vra lower than the voltage Vrx is applied to the address electrode AE, the discharge between the scan electrode YE and the address electrode AE can be strengthened, and the discharge between the sustain electrode XE and the scan electrode YE can be weakened. Therefore, even in this case, the intensity of visible light generated by the discharge between sustain electrode XE and scan electrode YE can be reduced.

  That is, most of the originally unnecessary visible light generated in the reset period RST is visible light generated by the reset discharge between the address electrode AE and the transparent electrode Yt. Here, as described in the above-described embodiment, most of the visible light generated by the reset discharge is shielded by the address electrode AE on the way from the discharge space DS to the glass substrate FS and reaches the glass substrate FS. do not do. Therefore, also in this case, the same effect as that of the above-described embodiment can be obtained.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  The present invention can be applied to a plasma display device.

Claims (4)

A plasma display panel, and a drive unit for driving the plasma display panel,
The plasma display panel is:
A first substrate and a second substrate facing each other through the discharge space;
A first electrode comprising a first bus electrode disposed on the first substrate and extending in a first direction; and a first display electrode connected to the first bus electrode;
A second bus electrode disposed on the first substrate and extending in the first direction; and a second display electrode connected to the second bus electrode, and is paired with the first electrode. Two electrodes,
A plurality of partition walls provided on the second substrate, extending in a second direction intersecting the first direction, and spaced apart from each other;
A cell formed in a region surrounded by the first and second bus electrodes and the partition;
A first dielectric layer provided on the first substrate and covering the first and second electrodes;
A plurality of address electrodes formed of a metal material on the first dielectric layer, extending in the second direction through the cells, and disposed along the barrier ribs;
A protective layer provided on the first dielectric layer and the address electrode and exposed to a discharge space of the cell;
One field for displaying one screen is composed of a plurality of subfields,
At least one subfield of the plurality of subfields has a reset period for adjusting an amount of wall charges accumulated in the first and second electrodes and the address electrode,
The drive unit is
A second drive circuit that applies a waveform voltage that rises from a first voltage to a second voltage with the passage of time to the second electrode during the reset period;
A third drive circuit for applying a third voltage equal to or lower than the first voltage to the address electrode when the waveform voltage is applied to the second electrode;
A first drive circuit that applies a fourth voltage lower than the second voltage and higher than the third voltage to the first electrode when the waveform voltage is applied to the second electrode; A plasma display device characterized by comprising: The plasma display device according to claim 1, wherein
The plasma display apparatus, wherein the fourth voltage is lower than the first voltage. The plasma display device according to claim 1, wherein
A plasma display device comprising: the first dielectric layer and a second dielectric layer provided between the address electrode and the protective layer. The plasma display device according to claim 1, wherein
2. The plasma display device according to claim 1, wherein the address electrode is composed of a three-layer film in which chromium, copper and chromium are laminated in this order.

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