JPWO2009031377A1 - Multi-channel self-aligned transistor by double self-aligned process and method of manufacturing the same - Google Patents

Abstract

Multiple channels by double self-alignment process that can determine the position of gate, drain and source electrodes in sequence by using back exposure twice, and can achieve multi / short channel with vertical structure using comb gate electrode A self-aligned transistor and a method for manufacturing the same are provided. In a multi-channel self-aligned transistor using a double self-alignment process, an opaque gate electrode (11) processed into a comb shape on a substrate (10), an insulating film (21) stacked thereon, and processed into the comb shape. The transparent drain electrode (12) formed by the first back exposure from the substrate (10) side, the insulating film (21a) stacked thereon, and the opaque gate electrode (11) A transparent source electrode (13) formed by second back exposure from the substrate (10) side above the opaque gate electrode (11) processed into a comb shape, and a semiconductor (31) stacked thereon are formed. Have.

Description

  The present invention relates to a multi-channel self-aligned transistor using a double self-aligned process and a method for manufacturing the same.

2. Description of the Related Art Conventionally, organic electronics technology that has features of being capable of large area, ultra-thin, lightweight, and flexible has attracted attention. The switching device includes an organic transistor, and various proposals and studies have been made such as an organic transistor having a pentacene semiconductor, an organic SIT, and an organic transistor using a self-alignment technique.
JP 2005-158775 A

  Among them, Patent Document 1 is proposed by the inventors of the present application, and discloses a method for manufacturing an organic field effect transistor. There, a self-alignment method is employed in which the position of the subsequent source / drain electrodes is determined by using a back exposure method and using a gate electrode formed in advance as a mask. This method can determine the positions of the three electrodes that are the main part of the transistor and can be formed small with an overlap length of 0.8 μm or less, so that the performance of the transistor can be improved. In addition, even when the gate electrode is curved when a transistor is formed on a flexible substrate, it can be said that this is an interesting technique that enables the subsequent alignment of the drain and source electrodes.

  However, in the organic field effect transistor according to Patent Document 1, since the channel is formed in the horizontal direction with respect to the substrate, it is difficult to shorten the channel length from the viewpoint of processing technology, and it is difficult to improve the performance by shortening the channel length. . Therefore, it has been desired to realize a self-aligned organic transistor having a vertical structure in which a gate, a drain, and a source electrode are stacked on a substrate.

  In view of the above situation, the present invention uses the back exposure method twice to sequentially determine the positions of the gate, drain, and source electrodes, and achieves a multi-short channel structure with a vertical structure using comb-shaped gate electrodes. An object of the present invention is to provide a multi-channel self-aligned transistor using a double self-aligned process that can be flexible and a method for manufacturing the same.

In order to achieve the above object, the present invention provides
[1] In a multi-channel self-aligned transistor using a double self-alignment process, an opaque gate electrode (11) processed into a comb shape on a substrate (10), an insulating film (21) stacked thereon, and the comb shape The transparent drain electrode (12) formed by the first back exposure from the substrate (10) side between the processed opaque gate electrode (11) and the insulating film (21a, 21a, 22) and the transparent source electrode (13) formed by the second back exposure from the substrate (10) side above the comb-shaped opaque gate electrode (11), and the semiconductor laminated thereon (31).

  [2] In the multi-channel self-aligned transistor according to the double self-alignment process described in [1], the comb-shaped opaque gate electrode (11) is Ta.

  [3] The multi-channel self-aligned transistor according to the double self-aligned process according to [1], wherein the transparent drain electrode (12) and the transparent source electrode (13) are indium zinc oxide (IZO). And

[4] The multichannel self-aligned transistor according to the double self-aligned process described in [1] above, wherein the insulating film (21, 21a, 22) is Ta ₂ O ₅ .

  [5] In the multi-channel self-aligned transistor according to the double self-aligned process described in [1], the insulating films (21a, 22) are made of polyimide.

  [6] In the multi-channel self-aligned transistor according to the double self-aligned process described in [1], the semiconductor (31) is an organic semiconductor.

  [7] In the multi-channel self-aligned transistor according to the double self-aligned process described in [6], the organic semiconductor is pentacene.

  [8] In the multi-channel self-aligned transistor according to the double self-aligned process described in [1], the semiconductor (31) is an oxide semiconductor.

  [9] In the multi-channel self-aligned transistor according to the double self-aligned process described in [8], the oxide semiconductor is indium zinc oxide (IZO).

  [10] In a method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process, an opaque gate electrode (11) is formed on a substrate (10), the opaque gate electrode (11) is processed into a comb shape, A step of forming an insulating film (21) on the surface, and coating a photoresist on the entire surface, followed by a first back exposure with ultraviolet light from the substrate (10) side, and after development, a photoresist pattern (41) is formed. A step of forming a transparent drain electrode (12), a step of lifting off an unnecessary portion electrode together with the photoresist pattern (41), laminating insulating films (21a, 22), and then a transparent source electrode (13 ), And after the photoresist coating, a second back exposure with ultraviolet light is performed from the substrate (10) side, A step of forming a strike pattern (42), a step of processing the source electrode (13) and the insulating films (21a, 22) using the photoresist pattern (42), and a removal of the photoresist pattern (42). And a step of forming a semiconductor (31).

  [11] In the method for manufacturing a multi-channel self-aligned transistor by the double self-alignment process according to [10], Ta is used for the opaque gate electrode (11) processed into the comb shape.

  [12] In the method for manufacturing a multi-channel self-aligned transistor by the double self-alignment process according to [10], indium zinc oxide (IZO) is used for the transparent drain electrode (12) and the transparent source electrode (13). It is characterized by that.

[13] In the method for manufacturing a multi-channel self-aligned transistor according to the double self-aligned process described in [10], Ta ₂ O ₅ is used for the insulating films (21, 21a, 22).

  [14] In the method for manufacturing a multi-channel self-aligned transistor according to the double self-alignment process described in [10], polyimide is used for the insulating films (21a, 22).

  [15] The method for manufacturing a multi-channel self-aligned transistor according to the double self-aligned process according to [10], wherein an organic semiconductor is used for the semiconductor (31).

  [16] In the method for manufacturing a multichannel self-aligned transistor by the double self-aligned process according to [15], pentacene is used for the organic semiconductor.

  [17] The method for manufacturing a multi-channel self-aligned transistor according to the double self-aligned process according to [10], wherein an oxide semiconductor is used for the semiconductor (31).

  [18] The method for manufacturing a multi-channel self-aligned transistor according to the double self-aligned process according to [17], wherein indium zinc oxide (IZO) is used for the oxide semiconductor.

  According to the present invention, it is possible to realize a multi-channel self-aligned transistor by a short self-alignment process with a short channel, a multi-channel, and a self-alignment and high performance.

FIG. 3 is a cross-sectional view of a multi-channel self-aligned transistor using a double self-aligned process illustrating an embodiment of the present invention. FIG. 4 is a manufacturing process diagram of a multi-channel self-aligned transistor by a double self-alignment process showing the first embodiment of the present invention. It is a figure which shows the p-type organic-semiconductor material (the 1) based on this invention. It is a figure which shows the p-type organic-semiconductor material (the 2) which concerns on this invention. It is a figure which shows the p-type organic-semiconductor material (the 3) based on this invention. It is a figure which shows the insulating material and n-type organic-semiconductor material which concern on this invention. It is a manufacturing-process figure of the multichannel self-alignment transistor by the double self-alignment process which shows 2nd Example of this invention. It is a figure which shows the characteristic of the transistor obtained by the manufacturing method of the multi-channel self-alignment transistor by the double self-alignment process of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11 Comb gate electrode 12 Drain electrode 13 Source electrode 21, 21a, 22 Insulating film 31 Organic semiconductor or oxide semiconductor 41, 42 Photoresist pattern L Transistor channel length

  The multi-channel self-aligned transistor according to the double self-aligned process of the present invention includes an opaque gate electrode (11) processed into a comb shape on a substrate (10), an insulating film (21) stacked thereon, and the comb-shaped transistor. The transparent drain electrode (12) formed by the first back exposure from the substrate (10) side, and the insulating film (21a) laminated thereon between the opaque gate electrode (11) processed into , 22) and the transparent gate electrode (13) formed by the second back exposure from the substrate (10) side above the opaque gate electrode (11) processed into the comb shape, and laminated thereon. It has a semiconductor (31).

  Hereinafter, embodiments of the present invention will be described in detail.

  1 is a cross-sectional view of a multi-channel self-aligned transistor according to a double self-alignment process according to an embodiment of the present invention, and FIG. It is process drawing.

  In these figures, 10 is a substrate, 11 is a comb gate electrode, 12 is a drain electrode, 13 is a source electrode, 21 and 21a are insulating films, 31 is an organic semiconductor or oxide semiconductor, and 41 and 42 are photoresist patterns. . As shown in FIG. 1, the channel length L of the transistor is determined by the difference in height between the drain electrode 12 and the source electrode 13, that is, the film thickness of the insulating film 21a.

  First, a manufacturing process of a multi-channel self-aligned transistor according to the double self-alignment process of the first embodiment will be described with reference to FIG.

  First, as shown in FIG. 2A, after the substrate 10 is washed, an opaque gate electrode is formed and processed into a comb shape to obtain a comb gate electrode 11. Thereafter, an insulating film 21 is formed. Subsequently, after coating a positive photoresist on the entire surface, first back exposure with ultraviolet light is performed from the substrate 10 side using a back exposure method, and after development, a photoresist pattern is formed as shown in FIG. 41 is obtained. Here, the photoresist pattern 41 obtained by this back exposure method is about 1 μm smaller than the width of the comb-shaped gate electrode 11, but a pattern having the same width as the width of the comb-shaped gate electrode 11 can be formed. Subsequently, as shown in FIG. 2C, a transparent drain electrode 12 is formed. Thereafter, as shown in FIG. 2D, the electrode of the unnecessary portion is lifted off together with the photoresist pattern 41. Then, as shown in FIG. 2E, the insulating film 21a (the same material as the insulating film 21) and the transparent source electrode 13 are sequentially stacked. Furthermore, after the photoresist is coated, a second back exposure with ultraviolet light is performed to form a photoresist pattern 42. Next, as shown in FIG. 2F, the source electrode 13 and the insulating film 21a are processed using the photoresist pattern 42. Next, as shown in FIG. Thereafter, as shown in FIG. 2G, the photoresist pattern 42 is removed. Finally, as shown in FIG. 2 (h), by forming the organic semiconductor 31, a multi-channel self-aligned transistor by a double self-alignment process is completed.

In this first embodiment, Ta is used for the comb-shaped gate electrode 11, Indium zinc oxide (IZO) is used for the transparent drain / source electrodes 12 and 13, Ta ₂ O _{5 is} used for the insulating films 21 and 21a, and, for example, pentacene is used for the organic semiconductor 31. Using. Further, an oxide semiconductor such as indium zinc oxide can be used instead of the organic semiconductor.

  Hereinafter, materials used for each part of the multi-channel self-aligned transistor by the double self-alignment process will be described.

  First, the organic material will be described.

  A p-type organic semiconductor material is shown in FIGS. 3 to 5, and an insulating material and an n-type organic semiconductor material are shown in FIG.

First, the p-type organic semiconductor material will be described. Pentacene is the most representative organic material. At present, the value exceeding the mobility of 1.5 cm ² / Vs has been reported by each organization, and the value exceeding the mobility of single crystals of about 3 cm ² / Vs is also reported. There is no doubt that the characteristics exceeding a-SiFET can be obtained. Relying on the vapor deposition method from the viewpoint of being a low-molecular-weight material system, the material that can be made flexible is merely a feature of the transistor, and its future potential is poor. Recently, however, there have been reports of coating formation and inkjet printing (IJP) formation by heating 1,2,4-trichlorobenzene or dichlorobenzene solution. As a result, it is considered promising to be used as a transistor aiming at large area and flexible applications in the future. Hereinafter, initial report and mobility are polyacetylene, organic dye (1.5 × 10 ⁻⁵ cm ² / Vs), polythiophene (10 ⁻⁵ cm ² / Vs), p, p′-biphenol (4 × 10 ^−4). cm ² / Vs), poly (3-hexylthiophene (10 ⁻⁴ cm ² / Vs), Polyacetylene (10 ⁻⁴ cm ² / Vs), Poly (3-alkylthiophene) (3 × 10 ⁻³ cm ² / Vs), poly (1,4-naphthalene vinylene) and poly (p-phenylene vinylene) ( 2 × 10 -6 cm 2 / Vs), polypyrrole ohmic ^{polythiophene (2 × 10 -4 cm 2} /Vs),polythienylenevinylene(0.2 cm ² / Vs), oligothiophene substituents ^{(10 -2 cm 2 / Vs)} , α-sexithienyl, regioregular poly (3-hexylthiophene) (RR-P3HT) (0.1cm 2 / Vs), quaterthiophene, sexithiophene and Octithiophene ( as 0.072cm ² / Vs) has been reported. material system, mainly thiophenic and the introduction of highly oriented by regioregular and longer chain of about mobility 0.1 cm ² / Vs is achieved Thereafter, 1,4-bis (5'-hexyl-2,2'-bithiophen-5-yl) benzene (2-dH-TTPTT) (0.02 cm ² / Vs), BTQBT (0.2 cm ² / s), anthracene oligomer ^{3A (0.13cm 2 / Vs),} oligoselenophene DH5S (0.038cm 2 /Vs),Ovalene(Ov)(0.02cm 2 /Vs),Hexabenzocoronene(Hbc)(5.6×10 - ^{3 cm 2 /Vs),Ddicoronylene(Dc)(0.03cm 2 / Vs)} , stilbene π-conjugated polymer ^{(4.2 × 10 -3 cm 2 /} Vs), porphyrin (0.01cm ² / Vs), bennzo ^{-dichalcogenophene (0.17cm 2 / Vs),} polyfluorene derivatives ^{(0.024cm 2 /Vs),C60MC12(0.028cm 2 / Vs)} , TET (2 × 10 -4 cm 2 /Vs),Ov(0.07cm ^{2 /Vs),6T(0.08cm 2} Vs), containing Se material (0.17cm ² / Vs), PTAPV polymer ^{(3.6 × 10 -3 cm 2 /} Vs), hexabenzocoronene derivative (0.012cm ² / Vs), heteroacene compound (0.02 cm ² / Vs), thiophene-pyridine skeleton material (10 ⁻³ cm ² / Vs), thienylfuran oligomer (1.4 × 10 ⁻² cm ² / Vs), diiminobenzosemiquinonate ligand (0.038 cm) ² / Vs) has been reported. As a trend, various attempts have been made such as adopting strong intermolecular interaction by introducing S or Se, examining condensed polycyclic aromatic compounds, and improving solubility by introducing alkyl groups.

  Next, the insulating film material will be described.

As an insulating film material, thermally oxidized SiO ₂ has been used as a typical insulator because of its properties such as high insulation, stability, high flatness, hydrophilicity, low fixed charge density, and low in-band level. However, for the independent operation of the transistor, it is necessary to separate the gate electrode for application, such as polymer insulating films such as PMMA, PS, PVA, Ta ₂ O ₅ , Al ₂ O ₃ , cyanoethyl pullulan, acetyl There have been reported fluorinated pullulan, polyimide, poly-p-xylylene (PPX), coated inorganic insulating film SiO ₂ and the like. Here, the insulating film of inorganic Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ or the like is a material system often used as a p-channel semiconductor material of an inorganic TFT. In addition, in the case of cyanoethyl pullulan, mobility of 0.61 cm ² / Vs in combination with RR-P3HT was reported and attracted attention. Cyanoethyl pullulan is a material system that has been used as a high dielectric constant binder for dispersion-type inorganic EL elements, and has an interesting dielectric property. On the other hand, while the problem of lowering the process temperature remains, we should pay attention to polyimide and the like from the viewpoint of material stability. Some polyimides have the ability to vertically align rod-like molecules, and good orientation is expected in combination with pentacene. PPX has been studied as a coating film for organic EL elements in the past, but can be formed by low-temperature CVD, and has been studied as a coating film for organic devices as well as an insulating film for transistors. The same applies to the coating type SiO ₂ , and in the conventional semiconductor process, complete SiO ₂ has been realized at about 400 ° C. using oxygen plasma and tetraethylorthosilicate (TEOS), but recently it can be formed at room temperature mainly for building materials. It is interesting that SiO ₂ has been put into practical use. In addition, high-k materials such as HfO ₂ , ZrO ₂ , HfAlSiO _x , HfAlSiON, LaAlO _x , and LaSiO _x are also expected as materials that give a transistor a high current driving force.

  Next, the material of the transparent electrode will be described.

As a material for the transparent electrode, ITO, ZnO-based, In ₂ O ₃ —ZnO (IZO) -based, Ga-doped ZnO (GZO) film, silver-added ITO film, CuAlO ₂ , SrCu ₂ O ₂ thin film, SrCu ₂ O ₂ thin film In ₄ Sn ₃ O ₁₂ film, InGaZnO ₄ film, TiN, AlZnO and the like.

As typical oxide semiconductors, indium zinc oxide (IZO), ITO, ZnO, InGaO ₃ (ZnO) _{5, and the} like can be given.

Further, Ta, Mo, W, or the like can be used as a material for the gate electrode. These materials are characterized by (1) taper processing, (2) low resistance (resistivity is 100 μΩcm ² or less), and (3) good process stability.

  FIG. 7 shows a manufacturing process of a multi-channel self-aligned transistor by a double self-aligned process according to the second embodiment of the present invention. The manufacturing process of the second embodiment is almost the same as that of the first embodiment, except that the material of the insulating film 22 formed a second time is changed as shown in FIG. In this embodiment, polyimide is used as the material of the insulating film 22.

FIG. 8 is a diagram showing the characteristics of a transistor obtained by the method of manufacturing a multi-channel self-aligned transistor according to the double self-alignment process of the present invention. The horizontal axis represents the drain voltage V _D (V), and the vertical axis represents the drain current I. _D (μA).

  Here, the channel length L of the transistor was 0.25 μm. In general, when a transistor is shortened to a submicron order, the saturation characteristics deteriorate. This is thought to be due to the presence of a channel portion that cannot be controlled by the gate electrode, space charge limiting current, deterioration of pinch-off characteristics due to a high electric field at the drain end, and the like. This phenomenon can be improved by low electric field scaling that keeps the electric field in the transistor constant, but it is not perfect.

  According to the present invention, transistor characteristics exhibiting saturation characteristics were obtained even though the channel length of the transistors was as short as 0.25 μm. One of the reasons for this phenomenon is that the transistor is easily pinched off due to the non-uniformity of the channel formation due to the gate electric field at the drain and source electrodes, and the pentacene thickness of the organic semiconductor is good. It is conceivable that the transistor characteristics became excellent. In any case, transistor characteristics with good saturation characteristics could be obtained.

  In addition, this invention is not limited to the said Example, Based on the meaning of this invention, a various deformation | transformation is possible and these are not excluded from the scope of the present invention.

  The multi-channel self-aligned transistor according to the double self-aligned process of the present invention can be used as a transistor that enables self-aligned fabrication of a short channel transistor for improving the performance of the transistor.

Claims (18)

(A) an opaque gate electrode (11) processed into a comb shape on the substrate (10);
(B) an insulating film (21) laminated thereon;
(C) a transparent drain electrode (12) formed by a first back exposure from the substrate (10) side between the opaque gate electrode (11) processed into the comb shape;
(D) Transparent formed by the second back exposure from the substrate (10) side above the insulating films (21a, 22) stacked thereon and the opaque gate electrode (11) processed into the comb shape. A source electrode (13);
(E) A multi-channel self-aligned transistor by a double self-aligned process characterized by having a semiconductor (31) stacked thereon.   The multi-channel self-aligned transistor according to claim 1, wherein the comb-shaped opaque gate electrode (11) is Ta. .   The multi-channel self-aligned transistor according to claim 1, wherein the transparent drain electrode (12) and the transparent source electrode (13) are indium zinc oxide (IZO). Multi-channel self-aligned transistor with self-aligned process. In multi-channel self-aligned transistor of claim 1, wherein the double self-aligned process, the insulating film (21, 21a, 22) are multi-channel self-aligned by the double self-aligned process, which is a Ta ₂ O ₅ Transistor.   The multi-channel self-aligned transistor according to claim 1, wherein the insulating films (21a, 22) are polyimide.   The multi-channel self-aligned transistor according to claim 1, wherein the semiconductor (31) is an organic semiconductor.   The multi-channel self-aligned transistor according to claim 6, wherein the organic semiconductor is pentacene.   The multi-channel self-aligned transistor according to claim 1, wherein the semiconductor (31) is an oxide semiconductor.   The multi-channel self-aligned transistor according to claim 8, wherein the oxide semiconductor is indium zinc oxide (IZO). (A) forming an opaque gate electrode (11) on the substrate (10), processing the opaque gate electrode (11) into a comb shape, and forming an insulating film (21) thereon;
(B) After coating the entire surface of the photoresist, performing a first back exposure with ultraviolet light from the substrate (10) side, and after development, forming a photoresist pattern (41);
(C) forming a transparent drain electrode (12);
(D) a step of lifting off the unnecessary electrode together with the photoresist pattern (41);
(E) Insulating films (21a, 22) are laminated, then transparent source electrode (13) is laminated, and after the photoresist coating, the second back exposure by ultraviolet light from the substrate (10) side. Performing a photoresist pattern (42),
(F) processing the source electrode (13) and the insulating films (21a, 22) using the photoresist pattern (42);
(G) removing the photoresist pattern (42);
(H) A method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process, comprising: forming a semiconductor (31).   11. The method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process according to claim 10, wherein Ta is used for the comb-shaped opaque gate electrode (11). A method of manufacturing a self-aligned transistor.   11. The method of manufacturing a multi-channel self-aligned transistor according to the double self-aligned process according to claim 10, wherein indium zinc oxide (IZO) is used for the transparent drain electrode (12) and the transparent source electrode (13). A method of manufacturing a multi-channel self-aligned transistor using a double self-aligned process. 11. The method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process according to claim 10, wherein Ta ₂ O ₅ is used for the insulating film (21, 21a, 22). A method for manufacturing a channel self-aligned transistor.   11. The method of manufacturing a multi-channel self-aligned transistor according to claim 10, wherein polyimide is used for the insulating films (21a, 22). Production method.   The method of manufacturing a multi-channel self-aligned transistor according to claim 10, wherein an organic semiconductor is used for the semiconductor (31). .   16. The method of manufacturing a multi-channel self-aligned transistor according to claim 15, wherein pentacene is used for the organic semiconductor.   11. The method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process according to claim 10, wherein an oxide semiconductor is used for the semiconductor (31). Method.   18. The method of manufacturing a multi-channel self-aligned transistor by a double self-aligned process according to claim 17, wherein indium zinc oxide (IZO) is used for the oxide semiconductor. A method for manufacturing a transistor.

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