JPWO2006085608A1 - Semiconductor device and semiconductor device design method - Google Patents

Abstract

In the design method of an LSI chip (1) having a plurality of logic blocks (11) formed in cascade and connected to each other and having functions that can be changed, the characteristics of the logic blocks (11) are measured. The logic block (11) is reconfigured by changing the function of the logic block (11) so as to suppress the performance degradation of the LSI chip (1) due to the variation in the characteristics.

Description

  The present invention relates to a semiconductor device including a field programmable device such as a field programmable gate array (FPGA (registered trademark)) and a design method thereof.

  Conventionally, LSI (integrated circuit) chip manufacturing technology has entered the nanometer scale, so that millions of transistors are created in one die on the substrate. It has become possible to It is extremely difficult to manufacture such a large number of transistors with the same characteristics. In addition, each of the above characteristics is different between dies (D2D, die-to-die) and inside the die (WID, with-die).

  Known Document 1 (S. Ohkawa, M. Aoki, and H. Masuda, “Analysis and Characterization of Device Variations in an LSI Chip used an integrated device.” (pages 155-165, 2004.) shows that variation in WID was remarkably observed in an LSI fabricated by a 90 nm scale process. Known Document 2 (Bowman, KA, S. G. Duvall, and J. D. Meindl, "Impact of Diet-to-Die and Within-Diet Fractionations on the Maximum Clamp." Solid-State Circuits, vol. 37, no. 2, pages 183-190, 2002. In ps "ICCAD 2004, pages 343-346,2004.), When the scale of the process reduced gradually, the variation in the WID has been shown to become a primary.

  As described above, in the conventional configuration, the characteristics of the LSI differ from LSI chip to LSI chip, thereby reducing the yield and saturation of the operation speed. The device endeavors to minimize variations as much as possible, but this is very expensive. On the circuit side, various techniques for canceling the variation have been proposed, but it is questionable whether one of the larger variations can be dealt with.

  Specifically, in each logic block of the LSI chip as described above, a certain critical path (path with zero margin time, that is, the earliest start time (the time when the earliest can be started) and the latest start time (at the latest at this time). Includes the transistors whose characteristics have deteriorated due to variations in the characteristics of the transistors along the path of the activity having the same time).

  As a result, the conventional LSI chip including the transistor having the above-described characteristics deteriorates does not operate accurately at a desired clock frequency, and thus the yield of an LSI chip such as an ASIC is considerably reduced. Create a point.

  The present invention has been made in view of the above problems, and its purpose is to individually measure the characteristics of each circuit in an LSI chip and optimally reconfigure (reconfigure) each circuit based on the results. It is an object of the present invention to provide a semiconductor device and a design method thereof that can improve yield and suppress cost increase.

  In order to solve the above problems, a semiconductor device according to the present invention includes a substrate, a plurality of information processing circuits formed on the substrate in cascade connection with each other, the functions of which can be changed, and the substrate. And a measuring circuit for measuring the characteristics of each information processing circuit.

  According to the semiconductor device, the characteristic of each information processing circuit is measured by the measurement circuit, and the function of each information processing circuit is changed from the measurement result of the characteristic variation so as to reduce the performance deterioration due to the variation. Since the above performance deterioration can be suppressed by reconfiguring, the yield of the obtained semiconductor device can be improved.

  In order to solve the above-described problem, a semiconductor device design method according to the present invention includes a plurality of information processing circuits that are formed in cascade and connected to each other, and each of which can change its function, on a substrate. In this case, the characteristics of each of the information processing circuits are respectively measured, and the functions of the information processing circuits are changed to reconfigure the information processing circuits so as to suppress the performance degradation of the semiconductor device due to variations in the characteristics. It is characterized by doing.

  According to the above method, the characteristic of each information processing circuit is measured, and the function of each information processing circuit is changed and reconfigured from the measurement result of the characteristic variation so as to suppress the performance deterioration due to the variation. Thus, the performance deterioration can be reduced, and the yield of the obtained semiconductor device can be improved.

  Other objects, features, and advantages of the present invention will be fully understood from the following description. The benefits of the present invention will become apparent from the following description with reference to the accompanying drawings.

It is a figure which shows the design method of the conventional semiconductor device. It is a figure which shows the design method of the semiconductor device of this embodiment. It is a block diagram which shows each LUT block as an example of each logic block of the semiconductor device of the said embodiment. It is a wiring diagram which shows the connection relation of each said LUT block. It is a wiring diagram which shows the fractal arrangement | positioning of each said LUT block. It is a block diagram which shows the measurement principle of the characteristic variation of each said LUT block. It is a block diagram which shows the pulse generation circuit for a measurement used for the measurement of the said characteristic dispersion | variation. It is a waveform diagram of a measurement clock generated by the measurement pulse generation circuit. It is a block diagram which shows arrangement | positioning of each counter used for the measurement of the said characteristic dispersion | variation. 3 shows an example of a reconfiguration procedure in the design method of the present embodiment, the initial critical path length in each circuit block as each LUT block, the initial transistor performance in each circuit block, and the initial It is a figure which shows the result of having been reconfigure | reconstructed from (Optimized). 4 is a graph showing a critical path length distribution and a transistor performance distribution in the design method of the present embodiment, respectively. It is a histogram which shows the chip performance ratio (when the variation width of operation performance is set to 6% based on the measurement result) between the conventional fixed arrangement and the arrangement which compensates for the characteristic variation of the present embodiment. It is a histogram which shows the chip performance ratio (when variation width will be 12% of twice) of the conventional fixed arrangement and the arrangement which compensated for variation of this embodiment. It is a histogram which shows chip performance ratio (when variation width is 18 times of 3 times) of the conventional fixed arrangement and the arrangement which compensated for variation of this embodiment. It is a graph which shows the yield fall accompanying the reduction | decrease in a design margin in this embodiment and the conventional design method.

  The embodiment of the present invention will be described with reference to FIGS. In the semiconductor device design method according to the present embodiment, as shown in FIG. 1B, a plurality of logic blocks (information processing circuits) 11 whose functions can be changed are connected to each other in cascade on the substrate. This is suitable for manufacturing an LSI chip (semiconductor device) 1.

  A single LSI chip 1 may be formed or a plurality of LSI chips 1 may be formed on a silicon wafer. In the present embodiment, a plurality of LSI chips 1 are formed on a silicon wafer. Moreover, the said board | substrate will not be specifically limited if it is a thing for semiconductor device manufacture, A silicon substrate etc. are mentioned.

  Further, the LSI chip 1 was manufactured by a 90 nm scale process using an existing photolithography technique. The scale is not particularly limited, but the effect can be further enhanced when a scale having a finer structure such as a 90 nm scale or a 65 nm scale, which is 120 nm or less, is used.

  In the design method, the characteristics of the logic blocks 11 are measured and the functions of the logic blocks 11 are changed so as to suppress the performance degradation of the LSI chip 1 due to variations in the characteristics. Each logic block 11 is reconfigured.

  In the design method of the present embodiment, each logic block 11 is reconfigured by the above reconfiguration as compared with the conventional LSI chip 31 such as the cell-based fixed-structure ASIC shown in FIG. Since the arrangement of the functions can be optimized, the proportion of non-defective products (OK) can be increased and the yield can be improved.

  That is, as shown in FIG. 1A, an LSI chip 31 such as an ASIC with a normal fixed arrangement does not satisfy the required operating performance due to characteristic variations (NG), and an LSI chip that cannot be shipped as a product can be produced. In the design method of the embodiment, as shown in FIG. 1B, a reconfigurable LSI chip 1 based on a reconfigurable device is manufactured, and after completion, the characteristics in the LSI chip 1 are obtained for each LSI chip 1. By optimizing the arrangement according to the variation and performing the reconfiguration, the variation can be compensated and all the LSI chips 1 can satisfy the required operation performance. In other words, the design method according to the present embodiment is contrary to the conventional technique for suppressing variation as much as possible, and is a technology that exhibits the effect as the variation is larger. If (ASIC) is replaced with the semiconductor device (reconfigurable LSI) of the present embodiment, it is not necessary to suppress excessive variation in a fine process, and an increase in cost can be suppressed while improving yield.

  Next, reconstruction according to characteristic variation will be described. First, the variation in the LSI chip 1 is measured by some method, and the operation speed distribution of each logic block (or a group in which some logic blocks are grouped) 11 is grasped. Then, during reconfiguration, by assigning a circuit configuration with a long critical path to a block (group) with a fast operation and a circuit configuration with a short critical path to a block (group) with a slow operation, and optimizing the circuit configuration It is considered that variations in the LSI chip 1 can be compensated.

  This variation compensation can be expected not only to improve the yield, but also to improve the performance of the LSI chip 1 and reduce the design margin as mentioned in the problem of the present invention. This can eventually be used as an alternative to conventional ASICs. That is, even if the overhead (disadvantage) due to the reconfigurable semiconductor device is included, the performance superior to the fixedly arranged ASIC can be exhibited. In that case, the flexibility, the cost and labor at the time of design, and the significant reduction in the design period, which are advantages of the reconfigurable semiconductor device, can be enjoyed as they are.

  Next, the structure of the LSI chip 1 will be described. As shown in FIG. 2, the LSI chip 1 has a plurality of logic blocks (LB) 11 whose functions can be changed, connected in cascade. Each logic block (LB) 11 can change its function. Each of the logic blocks (LB) 11 is set in a rectangular shape, and the sides adjacent to each other are set so as to be substantially parallel so that they are arranged in a close-packed manner. Yes. Each wiring is formed to cross each other in a mesh shape so as to surround the periphery of each logic block (LB) 11. Each logic block (LB) 11 and each wiring are formed in a multilayer structure on the substrate.

  The method of changing the function by writing a program to a logic block or wiring is as follows: (1) writing to a volatile memory such as SRAM, (2) writing to a non-volatile memory such as EPROM or EEPROM, and (3) anti-voltage by applying a voltage. There are three main types: short-circuiting the fuse. In this embodiment, EPROM and EEPROM require a special manufacturing process different from that of a normal LSI, and the antifuse cannot be rewritten once written. In this embodiment, (1) SRAM method is used. However, it is also possible to use (2) or (3).

  As shown in FIG. 2, the logic block 11 according to the present embodiment is configured with an LUT (look-up-table, circuit element) and a DFF included in the logic block of the SRAM type FPGA as basic units. Here, this basic unit is called an LUT block. The LUT includes 16 D-FFs that are SRAMs and 16: 1 multiplexers (MUX4). In FIG. 2, the 16 D-FFs in the LUT are called “DFF”, and the DFF attached outside the LUT is called “SDFF”.

  The SRAM FPGA rewrites the logic by writing a value in this DFF (originally SRAM) at the time of reconfiguration. That is, the logic can be rewritten by rewriting the values of 16 SRAMs by regarding the multiplexer selection signals A, B, C and D as the input of the logic block and the output of the multiplexer as the output of the logic block. It becomes. The inputs A, B, C, and D of the blocks may be connected to the switch matrix so that the connection relationship between the blocks can be changed. However, in this embodiment, as shown in FIG. It may be connected.

  In the present embodiment, 2048 LUT blocks are connected in cascade with each other as a whole circuit, and changes in the output signal Mout of the LUT are propagated to the subsequent LUT blocks one after another, and the difference in the number of propagation stages. Thus, the above-described characteristic variation is measured. The principle of measurement will be described later.

  However, the characteristic variations of the transistors constituting the LUT block are similar if the transistors placed close to each other show close characteristics. Therefore, if the LUT blocks are arranged on a straight line and propagated to a far-distant block, the characteristics will vary. May be canceled. For example, if the characteristics of the LUT block in the vicinity of the point where propagation is started are greatly improved and the characteristics of the LUT block near the end of propagation are greatly degraded, As a result, the average number of propagation stages is expected.

  Therefore, in the present embodiment, each LUT block is arranged as each logic block 11 in a self-similar fractal form as shown in FIG. 4 so that the difference in the number of propagation stages due to characteristic variation appears as much as possible. In addition, LUT aggregate blocks, each of which is a group of 16 LUT blocks connected in cascade, are also arranged in a self-similar fractal shape. With this arrangement structure, propagation of signal changes occurs in order from the closest to the starting point, and cancellation (cancellation) of characteristic variations can be avoided as much as possible.

Next, a characteristic variation measuring mechanism and measuring method in the LSI chip 1 will be described. In the measurement method, first, in order to measure the characteristic variation, all the SDFFs are reset, and the DFF values are written as follows.
A certain block is set to the first stage, that is, a propagation start point, and all DFF values are set to 1. As a result, the LUT output of this block is always 1.
The DFF values of the second block are set to 0, 0, 1, 1, 0, 0, 1, 1,. Thereby, the LUT output of this block coincides with the input B. (Does not depend on inputs A, C, D)
・ The DFF values of the third and subsequent blocks are set to 0, 1, 0, 1,. As a result, the LUT output of this block matches the input A. (Does not depend on inputs B, C, D)
Since only the values to be written to the DFF are different, an arbitrary block can be set in the first stage, the second stage, the third stage and the subsequent stages.

  Further, as shown in FIG. 3, the input B of each block is connected to the previous stage Dout, and the input A is connected to the previous stage Mout. Since SDFF is reset at this stage, the first stage Dout, that is, the second stage input B is 0, and the second stage LUT output Mout, that is, the third stage input A is also 0. Therefore, the LUT output Mout of the third stage is also 0, and the LUT output is 0 similarly in the fourth and subsequent stages. Also, the SDFF input can be switched between the LUT output and the Sin by the scan signal, but it is set on the LUT output side.

  In this state, as shown in FIG. 5 and FIG. 6B, two clock waveforms (CLK_S) are input at short intervals in common for all SDFFs. The clock waveform may be generated by a generation circuit (measurement pulse generation circuit) shown in FIG. 6A arranged in the circuit. In the generation circuit, as shown in FIG. 6B, two clocks are generated in which the input signals A to D are started at different timings.

  FIG. 5 shows changes in each signal when such a clock waveform is input to each SDFF. First, the first stage SDFF takes in 1 at the first rise of the clock signal, and the first stage Dout, that is, the second stage input B becomes 1. As a result, the second-stage LUT output, that is, the third-stage input A becomes 1, and the third-stage LUT output becomes 1.

  Similarly, 1 is propagated to the subsequent stage one after another. After that, only the SDFF of the block in which the propagation of 1 has reached 1 at the time of the second rising edge of the clock signal takes in 1. Therefore, the number of SDFFs that have taken in 1 depends on the operation performance of the part. become. Since an arbitrary block can be used as the first stage, that is, the start point of propagation, this is performed at an arbitrary location on the LSI chip 1, and the characteristic variation in the LSI chip 1 is compared by comparing the number of SDFFs incorporating 1. Can be measured.

  In the measurement mechanism according to the present embodiment, as shown in FIG. 7, a counter (detection circuit) that counts the number of SDFFs that have taken in 1 is provided. When the input to the SDFF is switched to the Sin side, all the SDFFs are connected in a shift register shape as shown in FIG. For example, one counter is provided for every 64 SDFFs, and the counter is designed to increment the value of the internal register if the input is 1 at the rising edge of the clock signal. Therefore, when the clock signal is input 64 times in common to the SDFF and the counter in this state, the number of 1 held in 64 SDFFs is stored in the register inside the counter. The counters are connected by a bus as shown in the figure. When a clock signal is further input after switching the control signal for the counter, the values stored in each register are sequentially output to the external output pins.

  As described above, the basic unit composed of the LUT and the DFF is included in the original FPGA, and the characteristic variation measurement mechanism (measurement circuit) such as the generation circuit and the counter described above is incorporated in the conventional FPGA. The overhead in that case is considered to be very small.

  Next, we examined the experimental results showing the improvement in yield and processing speed by rearrangement. The technical idea of the present invention is that each circuit block can be reconfigured on a reconfigurable semiconductor device based on the characteristics of the transistor to optimize the arrangement of the circuit blocks. In this embodiment, compared with a semiconductor device in which the conventional arrangement is fixed, the improved yield obtained by the semiconductor device in which the arrangement is optimized using the re-arrangeable semiconductor device according to this embodiment, and The processing speed was evaluated.

  First, in a reconfigurable semiconductor device, each circuit block of each function occupies the same number of logic blocks 11, but each logic block 11 has a different critical path. ing. The different lengths in the respective critical paths have a normal distribution.

  The LSI chip 1A and the LSI chip 1B shown in FIG. 8 show an initial arrangement in which circuit blocks of each function are closely adjacent to each other in a tile shape. The circuit blocks have different performances due to variations in the die interior (WID) or between the dies (D2D).

  The LSI chip 1A to LSI chip 1C are for explaining a reconfiguration operation to be described later. Both the LSI chip 1A and the LSI chip 1B are the LSI chip 1, and the LSI chip 1C is the LSI chip 1A. It shows after the reconstruction of the area surrounded by the two-dot chain line.

  In the present embodiment, it is assumed that the above-described variation within the die (WID) and variation between each die (D2D) are random according to a Gaussian (normal) distribution. In the conventional FPGA, each circuit block indicating each function is fixed in the initial arrangement.

  In this embodiment, it is assumed that each circuit block can be exchanged by the proposed method (scheme) within a small area. In FIG. 8, each circuit block of the LSI chip 1A can be replaced within each 3 × 4 circuit block at the upper left. In the present embodiment, reconfiguration is performed as shown in the LSI chip 1C. This will be described in detail below.

  First, the number written on each circuit block of the LSI chip 1A indicates the critical path length of each circuit block, and the number written on each circuit block of the LSI chip 1B is the number of each circuit block. The performances of the transistors are shown respectively. For example, the critical path length of the circuit block 21A of the LSI chip 1A is “35” as illustrated, and the transistor performance is “19” as illustrated.

  Here, in the circuit block 21A, the transistor performance is below the critical path length of the circuit block. In such a case, the LSI chip 1 having the circuit block 21A does not operate at the target processing speed.

  Therefore, in this embodiment, the circuit block is replaced (reconfigured) as shown in the LSI chip 1C. More specifically, the circuit block 21B of the LSI chip 1A has a critical path length of “19” as illustrated. On the other hand, the performance of the transistor is “50”. Here, if the circuit block 21A and the circuit block 21B are replaced, the transistor performance does not fall below the critical path length in either the circuit block 21A or the circuit block 21B. Therefore, as shown in the LSI chip 1C, the circuit block 21A and the circuit block 21B are replaced. Thereby, the LSI chip 1 can be operated at a target processing speed. The same applies to other circuit blocks shown in the LSI chip 1C.

  In the present embodiment, in order to simplify the trial production, the routerability (wiring possibility) between the circuit blocks of the respective functions arranged is not considered. Therefore, the area of optimization is limited to a small area so as not to impair the feasibility.

  FIG. 9 shows the distribution of each critical path of each circuit block of each function and the characteristic distribution of each transistor of the manufactured LSI chip. At this time, each circuit block is assumed to have 256 (16 × 16) logic blocks.

  In order to evaluate the improvement in yield and processing speed by rearrangement, the former distribution was fixed (Nc = 80, σc = 16), and the latter distribution was parameterized by two parameters (Nf, σf). . If the performance of the transistors in each circuit block falls below the critical path length of each circuit block, as described above, the LSI chip in each circuit block does not operate at the target processing speed.

  As shown in Table 1, semiconductor devices were respectively manufactured under three conditions (from a small condition 1 to a large condition 3). Each of these conditions satisfies the following equation: Nc + 3σc = 80 + 3 × 16 = Nf−3σf

図１０〜図１２は、各動作処理速度を、目標の処理速度によって標準化したものである。表１は、本実施形態の方法と、従来の方法とでの、歩留りと処理速度の平均とを示した。各機能の各ブロックは、２５６×２５６のアレイ内に配置されている。最適化のための領域の大きさは、４×４に設定され、作製されたＬＳＩチップの数は１０００である。

10 to 12, each operation processing speed is standardized according to a target processing speed. Table 1 shows the average yield and processing speed in the method of this embodiment and the conventional method. Each block of each function is arranged in a 256 × 256 array. The size of the area for optimization is set to 4 × 4, and the number of manufactured LSI chips is 1000.

  In the condition (Cond.) 1, the yield was 0% in the case of the conventional fixed arrangement, but it was 56.1% in the arrangement optimized by the rearrangement of the present embodiment. Under the conditions (Cond.) 2 and 3, the yield is 100%, and the average processing speed is improved by 14% and 35%, respectively, compared to the conventional fixed type.

  Next, the design margin was examined. As described above, in the reconfiguration according to the present embodiment, the setting of the center value of the operation speed distribution corresponds to the setting of the design margin. Therefore, the effect on the design margin of the design method of the present embodiment was examined by repeating the reconstruction while changing the center value little by little.

  In this study, the variation width of the operation speed distribution is assumed to be 6% of the center value. The critical path length (converted to the number of logical block stages) of the circuit configuration is set to 19 stages at the longest.

  If no characteristic variation occurs, that is, if the operation speed of all logic blocks on the chip matches the center value, ideally the yield is 100% with the center value of the operation speed being 19.00. The yield should be 0% if it is a little smaller than 19.00.

  Therefore, in this examination, when the central value of the operation speed distribution is 19.00, it is considered that the design margin is 0, and the difference from the central value of 19.00 is regarded as the design margin. Furthermore, this design margin is divided by 19.00 and expressed as a percentage.

  First, when 10,000 chips are evaluated with a design margin of 0.80 (4.2%), the yield is 99.98% in the fixed arrangement and is completely 100.00% in the arrangement in which the variation is compensated. FIG. 13 shows the result of obtaining the yield in 10,000 chips for each margin while reducing the design margin from 0.05 to 0.05 in increments of 0.26%.

  In the fixed arrangement, the yield starts to decrease immediately, but in the arrangement (reconstruction) considering the variation, 100% is maintained up to the margin 0, and when it becomes negative, the yield starts to decrease rapidly. In other words, it can be concluded that a design margin is not necessary in this study model. At this time, the yield in the case of the fixed arrangement has decreased to 10% or less. From the above examination results, it can be said that the design method of this embodiment is very effective in reducing the design margin.

(Conclusion)
In the present embodiment, the semiconductor device that can improve the yield and the processing speed by using the semiconductor device that can be rearranged and the design method thereof have been described. The LSI chip of the LUT array was manufactured by a 90 nm scale CMOS manufacturing technology so that the process variation of each LUT could be measured.

  As a result of the rearrangement according to the present embodiment, it was found that the yield of the LSI chip as the obtained semiconductor device can be improved, and the processing speed can be improved by up to 35%.

  Each of the logic blocks 11 of the semiconductor device (LSI chip 1) is preferably a field programmable device and is preferably arranged in a fractal shape.

  Each of the logic blocks 11 includes a circuit element for storing logic for realizing an arbitrary logic function, and a flip-flop for storing an output of the circuit element. A measurement pulse generation circuit and a detection circuit, the measurement pulse generation circuit generating a first pulse and a second pulse delayed by a predetermined amount with respect to the first pulse, and for each flip-flop The first pulse and the second pulse are applied, and the detection circuit is connected for each predetermined number of flip-flops and detects the output of the connected flip-flops. There may be.

  Further, the characteristic of the logic block 11 may be the length of the critical path.

  It should be noted that the specific embodiments or examples made in the best mode for carrying out the invention are merely to clarify the technical contents of the present invention, and are limited to such specific examples. The present invention should not be construed as narrowly defined but can be implemented with various modifications within the spirit of the present invention and the scope of the following claims.

  The semiconductor device and the design method thereof according to the present invention can improve the yield by suppressing the influence of the characteristic variation due to the high integration by the most configuration even if the process scale is a nanoscale and high integration is achieved. In addition, since the processing speed can be improved, it can be suitably applied to general industrial uses of semiconductor manufacturing such as dedicated LSI (ASIC).

Claims (6)

A substrate,
On each of the above substrates, a plurality of information processing circuits formed in cascade with each other and capable of changing functions;
A measurement circuit for measuring the characteristics of each information processing circuit formed on the substrate;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein each of the information processing circuits is a field programmable device.   3. The semiconductor device according to claim 1, wherein each of the information processing circuits is arranged in a fractal shape. Each of the information processing circuits includes a circuit element for storing logic for realizing an arbitrary logic function and a flip-flop for storing an output of the circuit element, respectively.
The measurement circuit includes a measurement pulse generation circuit and a detection circuit,
The measurement pulse generation circuit generates a first pulse and a second pulse delayed by a predetermined amount with respect to the first pulse, and applies the first pulse and the second pulse to each flip-flop. And
4. The detection circuit according to claim 1, wherein the detection circuit is connected for each predetermined number of flip-flops and detects an output of the connected flip-flops. 5. Semiconductor device.   5. The semiconductor device according to claim 1, wherein the characteristic of each information processing circuit is a critical path length. In a method for designing a semiconductor device having a plurality of information processing circuits formed on a substrate, each of which is formed by being connected to each other in cascade and having a function changeable,
Measure the characteristics of each information processing circuit,
A method for designing a semiconductor device, comprising: reconfiguring each information processing circuit by changing a function of each information processing circuit so as to suppress performance deterioration of the semiconductor device due to variation in each characteristic.

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