JP7027977B2 - Oscillation circuit and control method of oscillation circuit - Google Patents

Description

The disclosure of the present application relates to an oscillation circuit and a control method of the oscillation circuit.

By incorporating a ring oscillator for a monitor in an LSI (Large Scale Integration), the operating limit frequency of the LSI can be estimated based on the oscillation frequency of the ring oscillator. By estimating the operating limit frequency of the LSI from the oscillation frequency of the ring oscillator that can be measured at the wafer stage, it is possible to determine whether the LSI is a good product or a defective product before packaging the LSI. It is also possible to predict what level the frequency rank of the LSI is. Such estimation is possible because the logic gate of the critical path that determines the operating limit frequency and the logic gate of the ring oscillator for monitoring include the logic gate created by the same process in the same LSI. That is, the ring delay of the ring oscillator (delay for one round of the loop) and the path delay of the critical path have a positive correlation with respect to the fluctuation of the delay due to the process variation.

While the critical path has a small number of logic gates of about 10 to 20 stages, the conventional ring oscillator has a large number of logic gates of several tens to 100 stages. In the ring oscillator, the variation in the individual delays of the logic gates connected in series is canceled by the averaging action over many logic gates, and the variation in the delay in the entire ring oscillator is not so large. On the other hand, in the case of the critical path, since there are not enough stages to cancel the variation in the delay of each logic gate, the variation in the delay in the entire critical path becomes relatively large. In recent years, the variation in semiconductor processes has become larger with the progress of miniaturization, and the correlation between the operating limit frequency of LSI and the oscillation frequency of ring oscillators has become weaker. In order to improve the correlation between the operation limit frequency of the LSI and the oscillation frequency of the ring oscillator, it is preferable to reduce the number of stages of the ring oscillator to the same level as the number of stages of the critical path.

FIG. 1 is a graph showing the correlation between the oscillation frequency of the ring oscillator and the operating limit frequency of the LSI. In FIG. 1, the horizontal axis is the oscillation frequency _{f_ROSC} of the same type of ring oscillator representing the LSI, and the vertical axis is the operation limit frequency _{f_CHIP} of the LSI. When the oscillation frequency of the ring oscillator is measured for a plurality of LSI chips, the oscillation frequency is relatively low in the case of a multi-stage ring oscillator, and the oscillation frequency is distributed within a narrow range as shown as distribution 13. Further, in the case of a ring oscillator having a small number of stages, the oscillation frequency is relatively high, and as shown by the distribution 14, it is distributed in a wide range. The distributions 13 and 14 are auxiliary visual representations of the spread of the frequency distribution on the graph, and are irrelevant to the dimension of the vertical axis (operating limit frequency _{f_CHIP} ). Further, when the operating limit frequency _{f_CHIP} is separately measured for the plurality of LSI chips, the operating limit frequency _{f_CHIP} is distributed within the range shown as the distribution 15. The distribution 15 is an auxiliary visual representation of the spread of the frequency distribution on the graph, and is independent of the dimensions on the horizontal axis (oscillation frequency _{f_ROSC} ).

For each of the distributions 13 and 14, the measured values of the oscillation frequency _{f_ROSC} of the ring oscillator of each LSI and the measured values of the operating limit frequency of the corresponding individual LSIs are used as the coordinate values. Plot the black dots at positions on the coordinate plane. The straight lines 11 and 12 drawn so that the distances from the plurality of points (the plurality of black points in FIG. 1) thus obtained are the closest are the oscillation frequency _{f_ROSC} and the operation limit frequency f for the distributions 13 and 14. It is a straight line showing the correlation with _{_CHIP} . When the number of stages of the ring oscillator in the case of distribution 14 is about the same as the number of stages of the critical path, when comparing the distribution 13 with a large number of stages and the distribution 14 with a small number of stages, the distribution 14 operates with the oscillation frequency _{f_ROSC} . The correlation with the critical frequency _{f_CHIP} becomes large. That is, the error (difference in coordinate position) between each plotted black point and the straight line 11 or 12 becomes small. This is because, as described above, by making the number of stages of the ring oscillator and the number of stages of the critical path the same, the variation in the overall delay becomes the same.

However, if the number of stages of the ring oscillator is reduced, the variation in the ring delay, which is the delay for one round of the loop, increases, so it is suitable for the original purpose of the ring oscillator, "evaluating the gate delay per stage". It will be a circuit that does not exist. When a small number of ring oscillators with large variations in ring delay are used, there is also a problem that the circuit area of the LSI increases, as will be described below.

A typical example of a conventional ring oscillator mounted on an LSI is one in which a single type of logic gate is connected in series from several tens to hundreds of stages (odd number stages). Since the purpose of the ring oscillator is to measure the gate delay of a single logic gate, basically, different types of logic gates are not mixed. Further, since the gate delay per stage is obtained from the delay required for one round of the ring, the number of stages of the ring oscillator is usually one type.

In recent multi-core and many-core microprocessors, the number of transistors to be mounted reaches hundreds of millions of transistors, so ring oscillators are mounted at a plurality of locations in order to follow the variation in the LSI. Specifically, there are about 3 types of logic gates (inverter, NAND, NOR), about 3 types of transistor thresholds (standard, low, high), and about 1 to 4 types of logic gates with different gate lengths and widths. , Prepare a configuration in which the number of fan-outs is about 1 to 4, and the wiring length and width are changed. As a result, a total of about 30 to 50 types of ring oscillators will be prepared as variations. If 30 to 50 types of ring oscillators are set as one set and each set is arranged at, for example, 8 locations (four corners + midpoints of four sides) in the LSI, about 240 to 400 ring oscillators will be mounted on the entire LSI. ..

When determining the correlation between the operation limit frequency of the LSI and the oscillation frequency of the ring oscillator, the number of locations in the LSI for the oscillation frequency of one type of ring oscillator in the above set (8 locations in the above example). Find the mean, median, or minimum over. Using this obtained value as a representative value of the ring oscillator of the type of the LSI, data paired with the operation limit frequency of the LSI is created. The data thus created is plotted for a large number (for example, several hundreds) of LSIs as shown in FIG. 1, and the correlation between the oscillation frequency and the operation limit frequency of the ring oscillator of the type is obtained. Correlation is obtained for each of the plurality of types (30 to 50 types in the above example) of the mounted ring oscillators in this way, and the one having a good correlation is selected from these 30 to 50 types of ring oscillators.

However, when a small number of ring oscillators are used, the variation range of the ring delay is wide, so that the statistical data amount may be insufficient with the number of arrangement locations in the LSI of about eight locations. In particular, when finding the lowest frequency, it is preferable to find the tail value of the normal distribution that approximates the distribution of the measured values, but in order to find the distribution with the normal probability plot, at least about 50 measurement points are required. be.

FIG. 2 is a diagram showing a normal probability plot for the measured value distribution of the oscillation frequency. In FIG. 2, the horizontal axis represents the oscillation frequency _{f_ROSC} of the same type of ring oscillator in the LSI, and the vertical axis represents the values above and below the mean value with reference to the standard deviation. Cumulative percentages were obtained for a large number of measured values of the oscillation frequency _{f_ROSC} having the auxiliary distribution 17, and the percentages of each measured value were plotted on the vertical axis according to the probability of the normal distribution, which are the white circles shown in FIG. Is. The higher the degree of coincidence between the plots of the straight lines 16 drawn so as to be closest to the plurality of plot points obtained in this way and the plots of the white circles, the closer the distribution 17 is to the normal distribution. In the straight line 16 obtained in this way, for example, the lower 3σ (three times the standard deviation) position (black circle 18) is specified, and the oscillation frequency _{f_ROSC} corresponding to this position is set as the minimum value for management purposes. You may set it. As described above, data paired with the operating limit frequency of the LSI is created by using this minimum value as a representative value of the ring oscillator of the type of the LSI.

When the minimum value is calculated as shown in FIG. 2, or when the average value or the median value is calculated by the same method or another method, it is sufficient to give sufficient accuracy to the representative value of the oscillation frequency of the ring oscillator. A large number of measured values are required. However, for example, if each type (30 to 50 types) of ring oscillators is prepared at 50 locations in the LSI, the number of ring oscillators becomes 1500 to 2500. Even if the number of stages of the ring oscillator is smaller than that of the conventional one, the increase in the circuit area occupied by the ring oscillator becomes a problem because the number of ring oscillators is large.

Summarizing the above, a ring oscillator with a small number of stages that has a high correlation with the critical path is not suitable for the purpose of evaluating the gate delay per stage in order to know the frequency rank. Even if a small number of ring oscillators are arranged separately, it is necessary to arrange a large number of them, and the increase in the circuit area becomes a problem.

In addition, which path inside the LSI is the actual critical path cannot be known until the LSI is manufactured. That is, it is unknown how many stages the actual critical path is. Therefore, in order to make the number of stages of the critical path and the number of stages of the ring oscillator equal to each other and increase the correlation, it is preferable that the number of stages of the ring oscillator that contributes to oscillation can be made variable.

Japanese Unexamined Patent Publication No. 2009-252955 Japanese Unexamined Patent Publication No. 2010-109115 Japanese Unexamined Patent Publication No. 11-101852 International Publication No. WO2009 / 08439 Pamphlet

In view of the above, an oscillation circuit capable of separately extracting a large number of oscillation signals having the same or different oscillation frequencies from one ring oscillator is desired.

The oscillation circuit has first to fourth terminals, electrically connects the first terminal and the second terminal, and electrically connects the third terminal and the fourth terminal. A first mode for connecting and a second mode for electrically connecting the first terminal and the third terminal and electrically connecting the second terminal and the fourth terminal. At least one switch circuit that can be set to any of the modes, and a plurality of first signal paths connected in series via the first terminal and the second terminal of the at least one switch circuit. A plurality of second signal paths connected in series via the third terminal and the fourth terminal of the at least one switch circuit, the first signal path and the plurality of first signal paths. The second signal path is connected to each other to form a loop, which loop contains an odd number of inverted logic gates connected in series.

In the oscillation circuit according to at least one embodiment, many oscillation signals having the same or different oscillation frequencies can be separately extracted from one ring oscillator.

It is a graph which shows the correlation between the oscillation frequency of a ring oscillator and the operation limit frequency of an LSI. It is a figure which shows the normal probability plot with respect to the measured value distribution of an oscillation frequency. It is a figure which shows the structure of the 1st Embodiment of a ring oscillator. It is a figure which shows the structural example of the 1st signal path and the 2nd signal path. It is a figure which shows another configuration example of a 1st signal path and a 2nd signal path. It is a figure which shows the structural example of the ring oscillator formed by using a NOR circuit. It is a figure which shows an example of the structure of a BFB switch. It is a figure which shows another example of the structure of a BFB switch. It is a figure which shows still another example of the structure of a BFB switch. It is a figure which shows the plurality of ring oscillators obtained by dividing the ring oscillator of FIG. It is a figure which shows the structure of the 2nd Embodiment of a ring oscillator. It is a figure which shows an example of the structure of an SNC switch. It is a figure which shows another example of the configuration of an SNC switch. It is a figure which shows the plurality of ring oscillators obtained by dividing the ring oscillator by 2nd Example. It is a figure which shows the possibility of oscillation of each loop divided in 1st Example of the ring oscillator shown in FIG. It is a figure which shows the possibility of oscillation of each loop divided in 2nd Example of the ring oscillator shown in FIG. It is a figure which shows the comparison of the circuit area in the case of providing a ring oscillator of a plurality of different stages. It is a figure which shows an example of the structure of the ring oscillator in which different kinds of logic gates are mixed. It is a figure which shows an example of the structure which controls a ring oscillator. It is a flowchart which shows an example of the method of controlling a ring oscillator. It is a figure which shows an example of the structure of a ring oscillator composed only of a NAND circuit. FIG. 21 is a diagram showing an example of a circuit configuration in which the ring oscillator of FIG. 21 is divided by a switch circuit formed by a transfer gate. FIG. 21 is a diagram showing an example of a circuit configuration in which the ring oscillator of FIG. 21 is divided by a switch circuit formed by a NAND circuit. It is a figure which shows the result of having evaluated the degree of variation of a ring oscillator by a simulation. It is a figure which shows another example of the structure of a BFB switch. It is a figure which shows the correspondence relationship between the setting of a control signal and the number of stages in a switch about the BFB switch shown in FIG. 25. It is a figure which shows the number of stages of a 1st signal path and a 2nd signal path when the control signal S is set to high. It is a figure which shows the number of steps of two turn-back paths when the control signal S is set to low. It is a figure which shows the structure of the 3rd Example of a ring oscillator. It is a figure which shows an example of the structure of an SFB switch. It is a figure which shows another example of the structure of an SFB switch. It is a figure which shows still another example of the structure of an SFB switch. It is a figure which shows the possibility of oscillation of each loop divided in the 3rd Example of the ring oscillator shown in FIG. It is a figure which shows an example of the structure of the ring oscillator in which different kinds of logic gates are mixed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In each figure, the same or corresponding components are referred to by the same or corresponding numbers, and the description thereof will be omitted as appropriate.

FIG. 3 is a diagram showing the configuration of the first embodiment of the ring oscillator. The ring oscillator shown in FIG. 3 includes gate chains 20-1 to 20-5, BFB (Bidirectional Fold-Back) switches 21-1 to 21-4, and a plurality of inverters 22.

Each of the gate chains 20-1 to 20-5 includes a first signal path and a second signal path parallel to each other. At least one of the first signal path and the second signal path is a gate chain in which inverting logic gates are connected in series. Each of the gate chains 20-1 to 20-5 has first to fourth terminals T1 to T4, as represented by the gate chain 20-1. In each of the gate chains 20-1 to 20-5, one end of the first signal path is the first terminal T1 and the other end of the first signal path is the second terminal T2. Similarly, one end of the second signal path is the third terminal T3 and the other end of the second signal path is the fourth terminal T4.

FIG. 4 is a diagram showing a configuration example of a first signal path and a second signal path. FIG. 4B shows the gate chain 20 as a representative of any one of the gate chains 20-1 to 20-5. In the gate chain 20, n NAND circuits 31-1 to 31-n (n: an integer of 2 or more) are connected in series between the first terminal T1 and the second terminal T2. A first signal path is provided. Further, a second signal path formed by a signal line not including an inverting logic gate is provided between the third terminal T3 and the fourth terminal T4.

In the gate chain 20 shown in FIG. 4 (b), when the first terminal T1 and the third terminal T3 are directly connected and the second terminal T2 and the fourth terminal T4 are directly connected, FIG. The loop shown in 4 (a) is obtained. If n is odd, this loop can oscillate as a ring oscillator. When the enable signal EN applied to one input of the NAND circuit 31-1 is set to high (hereinafter referred to as "H" in the figure), the ring oscillator oscillates and the enable signal EN is set to low (hereinafter referred to as "" in the figure). When set to L "), the ring oscillator stops oscillating.

FIG. 5 is a diagram showing another configuration example of the first signal path and the second signal path. In the gate chain 20 shown in FIG. 5 (b), i NAND circuits 32-1 to 32 (positive integers smaller than i: n) are located between the first terminal T1 and the second terminal T2. A first signal path formed by connecting −i in series is provided. Further, a second signal path formed by connecting ni NAND circuits 32-i + 1 to 32-n in series is provided between the third terminal T3 and the fourth terminal T4. .. In the gate chain 20 shown in FIG. 5B, when the first terminal T1 and the third terminal T3 are directly connected, and the second terminal T2 and the fourth terminal T4 are directly connected, FIG. The loop shown in 5 (a) is obtained. If n is odd, this loop can oscillate as a ring oscillator.

In the configuration example of the first signal path and the second signal path shown in FIG. 4 or 5, a NOR circuit may be used instead of the NAND circuit. FIG. 6 shows a configuration example of a ring oscillator formed by using NOR circuits 33-1 to 33-n instead of the NAND circuits 32-1 to 32-n shown in FIG.

Furthermore, an inverter may be used instead of the NAND circuit or the NOR circuit to form the first signal path and the second signal path. In this case, in order to provide the control function by the enable signal, it is sufficient to provide the NAND or NOR circuit instead of the inverter at only one place.

Returning to FIG. 3, each of the BFB switches 21-1 to 21-4 has a first terminal U1, a second terminal U2, a third terminal U3, and a fourth terminal U3 as represented by the BFB switch 21. It has a terminal U4. The BFB switches 21-1 to 21-4 can be set to either the first mode or the second mode by the control signals S1 to S4, respectively. In the first mode, the first terminal U1 and the second terminal U2 are electrically connected, and the third terminal U3 and the fourth terminal U4 are electrically connected. In the second mode, the first terminal U1 and the third terminal U3 are electrically connected, and the second terminal U2 and the fourth terminal U4 are electrically connected.

The plurality of first signal paths of the gate chains 20-1 to 20-5 are connected in series via the first terminal U1 and the second terminal U2 of the BFB switches 21-1 to 21-4. Further, the plurality of second signal paths of the gate chains 20-1 to 20-5 are connected in series via the third terminal U3 and the fourth terminal U4 of the BFB switches 21-1 to 21-4.

In FIG. 3, the first terminal T1 and the third terminal T3 of the gate chain 20-1 are directly connected to each other, and the second terminal T2 and the fourth terminal T4 of the gate chain 20-5 are directly connected to each other. Connected to. As a result, the plurality of first signal paths and the plurality of second signal paths are connected to each other so as to form one loop.

The number of inverting logic gates included in the first signal path and the second signal path is set so that the loop includes an odd number of inverting logic gates connected in series. Therefore, in FIG. 3, the loop formed by all the plurality of first signal paths and all the plurality of second signal paths can oscillate as a ring oscillator. Furthermore, it is also possible to divide the entire loop by switching the operation mode of the BFB switches 21-1 to 21-4, and to oscillate each divided partial loop as a ring oscillator. This will be described later.

FIG. 7 is a diagram showing an example of the configuration of BFB switches 21-1 to 21-4. In FIG. 7, any one of the BFB switches 21-1 to 21-4 is shown as the BFB switch 21 on behalf of the BFB switch 21. The BFB switch 21 shown in FIG. 7 (a) includes transfer gates 41 to 44 in which the channel of the polyclonal transistor and the channel of the dichloromethane transistor are connected in parallel with each other.

In the first mode in which the control signal S is high, the transfer gates 41 and 43 are conducted, and as shown in FIG. 7B, the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected. At this time, the transfer gates 42 and 44 are in a non-conducting state. In the second mode in which the control signal S is low, the transfer gates 42 and 44 are conducted, and the first terminal U1 and the third terminal U3 are electrically connected as shown in FIG. 7 (c). The second terminal U2 and the fourth terminal U4 are electrically connected. At this time, the transfer gates 41 and 43 are in a non-conducting state.

FIG. 8 is a diagram showing another example of the configuration of the BFB switches 21-1 to 21-4. The BFB switch 21 shown in FIG. 8A includes NAND circuits 51 to 56.

In the first mode in which the control signal S is high, the NAND circuits 51 and 54 function as inverters, and as shown in FIG. 8B, the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected to each other. At this time, the outputs of the NAND circuits 53 and 56 are fixed at high, and the NAND circuits 52 and 55 also function as inverters. In the second mode in which the control signal S is low, the NAND circuits 53 and 56 function as inverters, and as shown in FIG. 8C, the first terminal U1 and the third terminal U3 are electrically connected. And the second terminal U2 and the fourth terminal U4 are electrically connected to each other. At this time, the outputs of the NAND circuits 51 and 54 are fixed at high, and the NAND circuits 52 and 55 also function as inverters.

FIG. 9 is a diagram showing still another example of the configuration of the BFB switches 21-1 to 21-4. The BFB switch 21 shown in FIG. 9A includes NOR circuits 61 to 66.

In the first mode in which the control signal S is high, the NOR circuits 61 and 64 function as inverters, and as shown in FIG. 9B, the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected to each other. At this time, the outputs of the NOR circuits 63 and 66 are fixed to low, and the NOR circuits 62 and 65 also function as inverters. In the second mode in which the control signal S is low, the NOR circuits 63 and 66 function as inverters, and as shown in FIG. 9C, the first terminal U1 and the third terminal U3 are electrically connected. And the second terminal U2 and the fourth terminal U4 are electrically connected to each other. At this time, the outputs of the NOR circuits 61 and 64 are fixed to low, and the NOR circuits 62 and 65 also function as inverters.

FIG. 10 is a diagram showing a plurality of ring oscillators obtained by dividing the ring oscillator of FIG. 3. In the example of FIG. 10, the control signals S1 to S4 applied to the BFB switches 21-1 to 21-4 are set to high (H), high (H), low (L), and low (L), respectively. ing. The BFB switches 21-1 to 21-4 connect between two adjacent gate chains connected to the switch when the control signal is high. When the control signal is low, the BFB switches 21-1 to 21-4 separate the two adjacent gate chains connected to the switch, and the two of the individual gate chains so as to fold back the signal. Connect between terminals. Therefore, in the example of FIG. 10, the signal propagates as shown by the arrow. That is, focusing only on the gate chain, the gate chains 20-1 to 20-3 form the first loop, the gate chain 20-4 forms the second loop, and the gate chain 20-5 forms the third loop. Form a loop of.

In this case, if each of the gate chains 20-1 to 20-5 contains an odd number of inverting logic gates connected in series, all of the first loop, the second loop, and the third loop described above oscillate. It is possible. Since an even number of inverting logic gates are provided in each signal propagation path of the BFB switches 21-1 to 21-4, the influence of the switch can be ignored in determining whether or not the loop can be oscillated.

Depending on the loop formed, an even number of inversion logic gates may be included, and the loop may not oscillate as a ring oscillator. Further, if the entire loop having an odd number of inverted logic gates in total is formed from an even number of gate chains, at least one gate chain will include an even number of inverted logic gates. Therefore, not all individual gate chains are necessarily gate chains containing an odd number of inverted logic gates. However, when the entire loop is formed from an odd number of gate chains, each gate chain can be configured as a gate chain including an odd number of inverting logic gates.

The NAND or NOR configuration gate chain 20 shown in FIGS. 4 to 6 and the transfer gate, NAND, or NOR configuration BFB switch 21 shown in FIGS. 7 to 9 can be used in any combination. That is, any combination of these circuits can be used to form an oscillator circuit based on the entire loop or the desired partial loop. However, from the viewpoint of accurately measuring the degree of variation, it is preferable that the loop is formed by the same type of logic gate. That is, the plurality of first signal paths and the plurality of second signal paths include only a plurality of first-type logic gates connected in series, and the first to second BFB switches 21-1 to 21-4 are included. It is preferable that the connection path between the terminals U1 to U4 of 4 includes only the first type of logic gate. With such a configuration, it is possible to make the influence of the variation of each logic gate uniform and appropriately evaluate the delay of the logic gate per stage based on the measurement of the oscillation frequency of the ring oscillator.

FIG. 11 is a diagram showing the configuration of a second embodiment of the ring oscillator. The ring oscillators shown in FIG. 3 include gate chains 20-1 to 20-5, BFB switches 21-1 to 21-4, a plurality of inverters 22, and SNC (Stage Number Control) switches 23-1 and 23-. 2 is included.

The configuration of FIG. 11 differs from the configuration of FIG. 3 in that SNC switches 23-1 and 23-2 are provided. The SNC switch 23-1 connects the first terminal T1 and the third terminal T3 of the gate chain 20-1 to each other. The SNC switch 23-2 connects the second terminal T2 and the fourth terminal T4 of the gate chain 20-5 to each other. Each of the SNC switches 23-1 and 23-2 has a first terminal V1 and a second terminal V2, as represented by the SNC switch 23-1.

Each of the SNC switches 23-1 and 23-2 is either a first mode connected via an odd number of inverting logic gates or a second mode connected via an even number of inverting logic gates. Functions as a stage number switching circuit that can be set to. Switching between the first mode and the second mode is performed by the control signals SL and SR. In the configuration example shown in FIG. 11, two SNC switches 23-1 and 23-2 are provided, but only one of them may be provided.

FIG. 12 is a diagram showing an example of the configuration of the SNC switch. In FIG. 12, the SNC switch 23 is shown as a representative of any one of the SNC switches 23-1 and 23-2. The SNC switch 23 includes NAND circuits 71 to 73. The NAND circuit 74 may be a NAND circuit on the input side of the adjacent gate chain. Alternatively, the NAND circuit 74 may also be configured to be included in the SNC switch 23-1. In this case, the output of the NAND circuit 74 becomes the first terminal V1.

When the control signal S is high, the NAND circuit 72 functions as an inverter, and the output of the NAND circuit 73 is fixed to high. At this time, as shown in FIG. 12B, a one-stage inverting logic gate exists in the signal propagation path from the second terminal V2 to the first terminal V1 of the SNC switch 23-1. .. In this case, the NAND circuit 74 also operates as an inverter. Further, the number of stages of the logical inversion gate is not one, but may be another odd number of stages.

When the control signal S is low, the NAND circuits 71 and 73 function as inverters, and the output of the NAND circuit 72 is fixed to high. At this time, as shown in FIG. 12 (c), a two-stage inverting logic gate exists in the signal propagation path from the second terminal V2 to the first terminal V1 of the SNC switch 23-1. .. In this case, the NAND circuit 74 also operates as an inverter. Further, the number of stages of the logical inversion gate is not two, but may be another even number of stages.

FIG. 13 is a diagram showing another example of the configuration of the SNC switch. In FIG. 13, the SNC switch 23 includes NOR circuits 76 to 78. The NOR circuit 79 may be a NOR circuit on the input side of the adjacent gate chain. Alternatively, the NOR circuit 79 may also be configured to be included in the SNC switch 23-1. In this case, the output of the NOR circuit 79 becomes the first terminal V1.

When the control signal S is high, the NOR circuit 77 functions as an inverter, and the output of the NOR circuit 78 is fixed to low. At this time, as shown in FIG. 13B, a one-stage inverting logic gate exists in the signal propagation path from the second terminal V2 to the first terminal V1 of the SNC switch 23-1. .. In this case, the NOR circuit 79 also operates as an inverter.

When the control signal S is low, the NOR circuits 76 and 78 function as inverters, and the output of the NOR circuit 77 is fixed to low. At this time, as shown in FIG. 13 (c), a two-stage inverting logic gate exists in the signal propagation path from the second terminal V2 to the first terminal V1 of the SNC switch 23-1. .. In this case, the NOR circuit 79 also operates as an inverter.

FIG. 14 is a diagram showing a plurality of ring oscillators obtained by dividing the ring oscillator according to the second embodiment. In the example of FIG. 14, the control signals S1 to S4 applied to the BFB switches 21-1 to 21-4 are set to high (H), high (H), low (L), and high (H), respectively. ing. Therefore, in the example of FIG. 10, the signal propagates as shown by the arrow. That is, focusing only on the gate chain, the gate chains 20-1 to 20-3 form the first loop, and the gate chains 20-4 and 20-5 form the second loop.

In the configuration example shown in FIG. 14, each of the gate chains 20-1 to 20-5 includes an odd number of inverted logic gates. In this case, as shown in FIG. 3, in the configuration in which the SNC switches 23-1 and 23-2 are not provided, an even number of inverting logic gates are provided in the second loop consisting of the gate chains 20-4 and 20-5. The second loop will not oscillate as a ring oscillator.

However, in the configuration shown in FIG. 14, the control signals SR and SL applied to the SNC switches 23-1 and 23-2 are set to low (L) and high (H), respectively. Therefore, the number of stages of the inverting logic gate existing in the signal propagation path inside the SNC switch 23-2 becomes one stage, and the second loop including the gate chains 20-4 and 20-5 and the SNC switch 23-2 , An odd-numbered inversion logic gate will be included. As a result, in the configuration shown in FIG. 14, the first loop can oscillate as a ring oscillator, and the second loop can also oscillate as a ring oscillator.

By providing the SNC switches 23-1 and 23-2 in this way, even if there is a partial loop that may include an even number of logical inversion gates depending on how the loop is divided, an odd number of one stage or more is present. A logical inversion gate for the stage can be added. As a result, the loops existing at both ends can always be oscillated as a ring oscillator regardless of how the loop is divided.

FIG. 15 is a diagram showing whether or not oscillation of each loop divided in the first embodiment of the ring oscillator shown in FIG. 3 is possible. In the ring oscillator of the first embodiment, each of the gate chains 20-1 to 20-5 includes an odd number of logical inversion gates. Therefore, each of the gate chains 20-1 to 20-5 can oscillate independently.

In the table shown in FIG. 15, the gate chains 20-1, 20-2, 20-3, 20-4, and 20-5 are designated as C1, C2, C3, C4, and C5, respectively. For example, in the combination of the control signals S1 to S4 shown as the pattern A in the first line, the control signals S1 to S4 are set to "H, H, H, H", respectively, so that all C1 to C5 are connected. One loop is formed. By connecting a plurality of gate chains forming a loop with an addition symbol "+" and displaying them (in this example, "C1 + C2 + C3 + C4 + C5"), these multiple gate chains are connected to form one loop. Shows.

For example, in the combination of the control signals S1 to S4 shown as the pattern B in the second line, the control signals S1 to S4 are set to "H, H, H, L", respectively, so that C1 to C4 are connected. A loop of 1 and a second loop containing only C5 are formed. The first loop "C1 + C2 + C3 + C4" to which C1 to C4 are connected is erased by a strike-through line, which indicates that the first loop cannot oscillate. Further, the second loop "C5" is not displayed as a strikethrough, which indicates that the second loop can oscillate as a ring oscillator. The meaning of this display is the same for all subsequent lines.

In the 16 patterns A to P defined by the combination of the control signals S1 to S4 shown in FIG. 15, when all the loops appearing in each combination are counted, there are 48 in total. Of the 48 loops, 34 loops oscillate as a ring oscillator. The number P of loops appearing in each pattern and the number Q of oscillating loops are shown as "Q / P" in the rightmost column of the table.

Since there are loops having the same gate chain combination among the above 48 loops, there are a total of 15 loops having different gate chain combinations when counted excluding the overlap. Of the 15 loops, 9 loops can oscillate as ring oscillators.

FIG. 16 is a diagram showing whether or not oscillation of each divided loop in the second embodiment of the ring oscillator shown in FIG. 11 is possible. In the ring oscillator of the second embodiment, each of the gate chains 20-1 to 20-5 contains an odd number of logical inversion gates. Therefore, each of the gate chains 20-1 to 20-5 can oscillate independently.

The notation used in the table shown in FIG. 16 is the same as the notation used in FIG. In the 16 patterns A to P defined by the combination of the control signals S1 to S4 shown in FIG. 16, the control signals SL and SR are set so that the loop existing at the left end or the right end always oscillates. If you count all the loops that appear in each combination, there are 48 in total. Of the 48 loops, 44 loops oscillate as a ring oscillator.

Since there are loops having the same gate chain combination among the above 48 loops, there are a total of 15 loops having different gate chain combinations when counted excluding the overlap. Of the 15 loops, 13 loops can oscillate as ring oscillators.

As can be seen by comparing FIGS. 15 and 16, the configuration of the second embodiment shown in FIG. 11 is more oscillating than the configuration of the first embodiment shown in FIG. The number can be significantly increased. That is, by providing SNC switches having a simple circuit configuration at both ends, the oscillation frequency that can be taken out separately can be significantly increased.

According to the above-described embodiment, by incorporating a ring oscillator having a sufficient number of stages into the LSI, it can be used as a ring oscillator for evaluating the delay per stage as in the conventional case. For this purpose, it is preferable to form a ring oscillator with a single type of logic gate.

Furthermore, since the incorporated ring oscillator can be divided and used as a plurality of minor stage ring oscillators, it is possible to measure the oscillation frequency of a ring oscillator having a number of stages corresponding to the number of stages of the critical path. Therefore, it is possible to appropriately evaluate the frequency rank of the LSI.

Further, since many loops among the plurality of loops having a small number of stages formed in this way can be oscillated as separate ring oscillators, there is no need to separately incorporate a large number of independent small number stage ring oscillators, and the circuit The effect of area reduction can be obtained.

As an example, it is assumed that 105-stage ring oscillators are mounted at 10 locations in the LSI, and 50 21-stage ring oscillators are required. Let A be the circuit area required to mount all of these 10 105-stage ring oscillators and 50 21-stage ring oscillators separately. This circuit area A is equal to the circuit area required for 20 105-stage ring oscillators.

On the other hand, in the configuration shown in FIG. 11, each of the gate chains 20-1 to 20-5 can oscillate as a 21-stage ring oscillator, that is, a configuration capable of oscillating as a 105-stage ring oscillator as a whole. Consider the case where there was. It is assumed that the 105-stage ring oscillator is mounted at 10 locations in the LSI. At this time, since each of the 105-stage ring oscillators can be divided and used as five ring oscillators with a small number of stages, the ten 105-stage ring oscillators can be used as 50 21-stage ring oscillators. However, the addition of BFB switches 21-1 to 21-4 and SNC switches 23-1 and 23-2 will increase the area by about 10%, so the total circuit area will be the same as 11 of the original 105-stage ring oscillators. Become. This circuit area is reduced by 45% with respect to the circuit area A described above.

FIG. 17 is a diagram showing a comparison of circuit areas when a plurality of ring oscillators having different numbers of stages are provided. Five different types of ring oscillators with 21 stages, 43 stages, 63 stages, 85 stages, and 105 stages are provided in the LSI at 50, 20, 10, 10, and 10 (100 in total), respectively. And. With this configuration, a total of 100 oscillation signals having 5 different frequencies can be obtained separately. The smaller the number of stages, the wider the range of variation, and more data is required to obtain good statistical values. Therefore, the ring oscillator with a smaller number of stages is configured to have a larger number. In the case of mounting 100 single oscillating ring oscillators in order to obtain the above 100 separate oscillation signals, the number of transistors is shown as "required number of single ROSCs (number of transistors)" in FIG. A total of 17760 transistors are required in terms of conversion.

On the other hand, it is assumed that the ring oscillator of the second embodiment shown in FIG. 11 is used and the gate chains 20-1 to 20-5 have a total of 105 stages. If 10 such ring oscillators are mounted on the LSI, it becomes possible to separately provide a total of 100 oscillation signals having 5 different frequencies, similar to the configuration of the single ring oscillator described above. .. When the ring oscillator of the second embodiment is used, a total of 4680 transistors are required in terms of the number of transistors, as shown in FIG. 17 as the “required number of proposed ROSCs (number of transistors)”. Therefore, the required circuit area is about one-fourth of that in the case of a single configuration. As described above, according to the ring oscillators of the first and second embodiments, even when it is desired to change to a plurality of different stages, it is possible to separately obtain signals having a large number of oscillation frequencies without increasing the circuit area. It will be possible.

In the ring oscillator of the above-described embodiment, it is preferable that the ring oscillator is formed by a single type of logic gate in order to be used for the purpose of evaluating the delay of a single-stage gate. However, not all gate chains need to be the same type of logic gates, and different types of logic gates may be mixed.

FIG. 18 is a diagram showing an example of the configuration of a ring oscillator in which different types of logic gates are mixed. The ring oscillator shown in FIG. 18 has the same configuration as the ring oscillator of the second embodiment shown in FIG. 11, but a plurality of gate chains are formed by different types of logic gates. Further, for convenience of illustration, only three gate chains 20-1 to 20-3 are provided instead of five. As shown in FIG. 18, the gate chains 20-1 to 20-3 are a gate chain formed by a NOR circuit, a gate chain formed by an inverter, and a gate chain formed by a NAND circuit, respectively.

By appropriately setting the control signals S1 and S2 applied to the BFB switches 21-1 and 21-2 and the control signals SL and SR applied to the SNC switches 23-1 and 23-2, various types of logic gates can be combined. The ring oscillator can be oscillated. Specifically, for example, in the pattern P1, it is possible to oscillate a ring oscillator of a NOR circuit, a ring oscillator of an inverter, and a ring oscillator of a NAND circuit. Further, for example, in the pattern P2, it is possible to oscillate a ring oscillator in which a NOR circuit and an inverter are mixed.

In the above-mentioned ring oscillator configuration, the plurality of first signal paths (and / or second signal paths) are at least a signal path in which first-type logic gates are connected in series and a second-type signal path. The logic gate will include a signal path connected in series. Since the critical path may be formed by different types of logic gates, it is possible to perform more accurate delay estimation of the critical path by combining different types of logic gates in this way. Become.

FIG. 19 is a diagram showing an example of a configuration for controlling a ring oscillator. The configuration shown in FIG. 19 includes a ring oscillator 80, a frequency divider 81, and a scan chain 82. The ring oscillator 80 may be, for example, the ring oscillator shown in FIG. 11, and may further include an encoder circuit that selects an output according to an applied signal from the scan chain 82.

The frequency divider 81 selects one of the output terminals OUT1 to OUT5 of the ring oscillator 80 according to the selection control signal SWx supplied from the ring oscillator 80, divides the oscillation signal from the selected output terminal, and divides the frequency. The divided signal is supplied to the output terminal OUT to the next stage. The output terminals OUT1 to OUT5 correspond to the output terminals OUT of the gate chains 20-1 to 20-5 in the case of the configuration of FIG. 11 as an example.

The scan chain 82 is a shift register formed by connecting a plurality of flip-flops in series, and is used to set a control signal to the ring oscillator 80 by a bit pattern sequentially applied bit by bit from the outside. .. The signals set by the scan chain 82 are enable signals EN1 to EN5, switch control signals SW1 to SW4, and control signals SWL and SWR for switching the number of stages. When the configuration of FIG. 11 is taken as an example, these control signals are the enable signal EN of the gate chains 20-1 to 20-5, the control signals S1 to S4 of the BFB switches 21-1 to 21-4, and the SNC switch 23. Corresponds to the control signals SR and SL of -1 and 23-2.

In order to specify one of the output terminals OUT1 to OUT5 by the selection control signal SWx supplied from the ring oscillator 80, the enable signals EN1 to EN5 and the switch control signals SW1 to SW4 are decoded to generate the selection control signal SWx. do it. Specifically, for example, when three gate chains 20-1 to 20-3 are connected to each other as one ring oscillator to oscillate, the output terminal OUT3 (output terminal of the gate chain 20-3) is selected. The selection control signal SWx may be generated and supplied to the frequency divider 81. For this decoding process, the selection control signal SWx may be output from the look-up table in which the enable signals EN1 to EN5 and the switch control signals SW1 to SW4 are input.

Using the configuration of FIG. 19, one of a first mode (a mode for connecting adjacent gate chains) and a second mode (a mode for folding back a signal path) is set for each of the BFB switches. That is, the mode of each BFB switch is set by setting the control signal to a desired value by the scan chain 82. With this setting, the ring oscillator can be divided into a plurality of parts by at least one switch circuit (BFB switch), and the oscillation signal can be supplied to the frequency divider 81. By detecting the output signal from the frequency divider 81 with an external measuring device, the oscillation frequency of one of the plurality of ring oscillators formed by dividing the ring oscillator is measured.

FIG. 20 is a flowchart showing an example of a method of controlling a ring oscillator. In step ST1, the scan chain 82 is made to read the bit pattern of the set signal. In step ST2, the ring oscillator is transmitted by the division pattern of the ring oscillator set according to the bit pattern. In step ST3, the oscillation frequency of the ring oscillator is measured based on the output signal from the frequency divider 81 using an external measuring device. In step ST4, it is determined whether or not the following ring oscillator division and oscillation pattern exist as targets for measuring the oscillation frequency. If the next pattern exists, the process returns to step ST1 and the processes of step ST1 and subsequent steps are repeated.

By the control method described above, the ring oscillator 80 can be set to a desired division pattern, an oscillation signal having a desired oscillation frequency can be extracted from the ring oscillator 80, and measurement can be performed by an external measuring device. As a result, the oscillation frequencies of the ring oscillators having an appropriate number of stages can be measured by an appropriate number, so that the LSI incorporating the ring oscillator 80 can be appropriately evaluated.

In the following, the relationship between the type of logic gate used in the switch circuit that divides the ring oscillator and the error of the oscillation frequency will be described. As described above, in view of the purpose of accurately measuring the degree of variation, it is preferable that the loop is formed by the same type of logic gate. The plurality of first signal paths and the plurality of second signal paths include only a plurality of first-type logic gates connected in series, and the first to fourth BFB switches 21-1 to 21-4. The connection path between the terminals U1 to U4 preferably includes only the first type of logic gate.

FIG. 21 is a diagram showing an example of the configuration of a ring oscillator composed of only a NAND circuit. In the following study, the variation is evaluated for the ring oscillator having the circuit configuration shown in FIG. 21. In the ring oscillator shown in FIG. 21, NAND circuits 91-1 to 91-7 are connected in series to form an oscillation circuit. The outputs of the NAND circuits 91-1 to 91-7 are also applied to the inputs of the NAND circuits 92-2 to 92-7 and 92-1, respectively, and the load is set so that the number of fanouts is 2. ing.

FIG. 22 is a diagram showing an example of a circuit configuration in which the ring oscillator of FIG. 21 is divided by a switch circuit formed by a transfer gate. In FIG. 22, the ring oscillator shown in FIG. 21 is divided into gate chains 20-1 and 20-2, and the BFB switch 21 shown in FIG. 7A is provided between the gate chains 20-1 and 20-2. Has been done. The variation in the oscillation frequency when the entire loop shown in FIG. 22 is oscillated as one ring oscillator will be evaluated in comparison with the variation in the oscillation frequency of the ring oscillator shown in FIG. 21. The comparative evaluation results will be described later.

FIG. 23 is a diagram showing an example of a circuit configuration in which the ring oscillator of FIG. 21 is divided by a switch circuit formed by a NAND circuit. In FIG. 23, the ring oscillator shown in FIG. 21 is divided into two gate chains, and a BFB switch 21 shown in FIG. 8A is provided between the two gate chains. However, in the circuit configuration shown in FIG. 23, a part of the plurality of NAND circuits belonging to the ring oscillator shown in FIG. 21 is diverted and used as the NAND circuit of the BFB switch 21, so that no additional NAND circuit is used. The BFB switch 21 is realized. The variation in the oscillation frequency when the entire loop shown in FIG. 23 is oscillated as one ring oscillator will be evaluated in comparison with the variation in the oscillation frequency of the ring oscillator shown in FIG. 21. The comparative evaluation results are shown below.

FIG. 24 is a diagram showing the results of evaluating the degree of variation of the ring oscillator by simulation. Specifically, the oscillation frequencies of the three ring oscillators shown in FIGS. 21 to 23 were calculated using a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator. At that time, the threshold value of the transistor is set by a random number by Monte Carlo simulation, and the ring delay is set for 2000 ring oscillators in each case where the range of variation (control value) of the threshold value of the transistor model is 1σ, 3σ, 5σ, and 6σ. Calculated. When the control value of the transistor threshold value is 1σ (1 times the standard deviation), it corresponds to the number of transistors included in the LSI being about 100, and the transistor is selected from the transistors in the LSI having a variation of 1σ. A ring oscillator is composed of transistors. When the control value of the transistor threshold is 3σ (three times the standard deviation), it corresponds to the number of transistors in the LSI being about 1000, and the control value of the transistor threshold is 5σ (five times the standard deviation). In this case, the number of transistors in the LSI corresponds to about 5 million. Further, when the control value of the transistor threshold value is 6σ (6 times the standard deviation), it corresponds to the number of transistors in the LSI being about 1 billion. Assuming a plurality of scale LSIs equipped with these quantities of transistors, the ring delay was calculated for 2000 ring oscillators for each, and the median value and standard deviation were obtained.

In the case of the single ring oscillator of FIG. 21 shown as “single ROSC” in FIG. 24, the standard deviation (1σ) of the ring delay in the case of 100 LSIs is 1.06% of the median ring delay. .. The standard deviation (1σ) of the ring delay in the case of 1000 LSIs is 4.83% of the median ring delay. The standard deviation (1σ) of the ring delay for an LSI of 5 million scale is 8.20% of the median ring delay. The standard deviation (1σ) of the ring delay in the case of an LSI of 1 billion scale is 9.97% of the median value of the ring delay. These standard deviation values indicate the degree of variation in ring delay.

The line shown as "BFB1-switch ROSC" in FIG. 24 shows the degree of variation (standard deviation) of the ring delay in the case of the ring oscillator of FIG. 22 and also shows the difference from the variation of the single ROSC. Further, the line shown as "BFB2-switch ROSC" shows the degree of variation (standard deviation) of the ring delay in the case of the ring oscillator of FIG. 23, and also shows the difference from the variation of the single ROSC.

As can be seen from FIG. 24, the degree of variation of the ring oscillator (“BFB1-switch ROSC”) of FIG. 22 is higher than that of the ring oscillator (“single ROSC”) of FIG. 21 for LSIs of all sizes. Further, as the scale of the LSI increases, the difference in variation increases from about 0.1% to about 0.7%. In comparison with this, the degree of variation of the ring oscillator (“BFB2-switch ROSC”) in FIG. 23 is almost the same for LSIs of all sizes. Even if the scale of the LSI is increased, the difference in variation increases to only 0.09%.

As can be seen from the above, there are cases where the switch circuit is divided by the switch circuit (FIG. 7 (a)) formed by the transfer gate and the case where the switch circuit is divided by the switch circuit (FIG. 8 (a)) formed by the NAND circuit. The effect of circuit variation on the ring oscillator is different. When the variation caused by the transfer gate cannot be tolerated, it is preferable to use a switch circuit using a logic gate of the same type as the gate chain as shown in FIGS. 8 (a) and 9 (a).

In the embodiments described so far, the SNC switch 23 is provided with the stage number adjusting function, but the BFB switch 21 is not provided with the stage number adjusting function. In the following, a configuration in which the BFB switch is also provided with a stage number adjustment function will be described.

FIG. 25 is a diagram showing another example of the configuration of the BFB switch. The BFB switch 21A shown in FIG. 25 is a switch circuit that can be used in place of the BFB switch 21, and includes NAND circuits 101 to 109. The NAND circuit 110 may be a NAND circuit on the input side of the adjacent gate chain. Alternatively, the NAND circuit 110 may also be configured to be included in the BFB switch 21A. In this case, the output of the NAND circuit 110 becomes the second terminal U2.

The circuit portions of the NAND circuits 101, 102, and 106 to 109 have the same configuration as the BFB switch 21 shown in FIG. 8 (a). This circuit portion is set to either the first mode or the second mode described above according to the control signal S.

The circuit portion of the NAND circuits 103 to 105 is provided in the portion of the second terminal U2 in order to control the number of stages of the inverting logic gate. In this circuit portion, the number of stages of the inverting logic gate interposed in the signal path is set to either one stage or two stages according to the control signal T. With this configuration, the BFB switch 21A shown in FIG. 25 has either an odd number or an even number of inverting logic gates interposed between the first terminal U1 and the second terminal U2 according to the control signal T. It can be set selectively. Furthermore, the number of inverting logic gates interposed between the second terminal U2 and the fourth terminal U4 can be selectively set to either an odd number or an even number according to the control signal T.

FIG. 26 is a diagram showing the correspondence between the setting of the control signal and the number of internal stages of the switch with respect to the BFB switch shown in FIG. 25. As shown in FIG. 26, when the control signals S and T are set to high and high, the total number of stages in the outward path by the first signal path and the return path by the second signal path is five round trip steps. When the control signals S and T are set to high and low, the total number of stages in the outward path by the first signal path and the return path by the second signal path is 6 round trips.

FIG. 27 is a diagram showing the number of stages of the first signal path and the second signal path when the control signal S is set to high. As shown in FIG. 27 (a), when the control signals S and T are set to high and high, the inverting logic element existing in the first signal path between the first terminal U1 and the second terminal U2. The number of stages is three. At this time, the number of stages of the inverting logic element existing in the second signal path between the fourth terminal U4 and the third terminal U3 is two. Further, as shown in FIG. 27 (b), when the control signals S and T are set to high and low, the inversion logic existing in the first signal path between the first terminal U1 and the second terminal U2. The number of stages of the element is four. At this time, the number of stages of the inverting logic element existing in the second signal path between the fourth terminal U4 and the third terminal U3 is two.

Returning to FIG. 26, when the control signals S and T are set to low and high, the first signal path and the second signal path are separated and folded in the middle, and become two-stage and three-stage folded paths, respectively. .. When the control signals S and T are set to low and low, the first signal path and the second signal path are separated and folded in the middle, and become two-stage and four-stage folded paths, respectively.

FIG. 28 is a diagram showing the number of stages of the two return paths when the control signal S is set to low. As shown in FIG. 28A, when the control signals S and T are set to low and high, the number of stages of the inverting logic element existing in the folding path between the first terminal U1 and the third terminal U3 is There are two stages. At this time, the number of stages of the inverting logic element existing in the folding path between the fourth terminal U4 and the second terminal U2 is three. Further, as shown in FIG. 28 (b), when the control signals S and T are set to low and low, the number of stages of the inverting logic element existing in the folding path between the first terminal U1 and the third terminal U3. Is two steps. At this time, the number of stages of the inverting logic element existing in the folding path between the fourth terminal U4 and the second terminal U2 is four.

As described above, by providing the BFB switch 21 with a stage number adjustment function, it is possible to adjust the stage number for loops other than the loops at both ends. Therefore, for example, even in the combination of "C3 + C4" in the patterns F and N shown in FIG. 16 and the combination of "C2 + C3" in the patterns K and L, the loop can be oscillated as a ring oscillator. That is, it is possible to further increase the number of oscillation signals that can be extracted separately.

FIG. 29 is a diagram showing the configuration of a third embodiment of the ring oscillator. The ring oscillator shown in FIG. 29 includes gate chains 20-1 to 20-5 and SFB (Single Fold-Back) switches 21B-1 to 21B-4.

In the configuration of the third embodiment shown in FIG. 29, the SFB switches 21B-1 to 21B-4 are provided in place of the BFB switches 21-1 to 21-4, that is, the first embodiment shown in FIG. Different from the example configuration. Each of the SFB switches 21B-1 to 21B-4 has first to fourth terminals U1 to U4. In each of the SFB switches 21B-1 to 21B-4, in the first mode, the first terminal U1 and the second terminal U2 are electrically connected, and the third terminal U3 and the fourth terminal U4 are connected to each other. Electrically connect. In the second mode, each of the SFB switches 21B-1 to 21B-4 electrically connects the first terminal U1 and the third terminal U3, and connects the second terminal U2 and the fourth terminal U4. Electrically disconnect from the first and third terminals U1 and U3. By setting the control signals S1 to S4 to desired values, each of the SFB switches 21B-1 to 21B-4 can be set to either the first mode or the second mode.

FIG. 30 is a diagram showing an example of the configuration of SFB switches 21B-1 to 21B-4. In FIG. 30, any one of the SFB switches 21B-1 to 21B-4 is shown as the SFB switch 21B on behalf of the SFB switch 21B-1 to 21B-4. The SFB switch 21B shown in FIG. 30 (a) includes transfer gates 121 to 123 in which the channel of the polyclonal transistor and the channel of the nanotube transistor are connected in parallel with each other.

In the first mode in which the control signal S is high, the transfer gates 122 and 123 are conducted, and as shown in FIG. 30B, the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected. At this time, the transfer gate 121 is in a non-conducting state. In the second mode in which the control signal S is low, the transfer gate 121 is conducted and the first terminal U1 and the third terminal U3 are electrically connected as shown in FIG. 30 (c). .. At this time, the transfer gates 122 and 123 are in a non-conducting state, and the second terminal U2 and the fourth terminal U4 are electrically cut off from the other terminals and also cut off from each other.

FIG. 31 is a diagram showing another example of the configuration of the SFB switches 21B-1 to 21B-4. The SFB switch 21B shown in FIG. 31 (a) includes NAND circuits 131 to 134.

In the first mode in which the control signal S is high, the NAND circuits 131 and 132 function as inverters, and as shown in FIG. 31B, the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected to each other. At this time, the output of the NAND circuit 134 is fixed at high, and the NAND circuit 133 also functions as an inverter. In the second mode in which the control signal S is low, the NAND circuits 133 and 134 function as inverters, and as shown in FIG. 31 (c), the first terminal U1 and the third terminal U3 are electrically connected. Connected to. At this time, the outputs of the NAND circuits 131 and 132 are fixed at high, and the second terminal U2 and the fourth terminal U4 are electrically cut off from the other terminals and also cut off from each other.

FIG. 32 is a diagram showing still another example of the configuration of the SFB switches 21B-1 to 21B-4. The SFB switch 21B shown in FIG. 32 (a) includes NOR circuits 141 to 144. In the first mode in which the control signal S is high, the NOR circuits 141 and 142 function as inverters, and as shown in FIG. 32 (b), the first terminal U1 and the second terminal U2 are electrically connected. And the third terminal U3 and the fourth terminal U4 are electrically connected to each other. At this time, the output of the NOR circuit 144 is fixed to low, and the NOR circuit 143 also functions as an inverter. In the second mode in which the control signal S is low, the NOR circuits 143 and 144 function as inverters, and as shown in FIG. 32 (c), the first terminal U1 and the third terminal U3 are electrically connected. Connected to. At this time, the outputs of the NOR circuits 141 and 142 are fixed to low, and the second terminal U2 and the fourth terminal U4 are electrically cut off from other terminals and also cut off from each other.

FIG. 33 is a diagram showing whether or not oscillation of each divided loop in the third embodiment of the ring oscillator shown in FIG. 29 is possible. In the ring oscillator of the third embodiment, the leftmost gate chain 20-1 among the gate chains 20-1 to 20-5 includes an odd-numbered logical inversion gate, and the other gate chains 20-2 to 20. Each -5 may include an even-numbered logical inversion gate.

The notation used in the table shown in FIG. 33 is the same as the notation used in FIG. In the five patterns A to E defined by the combination of the control signals S1 to S4 shown in FIG. 33, only a single loop including the leftmost gate chain 20-1 is always formed. As shown in FIG. 33, a total of 5 different oscillation frequencies are obtained, and a total of 5 separate oscillation signals, each of which has these oscillation frequencies, are obtained.

In the configuration of the third embodiment of the ring oscillator shown in FIG. 29, the number of oscillation signals obtained separately is smaller than that of the first and second embodiments, and a statistically sufficient number of samples can be obtained. May not be. However, even with the ring oscillator of the third embodiment, it is possible to generate oscillation signals having a plurality of different oscillation frequencies by changing the number of stages of the inverting logic gate. Therefore, even in the ring oscillator of the third embodiment, it is possible to obtain an oscillation signal having a higher correlation with the critical path as compared with the conventional ring oscillator having a fixed oscillation frequency.

Note that Patent Document 1 discloses a ring oscillator having a plurality of oscillation patterns similar to those in the third embodiment. However, in the circuit configuration described in Patent Document 1, the fourth terminal U4 is not cut off from other terminals (particularly the third terminal and the like). That is, the circuit configuration described in Patent Document 1 electrically connects the first terminal U1 and the third terminal U3 in the second mode as in the third embodiment, and is connected to the second terminal U2. The configuration is such that the fourth terminal U4 is electrically disconnected from the first and third terminals U1 and U3.

FIG. 34 is a diagram showing an example of the configuration of a ring oscillator in which different types of logic gates are mixed. The ring oscillator shown in FIG. 34 has the same configuration as the ring oscillator of the third embodiment shown in FIG. 29, but a plurality of gate chains are formed by different types of logic gates. Further, for convenience of illustration, only three gate chains 20-1 to 20-3 are provided instead of five. As shown in FIG. 34, the gate chains 20-1 to 20-3 are a gate chain formed by a NOR circuit, a gate chain formed by an inverter, and a gate chain formed by a NAND circuit, respectively.

By appropriately setting the control signals S1 to S2 applied to the SFB switches 21B-1 to 21B-2, it is possible to oscillate a ring oscillator in which various types of logic gates are combined. Specifically, for example, in the pattern P2, it is possible to oscillate a ring oscillator including a ring oscillator of a NOR circuit and a ring oscillator of an inverter. Since the critical path may be formed by different types of logic gates, it is possible to perform more accurate delay estimation of the critical path by combining different types of logic gates in this way. Become.

Although the present invention has been described above based on the examples, the present invention is not limited to the above examples, and various modifications can be made within the scope of the claims.

20-1 to 20-5 Gate chain 21-1 to 21-4 BFB switch 22 Inverter 23-1, 23-2 SNC switch 80 Ring oscillator 81 Divider 82 Scan chain

Claims (9)

A first terminal having first to fourth terminals, electrically connecting the first terminal and the second terminal, and electrically connecting the third terminal and the fourth terminal. Mode and a second mode in which the first terminal and the third terminal are electrically connected and the second terminal and the fourth terminal are electrically connected. At least one switch circuit that can be set to the mode,
A plurality of first signal paths connected in series via the first terminal and the second terminal of the at least one switch circuit.
A plurality of second signal paths connected in series via the third terminal and the fourth terminal of the at least one switch circuit.
The plurality of first signal paths and the plurality of second signal paths are connected to each other so as to form one loop, and the loop includes an odd number of inverted logic gates connected in series. Oscillation circuit. At least one of the two connection points connecting the plurality of first signal paths and the plurality of second signal paths to each other, the first mode and the even number of connecting points via an odd number of inverting logic gates. The oscillation circuit according to claim 1, further comprising a stage number switching circuit that can be set to any mode of the second mode connected via an inverting logic gate. The oscillation according to claim 1 or 2, wherein the switch circuit can selectively set the number of inverting logic gates interposed between the first terminal and the second terminal to either an odd number or an even number. circuit. The switch circuit is any one of claims 1 to 3, wherein the number of inverting logic gates interposed between the second terminal and the fourth terminal can be selectively set to either an odd number or an even number. Oscillation circuit described in the section. The plurality of first signal paths and the plurality of second signal paths include only a plurality of first-type logic gates connected in series, and are located between the first to fourth terminals of the switch circuit. The oscillation circuit according to any one of claims 1 to 4, wherein the connection path includes only the first type of logic gate. The plurality of first signal paths include any of claims 1 to 4, wherein the plurality of first signal paths include a signal path in which a first type of logic gate is connected in series and a signal path in which a second type of logic gate is connected in series. The oscillation circuit described in item 1. The oscillation circuit according to any one of claims 1 to 6, wherein a plurality of switch circuits are provided. A first terminal having first to fourth terminals, electrically connecting the first terminal and the second terminal, and electrically connecting the third terminal and the fourth terminal. Mode and a second mode in which the first terminal and the third terminal are electrically connected and the second terminal and the fourth terminal are electrically connected. At least one switch circuit that can be set to the mode,
A plurality of first signal paths connected in series via the first terminal and the second terminal of the at least one switch circuit.
A plurality of second signal paths connected in series via the third terminal and the fourth terminal of the at least one switch circuit.
The plurality of first signal paths and the plurality of second signal paths are connected to each other so as to form one loop, and the loop includes an odd number of inverted logic gates connected in series. In the oscillation circuit
For each of the at least one switch circuit, it is specified whether to set the first mode or the second mode.
The loop is divided into a plurality by the at least one switch circuit.
A method for controlling an oscillation circuit including each step of measuring the oscillation frequency of one of a plurality of ring oscillators formed by dividing the loop. A first terminal having first to fourth terminals, electrically connecting the first terminal and the second terminal, and electrically connecting the third terminal and the fourth terminal. And the second mode in which the first terminal and the third terminal are electrically connected and the fourth terminal is electrically disconnected from the first to third terminals. At least one switch circuit that can be set to that mode,
A plurality of first signal paths connected in series via the first terminal and the second terminal of the at least one switch circuit.
A plurality of second signal paths connected in series via the third terminal and the fourth terminal of the at least one switch circuit.
The plurality of first signal paths and the plurality of second signal paths are connected to each other so as to form one loop, and the loop includes an odd number of inverted logic gates connected in series. Oscillation circuit.

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