JPWO2006035711A1 - D / A conversion circuit, display panel drive circuit, and display device - Google Patents

Abstract

An object of the present invention is to provide a D / A, a display panel drive circuit, and a display device that can reduce the occupied area when an IC is formed. According to the present invention, contact pads are provided in a rectangular guard ring region at both ends and in the center, and a plurality of MOS switch transistors are arranged between the contact pads to form a circuit in the IC. An element unit region is formed, and each contact pad at both ends of the unit region receives one of a plurality of analog voltages, and the center contact pad is connected to a predetermined output. Each switch transistor is a switch circuit, and an analog conversion voltage is obtained by selecting ON / OFF of a plurality of switch transistors in the unit area according to data. [Selection] Figure 1

Description

  The present invention relates to a D / A conversion circuit, a display panel drive circuit, and a display device. Specifically, the D / A conversion circuit is provided corresponding to a column pin of the display panel. In a D / A conversion circuit (D / A) that generates a drive voltage or a current that is a source of drive current, when the D / A is integrated into an IC, the occupied area can be greatly reduced, and the number of drive pins relative to the display panel The present invention relates to an improvement in D / A so that a driver having a large number of drivers can be easily realized.

In an organic EL display panel of an organic EL display device mounted on a mobile phone, PHS, DVD player, PDA (mobile terminal device), etc., the number of column lines is 396 (132 × 3) terminal pins (column pins), A row line having 162 terminal pins has been proposed, and the number of column line and row line terminal pins tends to increase further.
As a drive circuit for such an organic EL display panel, the applicant's application in which a D / A is provided corresponding to a column pin is known (Patent Documents 1 and 2). In Patent Document 2, a D / A provided for a column pin receives display data and a reference current, and each D / A D / A converts the display data in accordance with the column pin of the organic EL panel according to the reference current. As a result, a drive current in the column direction or a current that is the source of this drive current is generated.
In the liquid crystal display panel, the number of column pin and row line terminal pins is larger than the above.
JP 2003-234655 A In recent years, the number of drive pins of an organic EL display device tends to increase due to a demand for higher resolution. The currently developed QVGA full color of the organic EL display device has 360 pins of 120 pins for each of R, G, and B, so three drivers are currently required.

By the way, a resistance division type voltage output type D / A built in a drive circuit of a liquid crystal display panel or an organic EL panel is usually a depleted MOS transistor (D-MOS) having a high breakdown voltage (power supply voltage of about 20 V). ) And an enhancement MOS transistor (E-MOS) are connected in series, and an E / D-MOS switch circuit is used.
In this case, as shown in FIG. 6, the D / A 10 includes a reference current generation circuit 1, a selection circuit 2, and a buffer amplifier (voltage follower) 3.
The reference current generating circuit 1 uses 16 resistors R1 to R16 connected in series, and the D / A 10 is connected between the resistors of the reference current generating circuit 1 in the resistor dividing circuit. The selection circuit 2 receives the divided voltage generated. Then, display data of 4 bits D0 to D3 is applied to the selection circuit 2, and the transistor group including a large number of switch circuits of the E / D-MOS of the selection circuit 2 is selectively turned on / off, and the reference voltage One of the divided voltages of the generation circuit 1 is selected and sent to the buffer amplifier 3, and the D / A conversion output voltage Vo is generated at the output terminal 3 a of the buffer amplifier 3.
In the figure, white circles (◯) are E-MOS switch transistors TrE, and black circles (●) are D-MOS switch transistors TrD.
Vin is an external reference input voltage applied to the reference voltage generation circuit 1.
The “H” (= High level) and “L” (= Low level) signals of the display data of 4 bits D0 to D3 input to the selection circuit 2 are supplied to the gates of these transistors via the control signal lines 8a to 8h. Selectively supplied.
Note that a source region and a drain region are respectively formed at predetermined intervals below the gate regions of these transistors to which the control signal lines 8a to 8h are selectively connected (see FIG. 7). , Described later). Reference numerals 9a to 9d denote inverters which are connected to the control signal lines 8a, 8c, 8e and 8g, respectively, and are gate regions to which the control signal lines 8a, 8c, 8e and 8g are connected by inverting the 4 bits D0 to D3. Add to each.
This resistance division type D / A 10 is arranged in the horizontal direction for one of the voltage dividing points of the resistors connected to the control signal lines 8a to 8h according to the display data "H" and "L" of the 4 bits D0 to D3. One column of the switch transistor TrE and the switch transistor TrD selected is turned on at the same time, and one of the voltage at the voltage dividing point of each resistor corresponds to the value of the display data of the 4 bits D0 to D3. select. The voltage at the selected voltage dividing point is applied to the (+) input of the buffer amplifier 3. As a result, D / A conversion is performed, and an analog voltage Vo is generated at the output terminal 3a.

In the selection circuit 2, a range C of a horizontally long rectangular frame indicated by a dotted line is usually one unit area (cell) formed as one of circuit elements in the IC, and includes four E-MOSs and D− A total of eight switch transistor groups of four MOSs are provided in one unit region (cell) C. A guard ring is provided for each unit region C to divide the region, and the unit region C is arranged vertically or horizontally to constitute the D / A selection circuit 2. At both ends of the unit region C, contact pads 6 for wiring are provided.
FIG. 7 is a layout explanatory diagram of one unit region (cell) C in which the switch transistors constituting the D / A selection circuit 2 of FIG. 6 are formed.
In FIG. 7, reference numeral 4 denotes a source / drain formation region, in which the source and / or drain of each transistor is formed between the contact pads 6 at both ends with a predetermined interval corresponding to the gate interval. Is done.
That is, the enhancement MOSTrE (hereinafter referred to as E-MOSTrE) and the depletion MOSTrD (hereinafter referred to as D-MOSTrD) are arranged in the order of source-gate-drain, and the source of the E-MOSTrE and the drain of the next D-MOSTrD are common areas. It is formed as. Alternatively, the drain of the E-MOSTrE and the source of the next D-MOSTrD are formed as a common region.
5e is a gate region of the switch transistor TrE, 5d is a gate region of the switch transistor TrD, and the gate regions 5e and 5d are formed in a strip shape over a predetermined interval for forming the source / drain regions. Since each transistor is a switch MOS, each gate region has a short gate length and a long gate width.
The source / drain formation region 4 is formed as a set of source / drains in a region provided at a predetermined interval between contact pads 6 provided at both ends. Reference numeral 7 denotes a vertically-long rectangular guard ring provided in the IC. The contact pad 6 and each of the switch transistors are formed inside the guard ring 7 to form one unit region (cell) C.
The square points provided in the contact pad 6, the guard ring 7, and the gate regions 5e and 5d are contacts.

Since D / A is provided corresponding to the terminal pins of a liquid crystal display panel or an organic EL panel, an increase in the number of terminal pins of the liquid crystal display panel or the organic EL panel leads to an increase in driver ICs. Increase manufacturing man-hours and price of EL panels. Moreover, recently, the number of D / A bits of the organic EL display device has increased from 6 bits to 6 to 8 bits from the 4-bit configuration, and the area occupied by the D / A in the driver IC tends to increase. Further, the power supply voltage has been reduced to around 15 V due to the demand for lower power consumption.
Therefore, in order to reduce the area occupied by the D / A, it is conceivable to form a switch circuit with a single E-MOS in terms of breakdown voltage. However, as shown in FIG. 7, in one unit region, the contact pad 6 normally occupies an area of about four switch transistors in D / A. Therefore, the ratio of the contact pads 6 and the guard ring 7 to the number of switch transistors in a single IC is relatively large. Therefore, the reduction in the number of MOS transistors does not reduce the occupied area greatly with respect to the occupied area of D / A in one IC.
An object of the present invention is to solve such problems of the prior art, and to provide a D / A capable of greatly reducing the occupation area when an IC is formed.
Another object is to provide a display panel driving circuit and a display device that can easily realize a driver having a large number of drive pins for the display panel.

In order to achieve such an object, the configuration of the D / A, display panel drive circuit or display device of the present invention is a reference for generating a plurality of analog voltages for D / A conversion at each of a plurality of terminals. A voltage generation circuit is provided, and each analog voltage of the reference voltage generation circuit is connected to a predetermined output via a plurality of switch circuits, and the plurality of switch circuits are selectively turned ON / OFF according to data. In a D / A conversion circuit that obtains one of a plurality of analog voltages as an analog conversion voltage to a predetermined output,
Contact pads are provided in the rectangular guard ring region at both ends and in the center, and a plurality of MOS switch transistors are arranged between the contact pads to form a unit region as a circuit element in the IC. Each of the contact pads at both ends of the unit region receives one of a plurality of analog voltages, the central contact pad is connected to a predetermined output, and each switch transistor in the unit region is connected to a switch circuit. An analog conversion voltage is obtained by selecting ON / OFF of a plurality of switch transistors in the unit area according to data.

As described above, in the present invention, two analog voltages can be received from the reference voltage generating circuit in one unit region (if the reference voltage generating circuit is a resistance voltage dividing type), Since two analog voltages (voltage at the voltage dividing point) can be output by one contact pad, the conventional two unit areas become one area. In addition, since one unit area only requires three contact pads, one unit area for two units is increased by one contact pad with respect to two unit areas in total. Since the size is obtained by subtracting one area, the area is smaller than two unit areas, and the total number of unit areas can be reduced to about half.
The increased one contact pad occupies an area of about 4 switch transistors in D / A, and in the D / A conversion circuit, a plurality of unit areas are used according to the number of conversion bits. As the number of conversion bits increases, the present invention can greatly reduce the occupied area.
As a result, the present invention can reduce the occupied area of D / A when it is integrated into an IC, and in particular, the effect of reducing the occupied area of D / A of a driver having a large number of drive pins with respect to the display panel is great. is there.

FIG. 1 is a circuit diagram of a D / A having a 4-bit configuration according to an embodiment to which the D / A of the present invention is applied. FIG. 2 is an explanatory diagram of a layout of one unit region (cell). FIG. FIG. 4 is a circuit diagram of D / A of an embodiment for driving an active matrix type liquid crystal display panel, and FIG. 5 is an active matrix type organic EL panel. It is a circuit diagram of D / A of the Example driven. In addition, in each figure, the same thing as the component shown in FIG. 6, FIG. 7 is shown with the same code | symbol, and the description is omitted.
In FIG. 1, reference numeral 20 denotes a D / A, which includes a reference current generation circuit 1, a selection circuit 11, and a buffer amplifier 3.
The selection circuit 11 is composed of a unit area CE composed of two upper and lower switch circuit groups of E-MOS, and receives ON display data of 4 bits D0 to D3 to selectively turn ON / OFF the E-MOS TrE for switching operation. To do. Three contact pads 6 are provided in a region (cell) CE of one unit formed as one of circuit elements in the IC (see FIG. 2).
The control signal lines 8a to 8h are selected by one row of E-MOS TrEs of switch operation arranged in one horizontal direction of the voltage dividing points of the resistors according to the display data "H" and "L" of the 4 bits D0 to D3. As shown in the figure, each gate region of the E-MOSTrE is selectively connected at a cross connection point (•) so as to be turned on. As a result, one voltage among the voltage dividing points of the resistors is selected and applied to the (+) input of the buffer amplifier 3 to obtain the analog conversion voltage Vo at the output terminal 3a.

FIG. 2 is a layout diagram of a region (cell) CE of one unit.
As shown in FIG. 2, three contact pads 6 are provided at the upper and lower end portions and the central portion. Between these contact pads 6, that is, between one contact pad 6 at the both ends and the center contact pad 6, and between the other contact pad 6 at both ends and the center contact pad 6. Each has four strip-shaped gate regions 12 provided as the gate regions of the switching E-MOSTrE. The gate has a short length and a long width. The source / drain forming regions are provided as 4a and 4b, respectively, between the contact pads 6 provided at both ends and the center, and the source-gate-drain of the E-MOSTrE and the next E-MOSTrE are arranged in order. The source of the MOSTrE and the drain of the next E-MOSTr are formed as a common region. A gate region 12 of each E-MOS TrE is formed between the source and the train at the predetermined intervals. As a result, in the source / drain formation region 4a and the source / drain formation region 4b, four source / drain regions and a gate region of the E-MOS TrE for switching operation are formed, respectively.
Each gate region 12 and contact pad 6 is provided with a contact 13. The contact 13 is connected to one aluminum wiring in the upper aluminum wiring layer.

FIG. 3 is a connection diagram of the aluminum wiring.
Two upper-layer aluminum wirings 14 are allocated so as to be arranged in the length direction (vertical direction) of each strip-shaped gate region 12.
The width of the gate region 12 is, for example, a length L = 1.5 μm, a width W = 3.2 μm, and a gate interval is D = 0.5 μm.
As shown in the figure, the two aluminum wirings 14 in each gate region 12 receive signals at the same digit position in the 4-bit display data (D0 to D3), respectively. As shown in FIG. When one of the two aluminum wirings 14 receives a signal at one digit position (one of D0 to D3) having display data, the other one receives the signal at the same digit position (D0 to D0 through the inverter). D3). Therefore, here, two aluminum wirings 14 are provided in each gate region 12.
As shown in the figure, since the contact 13 is disposed between the two aluminum wirings 14 in each gate region 12, the area at the position of the contact 13 is determined by the contact 13 in any wiring line above and below the aluminum wiring 14. It can be easily and selectively connected to any one of the aluminum wirings 14 by extending to the top. Of course, it may not be connected to a certain gate region 12.
In addition, the connection with the aluminum wiring 14 is such that a part of the contact 13 is overlapped with each part of the two aluminum wirings 14 and under the overlap of the aluminum wiring 14 on the wiring side. Can be made to contact either one of the aluminum wirings 14 at the overlap portion without providing an insulating layer. In the figure, the aluminum wiring 14 and the contact 13 are not connected because they are connected to the gate region of the E-MOSTrE in the region CE of the adjacent unit. Therefore, the connection part is not shown.

Thus, two aluminum wirings 14 are provided for each gate region 12 and selectively connected to the gate region 12. Then, by reducing the contact pad 6 by 1 and making the 2 × unit region (cell) C of FIG. 6 into one unit region (cell) CE, the area of the four switch transistors is increased. The occupied area for the unit area (cell) C can be reduced.
When the contact pad 6 is composed of four transistors and the number of switch transistors is compared with the conventional one, assuming that the area (cell) C of one unit in FIG. The area (cell) CE of the number of transistors of 16 × 2 = 32 is the size of 20 and the occupied area in the IC is reduced by about 38%. Furthermore, since the area (cell) CE of one unit plays the role of the conventional two, the area (cell) of the unit has a higher density if the formation area such as two guard rings is included. This is equivalent to the fact that they are adjacently arranged, and the occupied area is further reduced.
In one D / A, the area (cell) CE of one unit is required to be accumulated times the number of conversion bits of “2” in accordance with the number of digits of conversion data, so that a large occupied area is reduced. In addition to a display panel driving circuit such as a liquid crystal display panel, in particular, in an organic EL driving circuit, the number of terminal pins of the organic EL panel is doubled.

FIG. 4 is an explanatory diagram of a D / A corresponding to FIG. 1 in the case of 6 bits, and relates to a voltage driving circuit for driving an active matrix liquid crystal display panel.
Reference numeral 21 denotes a D / A, which includes a reference current generating circuit 1, a selection circuit 15, and a buffer amplifier 3. The reference current generating circuit 1 is a circuit using a resistor voltage dividing circuit in which 64 resistors R1 to R64 are connected in series. The display data input to the selection circuit 15 is 6 bits D0 to D5.
In the layout diagram corresponding to FIG. 2, the number of E-MOSTrEs between the upper and lower contact pads 6 is increased by 2 each because of the change from 4 bits to 6 bits. Will be omitted.
In the figure, 16 is a driver IC for driving the liquid crystal display panel, 17 is its output terminal pin, 18 is a pixel circuit in the active matrix type liquid crystal display panel, and 18a is a liquid crystal that receives the output voltage of the D / A 21. It is a terminal pin of the display panel 18.
The pixel circuit 18 has an output terminal of a driver IC 16 serving as a source driver when an N-channel MOS transistor TM is turned ON / OFF by a signal (Y line side input) from a gate driver (not shown). A voltage generated at the pin 17 is applied to the liquid crystal cell CL as a load via the terminal pin 18a (X line side input).
FIG. 5 is an explanatory diagram corresponding to FIG. 1 in the case of 6 bits, and relates to a voltage driving circuit for driving an active matrix organic EL panel.
The active matrix type liquid crystal display panel 18 of FIG. 4 is replaced with an active type organic EL panel 180.
Therefore, in the figure, 16 is a driver IC for driving the organic EL panel, 17 is its output terminal pin, 180 is a pixel circuit in the active organic EL panel, and 18a is an active receiving the output voltage of the D / A 21. It is a terminal pin of the type organic EL panel 18. Reference numeral 19 denotes an organic EL element provided in the pixel circuit.
Although there is a difference in the driving operation between the liquid crystal panel and the organic EL panel, the operation as voltage driving is not substantially different, and the description thereof is omitted.

As described above, the reference current generating circuit 1 of the embodiment is of the resistance voltage dividing type. However, in the present invention, the reference current generating circuit 1 has analog voltages for D / A conversion at a number of terminals. Any circuit configuration may be used as long as it is generated at each terminal.
The D / A of the embodiment is a voltage output. For example, by converting a converted output voltage into a current by providing a voltage-current conversion circuit on the output side, the D / A of the current output Of course, A may be used. Accordingly, it is possible to drive the organic EL panel.
In addition, D / A of this invention is not limited to what is applied to an organic EL drive circuit or an organic EL display device.

FIG. 1 is a circuit diagram of a 4-bit D / A according to an embodiment to which the D / A of the present invention is applied. FIG. 2 is an explanatory diagram of the layout of one unit area (cell). FIG. 3 is an explanatory diagram of aluminum wiring for the region (cell) of the unit of FIG. FIG. 4 is a D / A circuit diagram of an embodiment for driving an active matrix liquid crystal display panel. FIG. 5 is a D / A circuit diagram of an embodiment for driving an active matrix organic EL panel. FIG. 6 is an explanatory diagram of a D / A transistor configuration in a conventional organic EL drive circuit. FIG. 7 is a layout explanatory diagram of one unit region (cell) in which the switch transistors constituting the D / A of FIG. 5 are formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Reference voltage generation circuit (resistance voltage dividing circuit), 2, 11, 15 ... Selection circuit,
3. Buffer amp (voltage follower),
4 ... Source / drain formation region,
5e ... gate region of enhancement MOS transistor (E-MOS),
5d: gate region of depletion MOS transistor,
6 ... contact pads, 7 ... guard rings,
8a, 8h ... control signal line, 9 ... inverter,
10, 20, 21 ... D / A conversion circuit (D / A)
12 ... Gate area,
13 ... Contact, 14 ... Aluminum wiring,
16 ... driver IC, 17 ... output terminal pin, 18, 180 ... pixel circuit,
19: Organic EL element, C, CE: Unit region (cell).

Claims (12)

A reference voltage generating circuit for generating a plurality of analog voltages for D / A conversion at each of a plurality of terminals; and each of the analog voltages of the reference voltage generating circuit via a plurality of switch circuits. D / A conversion to obtain one of the plurality of analog voltages as the analog conversion voltage to the predetermined output by selectively connecting the plurality of switch circuits to ON / OFF according to data. In the circuit
Contact pads are provided in the rectangular guard ring region at both ends and in the center, and a plurality of MOS switch transistors are arranged between the contact pads to form a unit region as a circuit element in the IC. The contact pads at both ends of the unit region each receive one of the plurality of analog voltages, and the central contact pad is connected to the predetermined output, A D / A conversion circuit that uses each switch transistor as the switch circuit, and obtains the analog conversion voltage by selecting ON / OFF of the plurality of switch transistors in the unit area according to the data.   The reference voltage generation circuit includes a resistance voltage dividing circuit provided in the IC and having a plurality of resistors connected in series, and the analog voltages are generated according to voltages at a plurality of voltage dividing points. 2. The D / A conversion circuit according to claim 1, wherein a plurality of areas are arranged adjacent to each other in the IC.   3. The buffer amplifier according to claim 2, further comprising a buffer amplifier connected to the predetermined output, wherein the output of the buffer amplifier is an output of the D / A conversion circuit, and the buffer amplifier is provided in the IC. D / A conversion circuit.   4. The D / A conversion circuit according to claim 3, wherein the unit region is formed as a cell having the guard ring, and the MOS transistor is an enhancement MOS transistor. Voltages at a plurality of voltage dividing points of a resistor voltage dividing circuit in which a plurality of resistors are connected in series are respectively connected to a predetermined output via a plurality of switch circuits, and the plurality of switch circuits are selectively selected according to data. In the D / A conversion circuit which obtains the predetermined output as an analog conversion voltage by turning ON / OFF one of the voltages at the plurality of voltage dividing points.
Contact pads are provided in the rectangular guard ring region at both ends and in the center, and a plurality of MOS switch transistors are arranged between the contact pads to form a unit region as a circuit element in the IC. The contact pads at both ends of the unit area receive the voltage of one of the voltage dividing points, respectively, the center contact pad is connected to the predetermined output, and each of the unit areas A D / A conversion circuit that uses each switch transistor as the switch circuit, and obtains the analog conversion voltage by selecting ON / OFF of the plurality of switch transistors in the unit area according to the data.   6. The D / A conversion circuit according to claim 5, wherein a plurality of the unit areas are arranged adjacent to each other in the IC.   The ON / OFF selection of the switch transistor is performed by selecting the plurality of the plurality of the switch transistors between one of the both ends of the unit region and the center contact pad in one of the unit regions arranged adjacent to each other. 7. The D / A conversion circuit according to claim 6, wherein all the switch transistors are turned on in accordance with the data, and all the other other switch transistors are turned off.   8. The D / A conversion circuit according to claim 7, wherein the unit region is formed as a cell having the guard ring, and the MOS transistor is an enhancement MOS transistor.   The plurality of switch transistors have a source formation region, a drain formation region, or a formation region of both of them at one of the contact pads, the center contact pad, and the both ends. A plurality of gate electrodes of each transistor are formed at a predetermined interval between the other contact pad and the center contact pad, and the gate region of each transistor extends over the source region and the drain region at the predetermined interval. It is formed in a strip shape, and a plurality of wiring lines are provided in each upper layer of the gate region of each of the transistors, and the plurality of wiring lines are formed of transistors corresponding to the switch transistors in the gate region or other unit regions. 9. A selective connection to the gate region. Mounting of the D / A converter circuit.   And a buffer amplifier connected to the predetermined output. The output of the buffer amplifier is used as an output of the D / A conversion circuit. The buffer amplifier is provided in the IC. 10. The D / A conversion according to claim 9, wherein one of the wiring lines receives a signal at a certain digit position in the data and the other one receives a signal at the certain digit position via an inverter. circuit.   11. A display panel comprising the D / A conversion circuit according to claim 1 corresponding to a terminal pin of a display panel, wherein a predetermined output of the D / A conversion circuit is provided for driving the display panel. Driving circuit.   A display device comprising the display panel drive circuit according to claim 11 and the display panel.

Images