JP2003323161A - Circuit arrangement of decoder and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arrangement structure of a decoder having m*n pieces of nodes and its fabrication method. <P>SOLUTION: The nodes contain a plurality of transistor nodes and a plurality of channel nodes. The fabrication method of transistor nodes contains the process of forming gates, first source/drain regions and second source/drain regions. The channel nodes are fabricated by forming channels. The channels, the first source/drain regions and the second source/drain regions are formed at the same time by using the same material. Therein, the decoder circuit having narrower width is formed without using an additional mask. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This application incorporates by reference Taiwan Application No. 90101196, filed January 18, 2001.
The present invention relates to a circuit arrangement of a decoder and a method thereof, and more particularly, to a circuit arrangement of a decoder in which the number of masks used and the circuit width are made smaller and a manufacturing method thereof.

[0002]

[Description of Related Art] An LCD (liquid crystal display) has a data driver and a scan driver. The color or image on the display is converted by the following mechanism. First, one of the scan lines that needs to be scanned is defined by the scan driver. Next, all the pixels in one scan line are updated by inputting a data signal from the data driver. For example, color TFT LCD
Taking a (thin film transistor LCD) as an example, each pixel includes three sub-pixels, where a gray scale of each sub-pixel is controlled by a TFT (thin film transistor). The three sub-pixels respectively represent three colors of red, green and blue. Therefore, the color of each pixel is 3 TF
Controlled by T.

FIG. 1 shows the structure of a drive circuit for a color TFT LCD 100. Resolution of color LCD is 1280 pixels x 1
When using 024 lines, 3840 (1280 x
3) Subpixels and TFTs are needed. First, the data driver 106 receives the digital image data D and, at the same time, receives the digital image data D from the DAC.
108 (digital / analog converter, D / A) converts into analog image data. Next, the scan driver 104 selects the scan line 114 (m), and the data of the sub-pixel on the scan line (m) is transferred to the data driver 1.
Update via data line 112 from 06.

In an LCD, each subpixel contains a liquid crystal that determines its transmissivity, which is controlled by the voltage applied to the liquid crystal. When the same polarity voltage is constantly applied to the sub-pixels, the liquid crystal is easily damaged. The transmittance of each sub-pixel is related to the value of the applied voltage, but not the polarity of the applied voltage. Therefore, the above problem of damage can be solved by polarity reversal. FIG. 2 is a circuit configuration diagram based on the DAC 108 in FIG. The DAC 108 includes a plurality of P-type DAC units 202, a plurality of N-type DAC units 204, a plurality of buffer units 206, a switch unit 210,
And 212. The P-type DAC unit 202 has a plurality of PMOSs.
(P-type metal-oxide-semiconductor) and N-type DA
The C unit 204 includes a plurality of NMOSs (N-type metal-oxide-
Semiconductor). These P-type and N-type DAC units are provided alternately and are configured to output different levels of voltage. When the digital image data D of a certain scanning line is input to the DAC unit 108, the digital data D (n) for each sub-pixel is based on the dot conversion method or the column conversion method, and the switch unit 2
It is selected by 10 and input to the P-type DAC unit 202 or the N-type DAC unit 204. When the digital data D (n) is input to the P-type DAC unit 202, the digital data D (n) is converted into the analog signal Vp. When the digital data D (n) is input to the N-type DAC unit 204, the digital data D (n) is converted into an analog signal Vn. After that, the analog signals Vp and Vn are input to the buffer unit 206 and output signals Vp ′ and Vn are input.
n'is generated respectively. Next, switch unit 2
12 outputs these output signals Vp ', Vn' to one of the data lines according to the scheme used by the switch unit 210. For those skilled in the art, the analog signal Vp ′,
It is well known that Vn 'is a voltage with different polarities.

FIG. 3 shows the N-type DAC unit 2 in FIG.
It is a circuit diagram of 04. Here, a 3-bit input is shown and 3-bit digital data D (n) is provided. The N-type DAC unit 204 has a resistance wire Rs.
And an output line OUT and a decoder 302. The two terminals of the resistance line Rs are connected to the voltages Vc and Vd, respectively. The resistance line Rs includes resistors R0 to R6 connected in series.
Consists of. Therefore, eight different voltage levels are supplied from V (0) to V (7).

The decoder 302 includes a plurality of transistor nodes 310 and a channel node 320 arranged in an array.
Consists of. The gates of the transistors in each column of the transistor node 310 are connected to each other, so that B
Input portions of the decoders (0) to B (5) are formed. The source / drain of the transistor Q in each row of the transistor node 310 and the channel node 320 are connected in series, whereby the signal lines L (0) to L (7) are formed.

Referring simultaneously to FIGS. 4A and 4B, these show a circuit diagram of a transistor node 310 including a transistor Q and a circuit diagram of a channel node 320 including a connection line K, respectively. Decoder input section B (0)
~ B (5) are configured to receive digital data D (n). Digital data D (n) b0 ', b0, b1', b
1, b2 ', b2 are respectively decoder input sections B (0) to B (0) -B
Input to (5). Where b0, b1, b2 are b0 ', b1',
This is the inverted data of b2 '. Signal lines L (0) to L (7)
Has an input terminal coupled to the output terminal of the resistance wire Rs. The output terminals of the signal lines L (0) to L (7) are all output lines OUT
Commonly connected to. The output line OUT is configured so that digital data is processed by digital / analog conversion and outputs an analog signal. The voltages V (0) to V (7) output from the resistance line Rs are input to the signal lines L (0) to L (7). The gate of the transistor on the signal line L (i) is
It is controlled by the decoder input section B. When the transistor on the signal line L (i) is turned on, the output line OUT has the voltage V (i).
Is output. During that time, only the transistor on the output line OUT is conducted, and only the input terminal and the output terminal of the signal line L (i) are conducted. Here, 0 ≦ i ≦ 7. For example, the digital data D (n) is 000, and b0 ', b1', b
Since 2'is all 1, only the transistor on the signal line L (0) is turned on. Therefore, the output line OUT outputs the analog signal Vn of the voltage V (0).

FIG. 5 shows the conventional decoder 3 of FIG.
02 shows the circuit layout. The arrangement of each transistor node 310 for the decoder 302 includes a gate 530, a source region 532 and a drain region 534, which correspond to the transistor region. In addition to the gate 530, the source region 532, and the drain region 534, the arrangement of the channel node 320 further includes a doped layer 526, which forms a short circuit between the source region 532 and the drain region 534 of the channel node 320 and keeps the transistor on at all times. Make it conductive. The channel node 320 corresponds to the channel area. 6A to 6E show the signal line L of FIG.
The manufacturing method of (0) is shown. The manufacturing process of the decoder 302 is as follows. A substrate 624 is prepared as shown in FIG. 6A, and then a doped layer 526 is formed in the channel region as shown in FIG. 6B. Next, as shown in FIGS. 6C to 6E, all the transistor nodes 3 of the decoder 302 are
Form transistors on 10 and all channel nodes 320. In FIG. 6C, an oxide layer 628 is formed on the substrate 624. A plurality of gates 530 are formed on the oxide layer 628, as shown in FIG. 6D, and a source region 532 and a drain region 534 are formed in the substrate 624, as shown in FIG. 6E. These gates 530 are connected to the decoder input B. And the channel node 32
The transistor is shorted because there is a doped layer 526 at 0. In this way, the transistor is conductive and is not controlled by the decoder input B. DAC 108 (n) is a P-type DAC unit 202 and N-type
Since it includes the DAC unit 204, it is necessary to form the P-type doped layer and the N-type doped layer individually using two additional masks.

FIG. 7 shows a circuit arrangement of the decoder 302 of FIG. 3 according to another conventional method. The decoder 302 includes a plurality of transistor nodes 310 and a channel node 320 arranged in an array. The arrangement of each transistor node 310 for the decoder 302 includes a gate 730, a source region 732, and a drain region 734, which correspond to the transistor region. Besides the gate 730, the source region 732 and the drain region 734, the arrangement of the channel node 320 further includes a shorting device 736, which is the source region 7 for the channel node 320.
This causes a short circuit between 32 and the drain region 734. The channel node 320 corresponds to the channel area. 8A to 8E show a method of manufacturing the signal line L (0) of FIG. The process of forming transistors in all the transistor nodes and channel nodes of the decoder 302 is as follows. A substrate 824 is prepared as shown in FIG. 8A, and then an oxide layer 828 is formed on the substrate 824 as shown in FIG. 8B. Next, FIG. 8C
A plurality of gates 730 are formed on the oxide layer 828, as shown in FIG. Then, as shown in FIG. 8D, a source region 732 and a drain region 734 are formed in the substrate 824, which completes the transistor arrangement. As shown in FIG. 8E, an insulating layer 838 is formed on the substrate 824 and a metal layer is provided on the insulating layer 838 to provide the short circuit device 736 in the channel region. The first contact 740 and the second contact 742 of the short-circuit device 736 penetrate the insulating layer 838 and are connected to the source region 732 and the drain region 734, respectively. Therefore, a short circuit occurs between the source region 732 and the drain region 734. Furthermore, the gate 730 is connected to the decoder input B and the transistor is always conducting. The shorting device 736 is connected to the source 732 and drain 734 of the transistor in the channel region so that the transistor is not controlled by any of the decoder inputs B.

Although the above-mentioned conventional method does not include the step of forming a doped layer using additional P-type and N-type masks, the short-circuit device 736, the source 732, and the drain 7 are not included.
Since the connection with 34 is made by the contact, DAC
The circuit width of the unit becomes large. Furthermore, using 10 data drivers in one panel would result in 384 DAC units in the data driver, which would increase the overall circuit width of the DAC units.
In the case of a 6-bit DAC unit, the latter conventional method is difficult to implement. When the DAC unit becomes 8 bits,
There is a problem that this data driver becomes too long to be used.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit arrangement of a decoder which can be manufactured with a smaller number of masks and a smaller circuit width, and a manufacturing method thereof. In accordance with the objects of the present invention, a decoder structure having m × n nodes is provided, the nodes including a plurality of transistor nodes and a plurality of channel nodes. Transistor node N (i1, j
1) corresponds to the transistor area A (i1, j1), and the channel node N (i2, j2) corresponds to the channel area A.
(I2, j2), where i1, i2, j1, j2
Satisfies 1 ≦ i1, i2 ≦ m, 1 ≦ j1, j2 ≦ n, i1 ≠ i2, j1 ≠ j2. The decoder structure includes a substrate, a first source / drain region, a second source / drain region, a channel, a first insulating layer, a gate, a second insulating layer, and a metal layer. The first source /
The drain region and the second source / drain region are located on the substrate in the transistor region A (i1, j1). The channels of the channel region A (i2, j2) are provided in the substrate. The first insulating layer covers the first source / drain region, the second source / drain region, and the channel. The gate includes the first source / drain region and the second source / drain region.
It is provided between the drain region and on the first insulating layer. The second insulating layer covers the gate.
The metal layer is located above the gate and electrically connects the gates of the same column to form a decoder input.

When the transistor node N (i1, j1) and the channel node N (i2, j2) are on the same row and are connected to each other, the transistor region A (i1, j1)
The first source / drain region and the second source / drain region of 1) are connected to the channel of the channel region A (i2, j2). The transistor node
Transistor node N (i3, j3) where N (i1, j1) is on the same row
Transistor node N (i1, j1)
Of the first source / drain region or the second source / drain region of the transistor node N (i3, j
3) The first source / drain region or the second
Connected to the source / drain region.

When the channel node N (i2, j2) is close to the channel node N (i4, j4) on the same row,
The channel of the channel node N (i2, j2) is connected to the channel of the channel node N (i4, j4). One end of the node on the same column receives a signal, and the other end is connected to a data line, which is configured to selectively output a signal. The metal layer is configured to electrically connect the gates of the transistor nodes on the same column, thereby forming Y decoder inputs to receive digital signal data.

In accordance with another object of this invention, a method of manufacturing a decoder structure is provided. The decoder includes m signal lines, n decoder inputs, p transistor nodes, and (m * np) channel nodes, where p is an integer less than m * n. is there. First, a substrate is prepared, and an insulating layer is formed on this substrate. Next, p gates are formed on the transistor region. Then, p first source / drain regions and p second source / drain regions are formed on the transistor region, while (m * np) channels are formed in the channel region. Complete the signal lines of the book. Then, a second insulating layer is formed and the metal layer is selectively patterned to form a decoder input. The decoder input is electrically connected to the gate by a plurality of contacts.

The above objects and other advantages of the present invention will become more apparent by describing the preferred embodiments of the present invention in detail with reference to the accompanying drawings.

[0016]

DETAILED DESCRIPTION OF THE INVENTION FIG. 9A illustrates a circuit layout of the decoder 302 of FIG. 3 according to a preferred embodiment of the present invention. The decoder 302 includes 8 * 6 nodes, each node including a plurality of transistor nodes 310 and a plurality of channel nodes 320, which correspond to a transistor region and a channel region, respectively. The circuit arrangement of each transistor node 310 includes a gate, a source, and a drain. Channel node 320 includes a channel. The gates of the transistor nodes on the same column are interconnected to form decoder inputs B (0) -B (5). The transistor node and the channel node in each row are connected in series, and thereby signal lines L (0) to L (7) are formed.

FIG. 9B is a sectional view of the signal line L (0) shown in FIG. 9A. The signal line L (0) has a substrate 924, a first source / drain region 932, and a second source / drain region 9
34, the channel region 936, and the first insulating layer 928.
A gate 930, a second insulating layer 938, and a metal layer 94.
Including 0 and. The first source / drain region 932 and the second source / drain region 934 form the transistor region A.
Substrate 9 at (0,1), A (0,3), A (0,5)
Located within 24. The channel 936 is provided in the substrate 924 in the channel regions A (0,0), A (0,2), A (0,4). A first source / drain region 932, a second source / drain region 934,
The channel 936 is covered with a first insulating layer 928. The gate 930 formed on the first insulating layer 928 is
It is provided between the first source / drain region 932 and the second source / drain region 934. In addition, gate 9
30 is covered with a second insulating layer 938, and a metal layer 940 provided over the second insulating layer 938 is electrically connected to the gate 930.

Transistor node N (0, 1) in the same row
And the channel node N (0,0) are closely connected to each other. The first source / drain region 932 is connected to the channel of the channel region A (0,0). The gate 930 of the transistor node in the same column has a metal layer 94.
Are electrically interconnected by 0 and therefore 6
A number of decoder inputs are formed and configured to receive the data signal D (n).

In the present invention, the transistor node 310
Is manufactured using conventional processes. A gate 930, a first source / drain region 932, and a second source / drain region 934 are sequentially formed. Channel node 3
The manufacture of 20 is completed in the channel forming process. The channel 936, the first source / drain region 932, and the second source / drain region 934 are simultaneously formed without using an additional mask. 10A to 10E are sectional views showing a method of manufacturing the signal line L (0) of the decoder 302 according to the preferred embodiment of the present invention. In FIG. 10A, a substrate 924 is prepared. Next, as shown in FIGS. 10B and 10C, an insulating layer 928 is formed on the substrate 924, and a plurality of gates 930 are formed in the transistor regions A (0,1), A (0,3), A (0 , 5). Referring to FIG. 10D, the channel area A (0,
Since 0), A (0,2), and A (0,4) are not covered by the gate, the channel 936 is directly connected to the channel region.
Formed in the substrate 924 at A (0,0), A (0,2), A (0,4). Therefore, the signal lines L (0) to
L (7) is formed. On the other hand, the channel area A (0,
0), A (0,2), A (0,4) channels are transistor regions A (0,1), A (0,3), A (0,5)
The first source / drain region 932 or the second source /
Each is electrically connected to the drain region 934. Next, referring to FIG. 10E, a metal layer 940 is formed over the substrate 924 and patterned to form decoder inputs B (0) -B (5). The decoder inputs B (0) to B (5) are electrically connected to the gate 930 on the same column by a plurality of contacts 942.

In the present invention, since the channel in the channel region and the source / drain region in the transistor region are formed at the same time, it is not necessary to add P-type and N-type channels as in the conventional method. As a result, the number of masks can be reduced by two in the present invention. Further, the circuit width of the present invention can be reduced without the metal layer forming a short circuit. Therefore, a decoder arrangement with a narrower circuit width can be completed without an additional mask.

From the above disclosure, it will be apparent to those skilled in the art that there are many other features, modifications and improvements. Therefore, such features, modifications, and improvements are considered to be part of the present invention, and the scope of the present invention is defined by the claims.

[Brief description of drawings]

FIG. 1 shows a driving circuit for a color TFT LCD.

FIG. 2 shows a block diagram of a driving circuit of the DAC in FIG.

FIG. 3 shows a conventional circuit diagram of the N-type DAC unit in FIG.

FIG. 4A shows a circuit diagram of a transistor node.

FIG. 4B shows a circuit diagram of a channel node.

5 shows a conventional circuit layout of the decoder in FIG.

6A is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG.

6B is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG.

6C is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG.

6D is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 5.

6E is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG.

FIG. 7 shows another conventional circuit arrangement of the decoder of FIG.

8A is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 7.

8B is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 7.

8C is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 7.

8D is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 7.

8E is a cross-sectional view showing the method of manufacturing the signal line L (0) of FIG. 7.

FIG. 9A shows a circuit layout of the decoder of FIG. 3 according to a preferred embodiment of the present invention.

9B shows a cross-sectional view of the signal line L (0) of FIG. 9A.

FIG. 10A is a cross-sectional view showing the method of manufacturing the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

FIG. 10B is a cross-sectional view showing the method of manufacturing the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

FIG. 10C is a cross-sectional view showing the method of manufacturing the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

FIG. 10D is a cross-sectional view showing the method of manufacturing the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

FIG. 10E is a cross-sectional view showing the method of manufacturing the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/822 H03M 1/76 5J022 27/04 H01L 27/04 F H03M 1/76 (72) Inventor Lin -Kaibu Taiwan, Tainan, Bei Chiu, Xian Street, Lane 103, Array 27, No. 20 (72) Inventor Khun-Cheng Hoon, Taiwan, Xinchu, Gwangfu Road, Sec. 1, lane 476, no. 56,7F (72) Inventor Qian-Ping Chen Taiwan, Tainan, Yunkan City, Junshan S. Road, Lane 902, No. 21-36 F term (reference) 2H092 JA24 JA27 JA28 JA34 JA36 JA41 JA44 2H093 NA31 NA41 NA51 NA61 NC05 NC24 NC34 ND43 ND49 ND52 ND55 ND60 NE03 NE10 5C006 AA22 AF83 BB16 BC02 BC12 BC20 BF34 BF43 EB11 JJ11BB05A05FF11BB02A05FF11 5C080 DD1111 JJ06 5F038 DF01 DF12 DF14 EZ18 EZ20 5J022 AB05 BA00 BA06 CD03 CF07 CG01

Claims (9)

[Claims] 1. A decoder structure having m * n nodes, each node including a plurality of transistor nodes and a plurality of channel nodes, wherein one of the transistor nodes N (i1, j1) is a transistor region. Corresponding to A (i1, j1), the channel node N (i2, j2)
One corresponds to the channel region A (i2, j2), where 1 ≤ i1, i2 ≤ m, 1 ≤ j1, j2 ≤ n, i1 ≠ i2, j1
≠ j2, the decoder structure includes a substrate, a first source / drain region and a second source / drain region formed in the substrate in the transistor region A (i1, j1), and the channel region A ( i2, j2), the channel formed in the substrate, the first source / drain region, the second source / drain region, the first insulating layer formed on the channel, and the first source / drain region. A gate formed on the first insulating layer between the drain region and the second source / drain region, a second insulating layer formed on the gate, and formed on the gate and above the gate. A metal layer electrically connected to the gate, and the transistor node N (i1, j1) is adjacent to the channel node N (i2, j2) on the same row, the transistor region A One of the first source / drain region and the second source / drain region of (i1, j1) is
When the transistor node N (i1, j1) connected to the channel of the channel region A (i2, j2) is adjacent to the transistor node N (i3, j3) on the same row, the transistor node N (i1 , j1), one of the first source / drain region and the second source / drain region is the first of the transistor node N (i3, j3).
If the channel node N (i2, j2) is connected to the source / drain region and one of the second source / drain regions and is adjacent to the channel node N (i4, j4) on the same row, the channel The channel of the node N (i2, j2) is connected to the channel of the channel node N (i4, j4), the metal layer electrically connects the gates of the transistor nodes on the same column, A decoder structure configured to thereby form a plurality of decoder inputs to receive digital signal data. 2. The decoder structure according to claim 1, wherein the first insulating layer is an oxide layer. 3. A method of manufacturing a decoder having m * n nodes, wherein the m * n nodes include p transistor nodes and (m * np) channel nodes. The transistor node corresponds to a transistor region, the channel node corresponds to a channel region,
Here, p is an integer smaller than m * n, and the method includes the steps of providing a substrate, forming an insulating layer on the substrate, and forming p gates on the transistor region. Forming p first source / drain regions and p second source / drain regions on the transistor region and forming m signal lines on the channel region; Forming a layer and forming n decoder inputs on the second insulating layer, the decoder inputs being electrically connected to the gate by a plurality of contacts. 4. The method of claim 3, wherein the first insulating layer is an oxide layer. 5. A decoder structure having a plurality of transistor nodes and a plurality of channel nodes, wherein one of the transistor nodes corresponds to a transistor region and one of the channel nodes corresponds to a channel region, The decoder structure includes a substrate, a transistor provided in the transistor region, the transistor including a gate and a source / drain region, the source / drain region being formed in the base body near the gate; A metal layer provided on the gate and insulated from the substrate; and a channel provided in the substrate in the channel region, wherein the first transistor node of the transistor node comprises:
When connected to the first channel node of the channel nodes on the same row, one of the source / drain regions of the transistor region is connected to the channel of the channel region, and the first transistor of the transistor node is connected. When the node is connected to the second transistor node of the transistor nodes on the same row, one of the source / drain regions of the first transistor node is one of the source / drain regions of the second transistor node. And the first channel node is connected to the second channel node of the channel nodes on the same row, the channel of the first channel node becomes the channel of the second channel node. Connected, said metal layer is Both the one contact, the gate of the transistor nodes on the same column are electrically connected, the decoder structure that is configured to receive the digital signal data to form a plurality of decoders input. 6. The decoder structure according to claim 5, further comprising a first insulating layer provided between the gate and the substrate and configured to electrically insulate the gate and the substrate. 7. The decoder structure of claim 5, further comprising a second insulating layer disposed between the metal layer and the substrate and configured to insulate the metal layer and the substrate. 8. The decoder structure of claim 5, wherein the channel region on the substrate does not include the gate of the transistor. 9. The decoder structure of claim 5, wherein the metal layer of the channel region is electrically insulated in the channel region.