JPS649731B2 - - Google Patents

Info

Publication number
JPS649731B2
JPS649731B2 JP13721581A JP13721581A JPS649731B2 JP S649731 B2 JPS649731 B2 JP S649731B2 JP 13721581 A JP13721581 A JP 13721581A JP 13721581 A JP13721581 A JP 13721581A JP S649731 B2 JPS649731 B2 JP S649731B2
Authority
JP
Japan
Prior art keywords
forward voltage
measured
thyristor
chamber
normal temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13721581A
Other languages
Japanese (ja)
Other versions
JPS5839021A (en
Inventor
Yoshihide Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56137215A priority Critical patent/JPS5839021A/en
Publication of JPS5839021A publication Critical patent/JPS5839021A/en
Publication of JPS649731B2 publication Critical patent/JPS649731B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7865—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To accurately detect the loose contact of the semiconductor device in a short time by a method wherein the forward voltage of the semiconductor device is measured at the normal temperature and a fixed high temperature respectively. CONSTITUTION:A thyristor which was placed on a carrier 9 is sent to a high temperature chamber 11 from a chamber of normal temperature 10. Probes 12 and 13 are provided in the chambers 10 and 11 respectively. First, the forward voltage V1 at the normal temperature is measured by the probe 12 located in the chamber of normal temperature, and the measured value is sent to a memory and arithmetic operational circuit 14 and memorized there. Then, the thyristor is heated up to a fixed high temperature in the heating chamber 11, the forward voltage is measured again using the probe 13, the measured value is sent to the memory and arithmetic operational circuit 14, the differences between V1 and V2 or between V1 and V3 are calculated at the circuit 14, the obtained value is compared with the reference voltage V0 by a comparative judging circuit 15, and if the difference is (V1-V2)>=V0, a decision is given as a non-defective article, and if the difference is (V1-V3)<=V0, a decision is given as a defective article. Through these procedures, a plurality of semiconductor devices can be reliably inspected continuously at a high speed.

Description

【発明の詳細な説明】 この発明は半導体装置のボンデイングワイヤの
接続不良を検出する検査方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection method for detecting poor connection of bonding wires in a semiconductor device.

トランジスタやサイリスタなどの半導体装置は
基板上に半導体ペレツトをマウントし、基板の近
傍に配置したリードと半導体ペレツトの表面の電
極とを金線やアルミニウム線などをワイヤのボン
デイングして電気的に接続した構造が一般的であ
る。このワイヤボンデイングは超音波ボンデイン
グや熱圧着ボンデイングなどで行われ、そのボン
デイング強度はワイヤの破断荷重を測定して行な
われるが、樹脂モールド等により、外装後は実施
できない。また、ワイヤの半導体ペレツトの電極
やリードとの接続部の電気的接続が不十分だと、
長時間の使用時にオーブン不良となることがあ
る。このようなワイヤの接続不十分、いわゆるル
ーズコンタクトは引張り試験などの機械的な方法
で検出することが困難であるため、現在は製造さ
れて製品となつた半導体装置の段階で、順方向電
圧を測定して、その測定値でルーズコンタクトの
有無を判定したり、順方向特性の波形を観測して
ルーズコンタクトを見出す方法で行つている。 Semiconductor devices such as transistors and thyristors are made by mounting semiconductor pellets on a substrate, and electrically connecting leads placed near the substrate and electrodes on the surface of the semiconductor pellet using wire bonding using gold wire, aluminum wire, etc. The structure is common. This wire bonding is performed by ultrasonic bonding, thermocompression bonding, etc., and the bonding strength is determined by measuring the breaking load of the wire, but it cannot be performed after being packaged due to resin molding or the like. Also, if the electrical connection between the wire and the electrode or lead of the semiconductor pellet is insufficient,
The oven may malfunction when used for a long time. Since it is difficult to detect such insufficient wire connections, so-called loose contacts, using mechanical methods such as tensile tests, it is currently difficult to detect forward voltage at the stage of manufacturing semiconductor devices. This is done by measuring and determining whether there is a loose contact based on the measured value, or by observing the waveform of the forward characteristic to find the loose contact.

ところが、半導体装置の順方向電圧は半導体ペ
レツトの不純物拡散状態のバラツキ等の影響で
個々の製品によつてバラツキがあり、この順方向
電圧の測定値からルーズコンタクトを正確に判定
することが難しかつた。また、波形観測も目視に
頼らねばならず、高精度の検出が可能でも、検査
工数が多くて作業性が悪かつた。 However, the forward voltage of semiconductor devices varies depending on the individual product due to the influence of variations in the impurity diffusion state of semiconductor pellets, and it is difficult to accurately determine loose contacts from the measured value of this forward voltage. Ta. In addition, waveform observation had to rely on visual observation, and even if highly accurate detection was possible, the number of inspection steps was large and workability was poor.

本発明はかかる現状に鑑み、半導体装置のルー
ズコンタクトを短時間で、而も高精度に検出する
方法を提供する。以下本発明の方法を例えばサイ
リスタを例にとつて説明する。 In view of the current situation, the present invention provides a method for detecting loose contacts in semiconductor devices in a short time and with high precision. The method of the present invention will be explained below using a thyristor as an example.

製品化されたサイリスタの一例を第１図に示す
と、１は放熱板、２は放熱板１と一体のアノード
リード、３及び４は放熱板１の近傍に位置するカ
ソードリード及びゲートリード、５は放熱板１上
にマウントされたサイリスタのペレツト、６はペ
レツト５のカソード電極とカソードリード３にボ
ンデイングされたワイヤ、７はペレツト５のゲー
ト電極とゲートリード４にボンデイングされたワ
イヤであり、８は外装樹脂材である。いま、この
サイリスタに順方向電流IFGが規定値Ipとなるゲー
ト順方向電圧VFG、すなわちリード３，４間の電
圧を測定すると、各ワイヤ６，７の両端の接続部
がルーズコンタクトのない良品の場合は、各ワイ
ヤ６，７の接続部の抵抗が無視できて、ペレツト
５の拡散状態だけで決まる順方向電圧VFGが求ま
る。 An example of a commercialized thyristor is shown in FIG. 1. 1 is a heat sink, 2 is an anode lead integrated with the heat sink 1, 3 and 4 are cathode leads and gate leads located near the heat sink 1, 5 6 is a wire bonded to the cathode electrode of the pellet 5 and the cathode lead 3, 7 is a wire bonded to the gate electrode of the pellet 5 and the gate lead 4, and 8 is a pellet of the thyristor mounted on the heat sink 1. is the exterior resin material. Now, when we measure the gate forward voltage V FG at which the forward current I FG of this thyristor reaches the specified value I p , that is, the voltage between leads 3 and 4, we find that the connection at both ends of each wire 6 and 7 is a loose contact. In the case of a non-defective product, the resistance at the connection between the wires 6 and 7 can be ignored, and the forward voltage V FG is determined only by the diffusion state of the pellet 5.

これに対して、ルーズコンタクトのある不良品
では、抵抗成分の電圧降下が順方向電圧VFGに加
わる。ここで順方向電圧VFGは負の温度係数を有
するが、抵抗成分は正の温度係数を有する。 On the other hand, in a defective product with loose contacts, a voltage drop due to the resistance component is added to the forward voltage V FG . Here, the forward voltage V FG has a negative temperature coefficient, but the resistance component has a positive temperature coefficient.

つまり、１つのサイリスタの各条件下でのVFG
−IFG特性を第２図のグラフで説明すると、ルー
ズコンタクトの良品及び不良品に対する常温測定
時における規定電流Ipに対するVFGがV1になると
した場合、このサイリスタを一定の高温下で再度
VFGを測定すると定電流Ipに対して良品の場合は
V2（V2＜V1）に、不良品の場合はV3（V2＜V3＜
V1）になる。この不良品のV3はルーズコンタク
トのある部分での抵抗が温度上昇によつて増加
し、この起電力が本来の順方向電圧V2に相加さ
れた結果の値である。このようにして測定された
各順方向電圧V1、V2、V3の夫々の値は製品毎に
多少のバラツキがあるが、その差であるV1−V2
の値やV1−V3の値は製品間においてほぼ一定で
あることが分つた。 That is, V FG under each condition for one thyristor
To explain the −I FG characteristics using the graph in Figure 2, if V FG is V 1 for the specified current I p when measuring good and defective loose contacts at room temperature, then this thyristor is re-operated at a constant high temperature.
When measuring V FG , if it is a good product for constant current I p,
V 2 (V 2 < V 1 ), and V 3 (V 2 < V 3 <
V1 ). The value of V 3 in this defective product is the result of the resistance at a portion of the loose contact increasing due to temperature rise, and this electromotive force being added to the original forward voltage V 2 . The values of the forward voltages V 1 , V 2 , and V 3 measured in this way vary slightly from product to product, but the difference between them is V 1 −V 2
It was found that the values of and the values of V 1 − V 3 are almost constant among products.

本発明はこのV1−V2とV1−V3の差がほぼ一定
であることを利用した検査方法で、例えば第３図
に示す要領で行う。即ち、搬送体９にサイリスタ
を載せて常温室１０から高温加熱室１１へと送
る。一方、この各々の室１０，１１に探針１２，
１３を設置する。そして、まず常温室１０の探針
１２で常温時での順方向電圧V1を測定して、そ
の測定値を記憶・演算回路１４に送つて記憶させ
る。次に、このサイリスタが高温室１１で一定の
高温に加熱されると、探針１３で再度順方向電圧
を求めて、その測定値（V2かV3）を記憶演算回
路１４に送り、ここで先の値V1との差V1−V2或
は差V1−V3を求めて、この差を比較判定回路１
５で基準電圧Vpと比較し、差（V1−V2）≧Vpな
らば良品と判定し、差（V1−V3）＜Vpならば不
要品と判定する。このようにすれば確実に、而も
複数個を高速で連続して検査することができる。 The present invention is an inspection method that utilizes the fact that the difference between V 1 -V 2 and V 1 -V 3 is substantially constant, and is carried out, for example, as shown in FIG. 3. That is, the thyristor is placed on the carrier 9 and sent from the room temperature room 10 to the high temperature heating room 11. On the other hand, a probe 12,
Install 13. First, the forward voltage V 1 at room temperature is measured with the probe 12 in the room temperature room 10, and the measured value is sent to the storage/arithmetic circuit 14 to be stored. Next, when this thyristor is heated to a certain high temperature in the high temperature room 11, the forward voltage is determined again with the probe 13, and the measured value (V 2 or V 3 ) is sent to the memory calculation circuit 14, where it is stored. Find the difference V 1 −V 2 or the difference V 1 −V 3 from the previous value V 1 and compare and judge this difference with the circuit 1.
5, the product is compared with the reference voltage V p , and if the difference (V 1 −V 2 )≧V p , it is determined to be a good product, and if the difference (V 1 −V 3 )<V p , it is determined to be an unnecessary product. In this way, it is possible to reliably and continuously inspect a plurality of items at high speed.

尚、本発明はサイリスタに限らずに、上記特性
を持つ半導体装置ならば全てに適用できる。例え
ば、トランジスタの場合はベース・エミツタ順方
向電圧が常温時と高温時で上記サイリスタと同じ
特性を有するので、このベース・エミツタ順方向
電圧の常温時と高温時の２回の測定で実行でき
る。 Note that the present invention is not limited to thyristors, but can be applied to any semiconductor device having the above characteristics. For example, in the case of a transistor, the base-emitter forward voltage has the same characteristics as the thyristor at room temperature and at high temperature, so the measurement can be performed by measuring the base-emitter forward voltage twice, at room temperature and at high temperature.

以上説明したように、本発明によれば順方向電
圧特性に製品間のバラツキがあつても容易に且つ
正確にルーズコンタクトの有無が検出でき、而も
検査の高速化や自動化が可能となる。 As described above, according to the present invention, the presence or absence of loose contacts can be easily and accurately detected even if there are variations in forward voltage characteristics between products, and inspection can be speeded up and automated.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は半導体装置の一例（サイリスタ）を示
す一部断面平面図、第２図は本発明の検査原理を
説明するための順方向電圧特性グラフ図、第３図
は本発明の方法を実施する装置の一例を示す概略
側面図である。 １……基板（放熱板）、３，４……リード、５
……半導体ペレツト、６，７……ワイヤ。 Fig. 1 is a partial cross-sectional plan view showing an example of a semiconductor device (thyristor), Fig. 2 is a forward voltage characteristic graph for explaining the inspection principle of the present invention, and Fig. 3 is a diagram showing the implementation of the method of the present invention. FIG. 2 is a schematic side view showing an example of a device for 1... Board (heat sink), 3, 4... Lead, 5
...Semiconductor pellet, 6,7...Wire.

Claims (1)

【特許請求の範囲】[Claims] １ ワイヤで半導体ペレツトの電極とリードと電
気的接続した半導体装置の順方向電圧を常温時と
一定の高温時で夫々測定して、その各測定値の差
でもつて前記ワイヤ接続部の良、不良を判定する
ようにしたことを特徴とする半導体装置の検査方
法。1. Measure the forward voltage of a semiconductor device electrically connected to the electrodes and leads of a semiconductor pellet with wires at room temperature and at a constant high temperature, and use the difference between the measured values to determine whether the wire connection is good or bad. 1. A method for testing a semiconductor device, characterized in that:
JP56137215A 1981-08-31 1981-08-31 Inspection of semiconductor device Granted JPS5839021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56137215A JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56137215A JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5839021A JPS5839021A (en) 1983-03-07
JPS649731B2 true JPS649731B2 (en) 1989-02-20

Family

ID=15193473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56137215A Granted JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5839021A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6384132A (en) * 1986-09-29 1988-04-14 Toshiba Corp Method and apparatus for inspecting wire bonding
JP2861423B2 (en) * 1991-02-13 1999-02-24 日本電気株式会社 Inspection method for semiconductor device
JP2800507B2 (en) * 1991-11-14 1998-09-21 富士通株式会社 Diagnostic device and diagnostic method
JP7192620B2 (en) 2019-03-29 2022-12-20 新東工業株式会社 inspection equipment
JP7192621B2 (en) 2019-03-29 2022-12-20 新東工業株式会社 inspection equipment
JP2020165902A (en) 2019-03-29 2020-10-08 新東工業株式会社 Inspection device

Also Published As

Publication number Publication date
JPS5839021A (en) 1983-03-07

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