JPS6489778A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPS6489778A
JPS6489778A JP62244003A JP24400387A JPS6489778A JP S6489778 A JPS6489778 A JP S6489778A JP 62244003 A JP62244003 A JP 62244003A JP 24400387 A JP24400387 A JP 24400387A JP S6489778 A JPS6489778 A JP S6489778A
Authority
JP
Japan
Prior art keywords
converter
video
data
inputted
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62244003A
Other languages
Japanese (ja)
Inventor
Minoru Yoneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62244003A priority Critical patent/JPS6489778A/en
Publication of JPS6489778A publication Critical patent/JPS6489778A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily process a video such as a four divided screen and a noise reduction by dividing a memory area into a time base correcting(TBC) area and a video storing area, further, extracting a vertical synchronization signal from digital data inputted to a D/A converter during the operation of the TBC, and controlling the address counter of the video storing area. CONSTITUTION:A video signal including a jitter is A/D-converted by a clock including the jitter, and inputted to a serial-parallel converter 12. The serial- parallel converter 12 makes four sampling data=32 bits into one block, and transfers the data to an A register 13. The data of a D register 17 are successively transferred block, by block eight blocks are transferred at 8TSC, and inputted to a D/A converter at every sampling data. Further, a vertical synchronization signal detecting circuit 25 detects a vertical synchronization signal from digital data transferred from a parallel-serial converter 18 to the D/A converter 19, and resets an address counter 23 for the video storing.
JP62244003A 1987-09-30 1987-09-30 Video signal processing circuit Pending JPS6489778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244003A JPS6489778A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244003A JPS6489778A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6489778A true JPS6489778A (en) 1989-04-04

Family

ID=17112266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244003A Pending JPS6489778A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6489778A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233881A (en) * 1990-06-27 1992-08-21 Samsung Electron Co Ltd Digital video signal reproducing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233881A (en) * 1990-06-27 1992-08-21 Samsung Electron Co Ltd Digital video signal reproducing circuit

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