JPS648716A - Fet multivibrator circuit - Google Patents

Fet multivibrator circuit

Info

Publication number
JPS648716A
JPS648716A JP62164302A JP16430287A JPS648716A JP S648716 A JPS648716 A JP S648716A JP 62164302 A JP62164302 A JP 62164302A JP 16430287 A JP16430287 A JP 16430287A JP S648716 A JPS648716 A JP S648716A
Authority
JP
Japan
Prior art keywords
fets
source
constitution
sources
constituting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164302A
Other languages
Japanese (ja)
Inventor
Noriyuki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62164302A priority Critical patent/JPS648716A/en
Priority to EP88304948A priority patent/EP0294986B1/en
Priority to DE8888304948T priority patent/DE3873189T2/en
Priority to US07/204,127 priority patent/US4910472A/en
Publication of JPS648716A publication Critical patent/JPS648716A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain high speed and low power consumption by adopting the constitution such that two FETs constituting a source coupled switch and a source follower are operated in the saturating state so as to use FETs. CONSTITUTION:Each source of FETs Q11, Q12 constituting the source coupling switch is connected to a source supply voltage Vss via FETs Q13, Q14 being constant current loads. Moreover, the sources of the FETs Q11, Q12 are connected across a capacitor C1. Drains of the FETs Q11, Q12 are connected to a source supply power VDD via load resistors R11, R12 and a level shift diode D11 and the diodes D12, D13 limit the voltage drop by the resistors R11, R12. Furthermore, the sources of the FETs Q15, Q16 being the components of the source follower are connected to the power supply Vss via the level shift diodes D14, D15 and constant current load FETs Q17, Q18. Thus, the FETs Q11, Q12, Q15 are operated in the saturating region.
JP62164302A 1987-06-09 1987-06-30 Fet multivibrator circuit Pending JPS648716A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62164302A JPS648716A (en) 1987-06-30 1987-06-30 Fet multivibrator circuit
EP88304948A EP0294986B1 (en) 1987-06-09 1988-05-31 Multivibrator circuit employing field effect devices
DE8888304948T DE3873189T2 (en) 1987-06-09 1988-05-31 MULTIVIBRATOR CIRCUIT USING FIELD EFFECT TRANSISTORS.
US07/204,127 US4910472A (en) 1987-06-09 1988-06-06 Multivibrator circuit employing field effect devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164302A JPS648716A (en) 1987-06-30 1987-06-30 Fet multivibrator circuit

Publications (1)

Publication Number Publication Date
JPS648716A true JPS648716A (en) 1989-01-12

Family

ID=15790539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164302A Pending JPS648716A (en) 1987-06-09 1987-06-30 Fet multivibrator circuit

Country Status (1)

Country Link
JP (1) JPS648716A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0810734A2 (en) * 1996-05-31 1997-12-03 Ebrahim Bushehri A loading arrangement for a logic gate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0810734A2 (en) * 1996-05-31 1997-12-03 Ebrahim Bushehri A loading arrangement for a logic gate
EP0810734A3 (en) * 1996-05-31 1999-05-06 Ebrahim Bushehri A loading arrangement for a logic gate

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