KR910017761A - Logic and Semiconductor Integrated Circuits - Google Patents

Abstract

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Description

Logic and Semiconductor Integrated Circuits

Since this is an open matter, no full text was included.

FIG. 1 is a partial basic plan view showing a first embodiment of an NTL circuit and an SPL circuit to which the present invention is applied. FIG. 7 is a detailed circuit diagram showing an embodiment of an NTL circuit according to the basic circuit diagram of FIG. Fig. 3 is a detailed circuit diagram showing a second embodiment of the SPL circuit according to the basic circuit diagram of Fig. 3;

Claims (26)

A phase inversion circuit having a first transistor receiving an input signal, variable impedance means coupled to a collector-emitter path of the first transistor, the impedance of which varies in response to the input signal, and output from the phase inversion circuit And a second transistor coupled to an output terminal, a non-inverted output signal output from the phase inversion circuit, and an active pull-down circuit coupled to an output terminal. 2. The logic circuit of claim 1 wherein the variable impedance means comprises a third transistor receiving the input signal and coupled to the collector-emitter path. 3. The logic circuit of claim 2 wherein the variable impedance means further comprises an impedance element coupled in parallel with the third transistor. 3. The logic circuit of claim 2 wherein the variable impedance means further comprises a unidirectional element coupled in parallel with the third transistor. 4. The logic circuit of claim 3, wherein the variable impedance means further comprises a unidirectional element coupled in series with the impedance element. The logic circuit of claim 5, wherein the impedance element is a resistance element. 5. The logic circuit of claim 4 wherein the unidirectional element is a diode. The logic circuit according to claim 1, further comprising a semiconductor substrate, wherein said logic circuit is formed on said semiconductor substrate. A logic comprising a bipolar transistor receiving a predetermined bi-wall signal at its base and a variable impedance means coupled to the collector-emitter path of the bipolar pansistor, and whose impedance is selectively varied in accordance with the potential level of the input signal. Circuit. 10. The method of claim 9, wherein the variable impedance means is provided in parallel with the level setting means and the level setting means provided between the first power supply terminal to which the first power supply voltage is supplied and the collector of the bipolar transistor. And switching means for selectively turning on depending on the level of the input signal. 11. The logic circuit of claim 10, wherein said level setting means comprises resistance means. 11. The logic circuit of claim 10, wherein said level setting means comprises a diode. 11. The logic circuit of claim 10 wherein the level setting means comprises a diode and resistance means provided in series with the diode. 11. The logic circuit of claim 10 wherein the bipolar transistor comprises an NPN transistor and the switch means comprises a P-channel MOSFET receiving the input signal at its gate. 15. The logic circuit of claim 14, wherein the P-channel MOSFET has a threshold value that corresponds to an intermediate value of an absolute value of a logic amplitude of the input signal. 10. The logic circuit according to claim 9, wherein the logic circuit comprises an acceleration capacitor which is provided as an NTN circuit and in parallel with the emitter load means of the bipolar transistor. 10. The logic circuit of claim 9, wherein the logic circuit comprises an acceleration capacitor which is provided as an SPL circuit and in parallel with the emitter load means of the bipolar transistor. 10. The logic circuit of claim 9 wherein the logic circuit is an ECL circuit. 10. The logic circuit of claim 9, wherein the logic circuit is included in a high speed logic integrated circuit device. 20. The logic circuit according to claim 19, wherein said high speed logic integrated routing device comprises said logic circuit and CMOS circuit which are selectively used in accordance with the frequency of a signal to be transmitted. A logic circuit according to claim 20, wherein said high speed logic integrated circuit device constitutes a high speed computer. A semiconductor integrated circuit device comprising first and second logic circuits selectively used in accordance with the frequency of the signal being transmitted. 23. The semiconductor integrated circuit device according to claim 22, wherein the first logic circuit is an NTL circuit, an SPL circuit, or an ECL circuit, and the second logic circuit is a COMS circuit. 24. The apparatus of claim 23, wherein the NTL circuit, the SPL circuit, and the ECL circuit are provided as collector loads of an input bipolar transistor and further include variable impedance means whose impedance is selectively varied in accordance with the level of the input signal. Semiconductor integrated circuit device. The variable impedance means according to claim 24, wherein the variable impedance means is provided in parallel with the resistance means provided between the first power supply voltage and the collector of the input bipolar transistor and the resistance means receives the input signal at the gate thereof. Semiconductor integrated circuit device comprising a p-channel MOSFET. An input terminal to which an input signal is to be supplied, an output terminal to which an output signal is to be supplied, first and second power terminals to which first and second power supply voltages are to be supplied, a base coupled to the input terminal, and the output A bipolar transistor having a collector coupled to a terminal, the first power supply terminal coupled between the collector of the bipolar transistor, the impedance having a first value when the bipolar transistor is to be in a conductive state, and the bipolar transistor being Variable impedance means controlled to have a second value whose impedance is lower than the first value when the signal is to be in a non-conductive state, and an emitter coupled between the emitter of the bipolar transistor and the second power supply terminal. Logic circuit comprising a load means. ※ Note: This is to be disclosed by the original application.