JPS6486770A - Sub picture display circuit - Google Patents

Abstract

PURPOSE:To prevent the zigzagged jitter of the vertical line of a sub picture from being generated by detecting the phases of the trailing edge of a horizontal synchronizing signal on the sub picture and the leading edge of a clock synchronizing with a main picture, performing the one horizontal line delay of a detecting signal, detecting an inflection point by performing phase comparison between a preceding line and the present line, and integrating a detected result. CONSTITUTION:At a sample and hold circuit 104, the delay of one horizontal scanning period of information supplied from an integrator 103 is performed setting the leading edge of a sub picture synchronizing signal supplied to an input terminal 101 as a sample pulse. One is added on an integrator 108 when output is generated in a trailing edge detector 107, and one is subtracted from it when the output is generated in a leading edge detector 106. And the image signal of the sub picture is quantized by an A/D converter 117, and is supplied to the data input terminal of a memory 114. Readout from the memory 114 is controlled by a memory readout control circuit 112 synchronizing with the main picture, and it is possible to realize the sub picture without having the jitter by displaying the sub picture in the displaying period of the main picture.